verilog使用1bit全加器实现4bit全加器【行波进位法】_4比特全加器

 行波加法器的电路图构成

module adder4bit(
    input     [3:0]    a,
    input     [3:0]    b,
    input             c_in,
    output    [3:0]    sum,
    output            c_out
);
wire c1, c2, c3;
 
adder1bit a1(a[0],b[0],c_in,sum[0],c1);
adder1bit a1(a[1],b[1],c1,sum[1],c2);
adder1bit a1(a[2],b[2],c2,sum[2],c3);
adder1bit a1(a[3],b[3],c3,sum[3],c_out);
 
endmodule
 
module adder1bit(
input a,
input b,
input c_in,
output sum,
output c_out
); 
 
assign sum = a ^ b ^ c_cin;
assign c_out = (a & b) + (a ^ b) & c_cin;
 
endmodule