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Zynq-Linux移植学习笔记之34-使用PCS/PMA IP核配置网络

作者：2023面试高手 | 2024-02-14 21:10:48

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pma ip

1、硬件设计

设计图如下，zynq PS ETH1连接PCS/PMA IP核。

这里PCS/PMA IP核相当于PHY，外部通过PCB连接到光模块。IP核的对应配置如下：

上面重要的部分是PHY的地址1.

 

2、uboot设计

在uboot中启用双网卡，需要修改zynq-common.h和zynq-zc70x.h两个配置文件

首先在zynq-zc70x.h中增加GEM1并且设置PHY地址为1

 

然后修改zynq-common.h文件，增加CONFIG_HAS_ETH1并设置eth1addr环境变量地址

在zynq_gem.c中增加针对不同网卡的配置

 

源码如下

  1. /*
  2.  * (C) Copyright 2011 Michal Simek
  3.  *
  4.  * Michal SIMEK <monstr@monstr.eu>
  5.  *
  6.  * Based on Xilinx gmac driver:
  7.  * (C) Copyright 2011 Xilinx
  8.  *
  9.  * SPDX-License-Identifier:	GPL-2.0+
  10.  */
  11.  
  12. #include <common.h>
  13. #include <net.h>
  14. #include <config.h>
  15. #include <malloc.h>
  16. #include <asm/io.h>
  17. #include <phy.h>
  18. #include <miiphy.h>
  19. #include <watchdog.h>
  20. #include <asm/arch/hardware.h>
  21. #include <asm/arch/sys_proto.h>
  22.  
  23. /* Bit/mask specification */
  24. #define ZYNQ_GEM_PHYMNTNC_OP_MASK	0x40020000 /* operation mask bits */
  25. #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK	0x20000000 /* read operation */
  26. #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK	0x10000000 /* write operation */
  27. #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK	23 /* Shift bits for PHYAD */
  28. #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK	18 /* Shift bits for PHREG */
  29.  
  30. #define ZYNQ_GEM_RXBUF_EOF_MASK		0x00008000 /* End of frame. */
  31. #define ZYNQ_GEM_RXBUF_SOF_MASK		0x00004000 /* Start of frame. */
  32. #define ZYNQ_GEM_RXBUF_LEN_MASK		0x00003FFF /* Mask for length field */
  33.  
  34. #define ZYNQ_GEM_RXBUF_WRAP_MASK	0x00000002 /* Wrap bit, last BD */
  35. #define ZYNQ_GEM_RXBUF_NEW_MASK		0x00000001 /* Used bit.. */
  36. #define ZYNQ_GEM_RXBUF_ADD_MASK		0xFFFFFFFC /* Mask for address */
  37.  
  38. /* Wrap bit, last descriptor */
  39. #define ZYNQ_GEM_TXBUF_WRAP_MASK	0x40000000
  40. #define ZYNQ_GEM_TXBUF_LAST_MASK	0x00008000 /* Last buffer */
  41.  
  42. #define ZYNQ_GEM_NWCTRL_TXEN_MASK	0x00000008 /* Enable transmit */
  43. #define ZYNQ_GEM_NWCTRL_RXEN_MASK	0x00000004 /* Enable receive */
  44. #define ZYNQ_GEM_NWCTRL_MDEN_MASK	0x00000010 /* Enable MDIO port */
  45. #define ZYNQ_GEM_NWCTRL_STARTTX_MASK	0x00000200 /* Start tx (tx_go) */
  46.  
  47. #define ZYNQ_GEM_NWCFG_SPEED100		0x000000001 /* 100 Mbps operation */
  48. #define ZYNQ_GEM_NWCFG_SPEED1000	0x000000400 /* 1Gbps operation */
  49. #define ZYNQ_GEM_NWCFG_FDEN		0x000000002 /* Full Duplex mode */
  50. #define ZYNQ_GEM_NWCFG_FSREM		0x000020000 /* FCS removal */
  51. #define ZYNQ_GEM_NWCFG_MDCCLKDIV	0x000080000 /* Div pclk by 32, 80MHz */
  52. #define ZYNQ_GEM_NWCFG_MDCCLKDIV2	0x0000c0000 /* Div pclk by 48, 120MHz */
  53.  
  54. #define ZYNQ_GEM_NWCFG_INIT		(ZYNQ_GEM_NWCFG_FDEN | \
  55. 					ZYNQ_GEM_NWCFG_FSREM | \
  56. 					ZYNQ_GEM_NWCFG_MDCCLKDIV)
  57.  
  58. #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK	0x00000004 /* PHY management idle */
  59.  
  60. #define ZYNQ_GEM_DMACR_BLENGTH		0x00000004 /* INCR4 AHB bursts */
  61. /* Use full configured addressable space (8 Kb) */
  62. #define ZYNQ_GEM_DMACR_RXSIZE		0x00000300
  63. /* Use full configured addressable space (4 Kb) */
  64. #define ZYNQ_GEM_DMACR_TXSIZE		0x00000400
  65. /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
  66. #define ZYNQ_GEM_DMACR_RXBUF		0x00180000
  67.  
  68. #define ZYNQ_GEM_DMACR_INIT		(ZYNQ_GEM_DMACR_BLENGTH | \
  69. 					ZYNQ_GEM_DMACR_RXSIZE | \
  70. 					ZYNQ_GEM_DMACR_TXSIZE | \
  71. 					ZYNQ_GEM_DMACR_RXBUF)
  72.  
  73. /* Use MII register 1 (MII status register) to detect PHY */
  74. #define PHY_DETECT_REG  1
  75.  
  76. /* Mask used to verify certain PHY features (or register contents)
  77.  * in the register above:
  78.  *  0x1000: 10Mbps full duplex support
  79.  *  0x0800: 10Mbps half duplex support
  80.  *  0x0008: Auto-negotiation support
  81.  */
  82. #define PHY_DETECT_MASK 0x1808
  83.  
  84. /* TX BD status masks */
  85. #define ZYNQ_GEM_TXBUF_FRMLEN_MASK	0x000007ff
  86. #define ZYNQ_GEM_TXBUF_EXHAUSTED	0x08000000
  87. #define ZYNQ_GEM_TXBUF_UNDERRUN		0x10000000
  88.  
  89. /* Clock frequencies for different speeds */
  90. #define ZYNQ_GEM_FREQUENCY_10	2500000UL
  91. #define ZYNQ_GEM_FREQUENCY_100	25000000UL
  92. #define ZYNQ_GEM_FREQUENCY_1000	125000000UL
  93.  
  94. /* Device registers */
  95. struct zynq_gem_regs {
  96. 	u32 nwctrl; /* Network Control reg */
  97. 	u32 nwcfg; /* Network Config reg */
  98. 	u32 nwsr; /* Network Status reg */
  99. 	u32 reserved1;
  100. 	u32 dmacr; /* DMA Control reg */
  101. 	u32 txsr; /* TX Status reg */
  102. 	u32 rxqbase; /* RX Q Base address reg */
  103. 	u32 txqbase; /* TX Q Base address reg */
  104. 	u32 rxsr; /* RX Status reg */
  105. 	u32 reserved2[2];
  106. 	u32 idr; /* Interrupt Disable reg */
  107. 	u32 reserved3;
  108. 	u32 phymntnc; /* Phy Maintaince reg */
  109. 	u32 reserved4[18];
  110. 	u32 hashl; /* Hash Low address reg */
  111. 	u32 hashh; /* Hash High address reg */
  112. #define LADDR_LOW	0
  113. #define LADDR_HIGH	1
  114. 	u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */
  115. 	u32 match[4]; /* Type ID1 Match reg */
  116. 	u32 reserved6[18];
  117. 	u32 stat[44]; /* Octects transmitted Low reg - stat start */
  118. };
  119.  
  120. /* BD descriptors */
  121. struct emac_bd {
  122. 	u32 addr; /* Next descriptor pointer */
  123. 	u32 status;
  124. };
  125.  
  126. int net_base_addr;
  127.  
  128. #define RX_BUF 3
  129. /* Page table entries are set to 1MB, or multiples of 1MB
  130.  * (not < 1MB). driver uses less bd's so use 1MB bdspace.
  131.  */
  132. #define BD_SPACE	0x100000
  133. /* BD separation space */
  134. #define BD_SEPRN_SPACE	64
  135.  
  136. /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
  137. struct zynq_gem_priv {
  138. 	struct emac_bd *tx_bd;
  139. 	struct emac_bd *rx_bd;
  140. 	char *rxbuffers;
  141. 	u32 rxbd_current;
  142. 	u32 rx_first_buf;
  143. 	int phyaddr;
  144. 	u32 emio;
  145. 	int init;
  146. 	struct phy_device *phydev;
  147. 	struct mii_dev *bus;
  148. };
  149.  
  150. static inline int mdio_wait(struct eth_device *dev)
  151. {
  152. 	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
  153. 	u32 timeout = 20000;
  154.  
  155. 	/* Wait till MDIO interface is ready to accept a new transaction. */
  156. 	while (--timeout) {
  157. 		if (readl(&regs->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
  158. 			break;
  159. 		WATCHDOG_RESET();
  160. 	}
  161.  
  162. 	if (!timeout) {
  163. 		printf("%s: Timeout\n", __func__);
  164. 		return 1;
  165. 	}
  166.  
  167. 	return 0;
  168. }
  169.  
  170. static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
  171. 							u32 op, u16 *data)
  172. {
  173. 	u32 mgtcr;
  174. 	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
  175.  
  176. 	if (mdio_wait(dev))
  177. 		return 1;
  178.  
  179. 	/* Construct mgtcr mask for the operation */
  180. 	mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
  181. 		(phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
  182. 		(regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK)| *data;
  183.  
  184. 	/* Write mgtcr and wait for completion */
  185. 	writel(mgtcr, &regs->phymntnc);
  186.  
  187. 	if (mdio_wait(dev))
  188. 		return 1;
  189.  
  190. 	if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
  191. 		*data = readl(&regs->phymntnc);
  192.  
  193. 	return 0;
  194. }
  195.  
  196. static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
  197. {
  198. 	return phy_setup_op(dev, phy_addr, regnum,
  199. 				ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
  200. }
  201.  
  202. static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
  203. {
  204. 	return phy_setup_op(dev, phy_addr, regnum,
  205. 				ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
  206. }
  207.  
  208. #ifndef CONFIG_PHYLIB
  209. static int phy_rst(struct eth_device *dev)
  210. {
  211. 	struct zynq_gem_priv *priv = dev->priv;
  212. 	u16 tmp;
  213. 	phyread(dev, priv->phyaddr, 0, &tmp);
  214. 	tmp |= 0x8000;
  215. 	phywrite(dev, priv->phyaddr, 0, tmp);
  216.  
  217. 	phyread(dev, priv->phyaddr, 0, &tmp);
  218. 	while (tmp & 0x8000) {
  219. 		putc('.');
  220. 		if (ctrlc())
  221. 			return 1;
  222. 		phyread(dev, priv->phyaddr, 0, &tmp);
  223. 	}
  224. 	puts("\nPHY reset complete.\n");
  225. 	return 0;
  226. }
  227. #endif
  228.  
  229. static void phy_negotiat(struct eth_device *dev)
  230. {
  231. 	struct zynq_gem_priv *priv = dev->priv;
  232. 	u16 control;
  233. 	u16 status;
  234. 	u16 temp;
  235. 	u16 timeout_counter=0;
  236. 	
  237. 	phywrite(dev,priv->phyaddr, 22, 2);
  238. 	phyread(dev, priv->phyaddr, 21, &control);
  239. 	control |= 0x0030;
  240. 	phywrite(dev, priv->phyaddr, 21, control);
  241.  
  242. 	phywrite(dev, priv->phyaddr, 22, 0);
  243.  
  244. 	phyread(dev, priv->phyaddr, 4, &control);
  245. 	control |= 0x0800;
  246. 	control |= 0x0400;
  247. 	control |= (0x0100 | 0x0080);
  248. 	control |= (0x0040 | 0x0020);
  249. 	phywrite(dev, priv->phyaddr, 4, control);
  250.  
  251. 	phyread(dev, priv->phyaddr, 9,&control);
  252. 	control |= 0x0300;
  253. 	phywrite(dev, priv->phyaddr, 9,control);
  254.  
  255. 	phywrite(dev, priv->phyaddr, 22, 0);
  256. 	phyread(dev, priv->phyaddr, 16,&control);
  257. 	control |= (7 << 12);	/* max number of gigabit attempts */
  258. 	control |= (1 << 11);	/* enable downshift */
  259. 	phywrite(dev, priv->phyaddr, 16,control);
  260. 	phyread(dev, priv->phyaddr, 0, &control);
  261. 	control |= 0x1000;
  262. 	control |= 0x0200;
  263. 	phywrite(dev, priv->phyaddr, 0, control);
  264.  
  265. 	phyread(dev, priv->phyaddr, 0, &control);
  266. 	control |= 0x8000;
  267. 	phywrite(dev, priv->phyaddr, 0, control);
  268.  
  269. 	while (1) 
  270. 	{
  271. 		phyread(dev, priv->phyaddr, 0, &control);
  272. 		if (control & 0x8000)
  273. 		{
  274. 				continue;
  275. 		}
  276. 		else
  277. 		{
  278. 				break;
  279. 		}
  280. 	}
  281. 	phyread(dev, priv->phyaddr, 1, &status);
  282. 	
  283. 	while ( !(status & 0x0020) ) 
  284. 	{
  285. 		phyread(dev, priv->phyaddr,19,  &temp);
  286. //		timeout_counter++;
  287.  
  288. //		if (timeout_counter == 30) 
  289. //		{
  290. //			printf("Auto negotiation error\n");
  291. //			return;
  292. //		}
  293. 		phyread(dev, priv->phyaddr, 1, &status);
  294. 	}
  295. 	printf("autonegotiation complete.\n");
  296. }
  297.  
  298. static void phy_detection(struct eth_device *dev)
  299. {
  300. 	int i;
  301. 	u16 phyreg;
  302. 	struct zynq_gem_priv *priv = dev->priv;
  303.  
  304.        
  305. 	if (priv->phyaddr != -1) {
  306. 		phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg);
  307. 		if ((phyreg != 0xFFFF) &&
  308. 		    ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
  309. 			/* Found a valid PHY address */
  310. 			debug("Default phy address %d is valid\n",
  311. 			      priv->phyaddr);
  312. 			return;
  313. 		} else {
  314. 			debug("PHY address is not setup correctly %d\n",
  315. 			      priv->phyaddr);
  316. 			priv->phyaddr = -1;
  317. 		}
  318. 	}
  319. 	debug("detecting phy address\n");
  320. 	if (priv->phyaddr == -1) {
  321. 		/* detect the PHY address */
  322. 		for (i = 31; i >= 0; i--) {
  323. 			phyread(dev, i, PHY_DETECT_REG, &phyreg);
  324. 			if ((phyreg != 0xFFFF) &&
  325. 			    ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
  326. 				/* Found a valid PHY address */
  327. 				priv->phyaddr = i;
  328. 				debug("Found valid phy address, %d\n", i);
  329. 				return;
  330. 			}
  331. 		}
  332. 	}
  333. 	priv->phyaddr = 0;
  334. 	debug("No PHY detected.  Assuming a PHY at address 0\r\n");	
  335. }
  336.  
  337. static int zynq_gem_setup_mac(struct eth_device *dev)
  338. {
  339. 	u32 i, macaddrlow, macaddrhigh;
  340. 	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
  341.  
  342. 	/* Set the MAC bits [31:0] in BOT */
  343. 	macaddrlow = dev->enetaddr[0];
  344. 	macaddrlow |= dev->enetaddr[1] << 8;
  345. 	macaddrlow |= dev->enetaddr[2] << 16;
  346. 	macaddrlow |= dev->enetaddr[3] << 24;
  347.  
  348. 	/* Set MAC bits [47:32] in TOP */
  349. 	macaddrhigh = dev->enetaddr[4];
  350. 	macaddrhigh |= dev->enetaddr[5] << 8;
  351.  
  352. 	for (i = 0; i < 4; i++) {
  353. 		writel(0, &regs->laddr[i][LADDR_LOW]);
  354. 		writel(0, &regs->laddr[i][LADDR_HIGH]);
  355. 		/* Do not use MATCHx register */
  356. 		writel(0, &regs->match[i]);
  357. 	}
  358.  
  359. 	writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
  360. 	writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);
  361.  
  362. 	return 0;
  363. }
  364.  
  365. static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
  366. {
  367.  
  368. 	u32 i;
  369. 	u16 tmp;
  370. 	unsigned short PhyReg;
  371. 	unsigned long clk_rate = 0;
  372. 	struct phy_device *phydev;
  373. 	const u32 stat_size = (sizeof(struct zynq_gem_regs) -
  374. 				offsetof(struct zynq_gem_regs, stat)) / 4;
  375. 	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
  376. 	struct zynq_gem_priv *priv = dev->priv;
  377. 	const u32 supported = SUPPORTED_10baseT_Half |
  378. 			SUPPORTED_10baseT_Full |
  379. 			SUPPORTED_100baseT_Half |
  380. 			SUPPORTED_100baseT_Full |
  381. 			SUPPORTED_1000baseT_Half |
  382. 			SUPPORTED_1000baseT_Full;
  383. 	
  384. 	if (!priv->init) {
  385. 		/* Disable all interrupts */
  386. 		writel(0xFFFFFFFF, &regs->idr);
  387.  
  388. 		/* Disable the receiver & transmitter */
  389. 		writel(0, &regs->nwctrl);
  390. 		writel(0, &regs->txsr);
  391. 		writel(0, &regs->rxsr);
  392. 		writel(0, &regs->phymntnc);
  393.  
  394. 		/* Clear the Hash registers for the mac address
  395. 		 * pointed by AddressPtr
  396. 		 */
  397. 		writel(0x0, &regs->hashl);
  398. 		/* Write bits [63:32] in TOP */
  399. 		writel(0x0, &regs->hashh);
  400.  
  401. 		/* Clear all counters */
  402. 		for (i = 0; i <= stat_size; i++)
  403. 			readl(&regs->stat[i]);
  404.  
  405. 		/* Setup RxBD space */
  406. 		memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
  407.  
  408. 		for (i = 0; i < RX_BUF; i++) {
  409. 			priv->rx_bd[i].status = 0xF0000000;
  410. 			priv->rx_bd[i].addr =
  411. 					((u32)(priv->rxbuffers) +
  412. 							(i * PKTSIZE_ALIGN));
  413. 		}
  414. 		/* WRAP bit to last BD */
  415. 		priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
  416. 		/* Write RxBDs to IP */
  417. 		writel((u32)priv->rx_bd, &regs->rxqbase);
  418.  
  419. 		/* Setup for DMA Configuration register */
  420. 		writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
  421.  
  422. 		/* Setup for Network Control register, MDIO, Rx and Tx enable */
  423. 		setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
  424.  
  425. 		priv->init++;
  426. 	}
  427. 	//debug("phy detection.\n");
  428. 	//phy_detection(dev);
  429. 	//phy_rst(dev);
  430. 	//phy_negotiat(dev);
  431. 	
  432. if(net_base_addr==0xe000b000)
  433. {
  434. 	priv->phyaddr=0;
  435. 	
  436. 	//change to page 0
  437. 	phyread(dev, priv->phyaddr, 22, &PhyReg);
  438. 	PhyReg = PhyReg & 0xfffe;
  439. 	phywrite(dev, priv->phyaddr, 22, PhyReg);
  440.  
  441. 	phyread(dev, priv->phyaddr, 20, &PhyReg);
  442. 	PhyReg = PhyReg | 0x82;
  443. 	phywrite(dev, priv->phyaddr, 20, PhyReg);
  444.  
  445. 	/*  reset phy	 */
  446. 	phyread(dev, priv->phyaddr, 0, &PhyReg);
  447. 	PhyReg |= 0x8000;
  448. 	phywrite(dev, priv->phyaddr, 0, PhyReg);
  449.  
  450. 	for(i=0;i<1000000000;i++);    //Delay
  451.  
  452. 	phyread(dev, priv->phyaddr, 0, &PhyReg);
  453. 	PhyReg |= 0x1000;
  454. 	PhyReg |= 0x0200;
  455. 	PhyReg &= 0xFBFF;
  456. 	phywrite(dev, priv->phyaddr, 0, PhyReg);
  457.  
  458.  
  459.  
  460. 	phyread(dev, priv->phyaddr, 1, &PhyReg);
  461. 	
  462. 	while ( !(PhyReg & 0x0020) ) 
  463. 	{
  464. 		phyread(dev, priv->phyaddr, 1, &PhyReg);
  465. 	}
  466. 	printf("GEM0 autonegotiation complete.\n");
  467. }
  468. else
  469. {
  470. #if 1
  471. 	priv->phyaddr=1;
  472.  
  473. 	phyread(dev, priv->phyaddr, 0, &PhyReg);
  474. 	PhyReg |= 0x1000;
  475. 	PhyReg |= 0x0200;
  476. 	PhyReg &= 0xFBFF;
  477. 	phywrite(dev, priv->phyaddr, 0, PhyReg);
  478.  
  479.  
  480.  
  481. 	phyread(dev, priv->phyaddr, 1, &PhyReg);
  482. 	
  483. 	while ( !(PhyReg & 0x0020) ) 
  484. 	{
  485. 		phyread(dev, priv->phyaddr, 1, &PhyReg);
  486. 	}
  487. 	printf("GEM1 autonegotiation complete.\n");
  488. #endif
  489. }
  490. 	puts("GEM link speed is 1000Mbps\n");
  491. 	writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, &regs->nwcfg);
  492. 	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
  493. 					ZYNQ_GEM_NWCTRL_TXEN_MASK);	
  494.  
  495. 	return 0;
  496. }
  497.  
  498. static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
  499. {
  500. 	u32 addr, size;
  501. 	struct zynq_gem_priv *priv = dev->priv;
  502. 	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
  503.  
  504. 	/* setup BD */
  505. 	writel((u32)priv->tx_bd, &regs->txqbase);
  506.  
  507. 	/* Setup Tx BD */
  508. 	memset(priv->tx_bd, 0, sizeof(struct emac_bd));
  509.  
  510. 	priv->tx_bd->addr = (u32)ptr;
  511. 	priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
  512. 				ZYNQ_GEM_TXBUF_LAST_MASK;
  513.  
  514. 	addr = (u32) ptr;
  515. 	addr &= ~(ARCH_DMA_MINALIGN - 1);
  516. 	size = roundup(len, ARCH_DMA_MINALIGN);
  517. 	flush_dcache_range(addr, addr + size);
  518. 	barrier();
  519.  
  520. 	/* Start transmit */
  521. 	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
  522.  
  523. 	/* Read TX BD status */
  524. 	if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN)
  525. 		printf("TX underrun\n");
  526. 	if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
  527. 		printf("TX buffers exhausted in mid frame\n");
  528.  
  529. 	return 0;
  530. }
  531.  
  532. /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
  533. static int zynq_gem_recv(struct eth_device *dev)
  534. {
  535. 	int frame_len;
  536. 	struct zynq_gem_priv *priv = dev->priv;
  537. 	struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
  538. 	struct emac_bd *first_bd;
  539.  
  540. 	if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
  541. 		return 0;
  542.  
  543. 	if (!(current_bd->status &
  544. 			(ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
  545. 		printf("GEM: SOF or EOF not set for last buffer received!\n");
  546. 		return 0;
  547. 	}
  548.  
  549. 	frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
  550. 	if (frame_len) {
  551. 		u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
  552. 		addr &= ~(ARCH_DMA_MINALIGN - 1);
  553. 		u32 size = roundup(frame_len, ARCH_DMA_MINALIGN);
  554. 		invalidate_dcache_range(addr, addr + size);
  555.  
  556. 		NetReceive((u8 *)addr, frame_len);
  557.  
  558. 		if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
  559. 			priv->rx_first_buf = priv->rxbd_current;
  560. 		else {
  561. 			current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
  562. 			current_bd->status = 0xF0000000; /* FIXME */
  563. 		}
  564.  
  565. 		if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
  566. 			first_bd = &priv->rx_bd[priv->rx_first_buf];
  567. 			first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
  568. 			first_bd->status = 0xF0000000;
  569. 		}
  570.  
  571. 		if ((++priv->rxbd_current) >= RX_BUF)
  572. 			priv->rxbd_current = 0;
  573. 	}
  574.  
  575. 	return frame_len;
  576. }
  577.  
  578. static void zynq_gem_halt(struct eth_device *dev)
  579. {
  580. 	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
  581.  
  582. 	clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
  583. 						ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
  584. }
  585.  
  586. static int zynq_gem_miiphyread(const char *devname, uchar addr,
  587. 							uchar reg, ushort *val)
  588. {
  589. 	struct eth_device *dev = eth_get_dev();
  590. 	int ret;
  591.  
  592. 	ret = phyread(dev, addr, reg, val);
  593. 	debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
  594. 	return ret;
  595. }
  596.  
  597. static int zynq_gem_miiphy_write(const char *devname, uchar addr,
  598. 							uchar reg, ushort val)
  599. {
  600. 	struct eth_device *dev = eth_get_dev();
  601.  
  602. 	debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
  603. 	return phywrite(dev, addr, reg, val);
  604. }
  605.  
  606. int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio)
  607. {
  608. 	struct eth_device *dev;
  609. 	struct zynq_gem_priv *priv;
  610. 	void *bd_space;
  611. 	
  612. 	printf("zynq_gem_initialize: baseAddr = 0x%x, phyAddr = 0x%x.\n",base_addr,phy_addr);
  613.  
  614. 	net_base_addr=base_addr;
  615.  
  616. 	dev = calloc(1, sizeof(*dev));
  617. 	if (dev == NULL)
  618. 		return -1;
  619.  
  620. 	dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
  621. 	if (dev->priv == NULL) {
  622. 		free(dev);
  623. 		return -1;
  624. 	}
  625. 	priv = dev->priv;
  626.  
  627. 	/* Align rxbuffers to ARCH_DMA_MINALIGN */
  628. 	priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
  629. 	memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
  630.  
  631. 	/* Align bd_space to 1MB */
  632. 	bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
  633. 	mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF);
  634.  
  635. 	/* Initialize the bd spaces for tx and rx bd's */
  636. 	priv->tx_bd = (struct emac_bd *)bd_space;
  637. 	priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE);
  638.  
  639. 	priv->phyaddr = phy_addr;
  640. 	priv->emio = emio;
  641.  
  642. 	sprintf(dev->name, "Gem.%x_%x", base_addr,phy_addr);
  643.  
  644. 	dev->iobase = base_addr;
  645.  
  646. 	dev->init = zynq_gem_init;
  647. 	dev->halt = zynq_gem_halt;
  648. 	dev->send = zynq_gem_send;
  649. 	dev->recv = zynq_gem_recv;
  650. 	dev->write_hwaddr = zynq_gem_setup_mac;
  651.  
  652. 	eth_register(dev);
  653.  
  654. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
  655. 	debug("zynq_gem MII init.\n");
  656. 	miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
  657. 	priv->bus = miiphy_get_dev_by_name(dev->name);
  658. #endif
  659.  
  660. 	zynq_gem_init(dev,bis);
  661. 	return 1;
  662. }

 

 

3、devicetree设置

devicetree中需要设置ETH1节点下的PHY配置信息，如下：

可以通过修改产生devicetree的相应的配置文件得到

完整的devicetree如下

  1. /dts-v1/;
  2.  
  3. / {
  4. 	#address-cells = <0x1>;
  5. 	#size-cells = <0x1>;
  6. 	compatible = "xlnx,zynq-7000";
  7.  
  8. 	cpus {
  9. 		#address-cells = <0x1>;
  10. 		#size-cells = <0x0>;
  11.  
  12. 		cpu@0 {
  13. 			compatible = "arm,cortex-a9";
  14. 			device_type = "cpu";
  15. 			reg = <0x0>;
  16. 			clocks = <0x1 0x3>;
  17. 			clock-latency = <0x3e8>;
  18. 			cpu0-supply = <0x2>;
  19. 			operating-points = <0xa4cb8 0xf4240 0x5265c 0xf4240>;
  20. 		};
  21.  
  22. 		cpu@1 {
  23. 			compatible = "arm,cortex-a9";
  24. 			device_type = "cpu";
  25. 			reg = <0x1>;
  26. 			clocks = <0x1 0x3>;
  27. 		};
  28. 	};
  29.  
  30. 	fpga-full {
  31. 		compatible = "fpga-region";
  32. 		fpga-mgr = <0x3>;
  33. 		#address-cells = <0x1>;
  34. 		#size-cells = <0x1>;
  35. 		ranges;
  36. 	};
  37.  
  38. 	pmu@f8891000 {
  39. 		compatible = "arm,cortex-a9-pmu";
  40. 		interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;
  41. 		interrupt-parent = <0x4>;
  42. 		reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
  43. 	};
  44.  
  45. 	fixedregulator {
  46. 		compatible = "regulator-fixed";
  47. 		regulator-name = "VCCPINT";
  48. 		regulator-min-microvolt = <0xf4240>;
  49. 		regulator-max-microvolt = <0xf4240>;
  50. 		regulator-boot-on;
  51. 		regulator-always-on;
  52. 		linux,phandle = <0x2>;
  53. 		phandle = <0x2>;
  54. 	};
  55.  
  56. 	amba {
  57. 		u-boot,dm-pre-reloc;
  58. 		compatible = "simple-bus";
  59. 		#address-cells = <0x1>;
  60. 		#size-cells = <0x1>;
  61. 		interrupt-parent = <0x4>;
  62. 		ranges;
  63.  
  64. 		adc@f8007100 {
  65. 			compatible = "xlnx,zynq-xadc-1.00.a";
  66. 			reg = <0xf8007100 0x20>;
  67. 			interrupts = <0x0 0x7 0x4>;
  68. 			interrupt-parent = <0x4>;
  69. 			clocks = <0x1 0xc>;
  70. 		};
  71.  
  72. 		can@e0008000 {
  73. 			compatible = "xlnx,zynq-can-1.0";
  74. 			status = "disabled";
  75. 			clocks = <0x1 0x13 0x1 0x24>;
  76. 			clock-names = "can_clk", "pclk";
  77. 			reg = <0xe0008000 0x1000>;
  78. 			interrupts = <0x0 0x1c 0x4>;
  79. 			interrupt-parent = <0x4>;
  80. 			tx-fifo-depth = <0x40>;
  81. 			rx-fifo-depth = <0x40>;
  82. 		};
  83.  
  84. 		can@e0009000 {
  85. 			compatible = "xlnx,zynq-can-1.0";
  86. 			status = "disabled";
  87. 			clocks = <0x1 0x14 0x1 0x25>;
  88. 			clock-names = "can_clk", "pclk";
  89. 			reg = <0xe0009000 0x1000>;
  90. 			interrupts = <0x0 0x33 0x4>;
  91. 			interrupt-parent = <0x4>;
  92. 			tx-fifo-depth = <0x40>;
  93. 			rx-fifo-depth = <0x40>;
  94. 		};
  95.  
  96. 		gpio@e000a000 {
  97. 			compatible = "xlnx,zynq-gpio-1.0";
  98. 			#gpio-cells = <0x2>;
  99. 			clocks = <0x1 0x2a>;
  100. 			gpio-controller;
  101. 			interrupt-controller;
  102. 			#interrupt-cells = <0x2>;
  103. 			interrupt-parent = <0x4>;
  104. 			interrupts = <0x0 0x14 0x4>;
  105. 			reg = <0xe000a000 0x1000>;
  106. 			emio-gpio-width = <0x40>;
  107. 			gpio-mask-high = <0x0>;
  108. 			gpio-mask-low = <0x5600>;
  109. 		};
  110.  
  111. 		i2c@e0004000 {
  112. 			compatible = "cdns,i2c-r1p10";
  113. 			status = "okay";
  114. 			clocks = <0x1 0x26>;
  115. 			interrupt-parent = <0x4>;
  116. 			interrupts = <0x0 0x19 0x4>;
  117. 			reg = <0xe0004000 0x1000>;
  118. 			#address-cells = <0x1>;
  119. 			#size-cells = <0x0>;
  120. 			clock-frequency = <0x61a80>;
  121. 		};
  122.  
  123. 		i2c@e0005000 {
  124. 			compatible = "cdns,i2c-r1p10";
  125. 			status = "okay";
  126. 			clocks = <0x1 0x27>;
  127. 			interrupt-parent = <0x4>;
  128. 			interrupts = <0x0 0x30 0x4>;
  129. 			reg = <0xe0005000 0x1000>;
  130. 			#address-cells = <0x1>;
  131. 			#size-cells = <0x0>;
  132. 			clock-frequency = <0x61a80>;
  133. 		};
  134.  
  135. 		interrupt-controller@f8f01000 {
  136. 			compatible = "arm,cortex-a9-gic";
  137. 			#interrupt-cells = <0x3>;
  138. 			interrupt-controller;
  139. 			reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
  140. 			num_cpus = <0x2>;
  141. 			num_interrupts = <0x60>;
  142. 			linux,phandle = <0x4>;
  143. 			phandle = <0x4>;
  144. 		};
  145.  
  146. 		cache-controller@f8f02000 {
  147. 			compatible = "arm,pl310-cache";
  148. 			reg = <0xf8f02000 0x1000>;
  149. 			interrupts = <0x0 0x2 0x4>;
  150. 			arm,data-latency = <0x3 0x2 0x2>;
  151. 			arm,tag-latency = <0x2 0x2 0x2>;
  152. 			cache-unified;
  153. 			cache-level = <0x2>;
  154. 		};
  155.  
  156. 		memory-controller@f8006000 {
  157. 			compatible = "xlnx,zynq-ddrc-a05";
  158. 			reg = <0xf8006000 0x1000>;
  159. 		};
  160.  
  161. 		ocmc@f800c000 {
  162. 			compatible = "xlnx,zynq-ocmc-1.0";
  163. 			interrupt-parent = <0x4>;
  164. 			interrupts = <0x0 0x3 0x4>;
  165. 			reg = <0xf800c000 0x1000>;
  166. 		};
  167.  
  168. 		serial@e0000000 {
  169. 			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
  170. 			status = "okay";
  171. 			clocks = <0x1 0x17 0x1 0x28>;
  172. 			clock-names = "uart_clk", "pclk";
  173. 			reg = <0xe0000000 0x1000>;
  174. 			interrupts = <0x0 0x1b 0x4>;
  175. 			device_type = "serial";
  176. 			port-number = <0x0>;
  177. 		};
  178.  
  179. 		serial@e0001000 {
  180. 			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
  181. 			status = "okay";
  182. 			clocks = <0x1 0x18 0x1 0x29>;
  183. 			clock-names = "uart_clk", "pclk";
  184. 			reg = <0xe0001000 0x1000>;
  185. 			interrupts = <0x0 0x32 0x4>;
  186. 			device_type = "serial";
  187. 			port-number = <0x1>;
  188. 		};
  189.  
  190. 		spi@e0006000 {
  191. 			compatible = "xlnx,zynq-spi-r1p6";
  192. 			reg = <0xe0006000 0x1000>;
  193. 			status = "disabled";
  194. 			interrupt-parent = <0x4>;
  195. 			interrupts = <0x0 0x1a 0x4>;
  196. 			clocks = <0x1 0x19 0x1 0x22>;
  197. 			clock-names = "ref_clk", "pclk";
  198. 			#address-cells = <0x1>;
  199. 			#size-cells = <0x0>;
  200. 		};
  201.  
  202. 		spi@e0007000 {
  203. 			compatible = "xlnx,zynq-spi-r1p6";
  204. 			reg = <0xe0007000 0x1000>;
  205. 			status = "disabled";
  206. 			interrupt-parent = <0x4>;
  207. 			interrupts = <0x0 0x31 0x4>;
  208. 			clocks = <0x1 0x1a 0x1 0x23>;
  209. 			clock-names = "ref_clk", "pclk";
  210. 			#address-cells = <0x1>;
  211. 			#size-cells = <0x0>;
  212. 		};
  213.  
  214. 		spi@e000d000 {
  215. 			clock-names = "ref_clk", "pclk";
  216. 			clocks = <0x1 0xa 0x1 0x2b>;
  217. 			compatible = "xlnx,zynq-qspi-1.0";
  218. 			status = "okay";
  219. 			interrupt-parent = <0x4>;
  220. 			interrupts = <0x0 0x13 0x4>;
  221. 			reg = <0xe000d000 0x1000>;
  222. 			#address-cells = <0x1>;
  223. 			#size-cells = <0x0>;
  224. 			is-dual = <0x1>;
  225. 			num-cs = <0x1>;
  226. 		};
  227.  
  228. 		memory-controller@e000e000 {
  229. 			#address-cells = <0x1>;
  230. 			#size-cells = <0x1>;
  231. 			status = "disabled";
  232. 			clock-names = "memclk", "aclk";
  233. 			clocks = <0x1 0xb 0x1 0x2c>;
  234. 			compatible = "arm,pl353-smc-r2p1";
  235. 			interrupt-parent = <0x4>;
  236. 			interrupts = <0x0 0x12 0x4>;
  237. 			ranges;
  238. 			reg = <0xe000e000 0x1000>;
  239.  
  240. 			flash@e1000000 {
  241. 				status = "disabled";
  242. 				compatible = "arm,pl353-nand-r2p1";
  243. 				reg = <0xe1000000 0x1000000>;
  244. 				#address-cells = <0x1>;
  245. 				#size-cells = <0x1>;
  246. 			};
  247.  
  248. 			flash@e2000000 {
  249. 				status = "disabled";
  250. 				compatible = "cfi-flash";
  251. 				reg = <0xe2000000 0x2000000>;
  252. 				#address-cells = <0x1>;
  253. 				#size-cells = <0x1>;
  254. 			};
  255. 		};
  256.  
  257. 		ethernet@e000b000 {
  258. 			compatible = "cdns,zynq-gem", "cdns,gem";
  259. 			reg = <0xe000b000 0x1000>;
  260. 			status = "okay";
  261. 			interrupts = <0x0 0x16 0x4>;
  262. 			clocks = <0x1 0x1e 0x1 0x1e 0x1 0xd>;
  263. 			clock-names = "pclk", "hclk", "tx_clk";
  264. 			#address-cells = <0x1>;
  265. 			#size-cells = <0x0>;
  266. 			phy-mode = "rgmii-id";
  267. 			xlnx,ptp-enet-clock = <0x6b49d20>;
  268. 		};
  269.  
  270. 		ethernet@e000c000 {
  271. 			compatible = "cdns,zynq-gem", "cdns,gem";
  272. 			reg = <0xe000c000 0x1000>;
  273. 			status = "okay";
  274. 			interrupts = <0x0 0x2d 0x4>;
  275. 			clocks = <0x1 0x1f 0x1 0x1f 0x1 0xe>;
  276. 			clock-names = "pclk", "hclk", "tx_clk";
  277. 			#address-cells = <0x1>;
  278. 			#size-cells = <0x0>;
  279. 			phy-mode = "gmii";
  280. 			xlnx,ptp-enet-clock = <0x6b49d20>;
  281. 			phy-handle = <0x5>;
  282.  
  283. 			phy@1 {
  284. 				compatible = "Xilinx PCS/PMA PHY";
  285. 				device_type = "ethernet-phy";
  286. 				xlnx,phy-type = <0x5>;
  287. 				reg = <0x1>;
  288. 				linux,phandle = <0x5>;
  289. 				phandle = <0x5>;
  290. 			};
  291. 		};
  292.  
  293. 		sdhci@e0100000 {
  294. 			compatible = "arasan,sdhci-8.9a";
  295. 			status = "disabled";
  296. 			clock-names = "clk_xin", "clk_ahb";
  297. 			clocks = <0x1 0x15 0x1 0x20>;
  298. 			interrupt-parent = <0x4>;
  299. 			interrupts = <0x0 0x18 0x4>;
  300. 			reg = <0xe0100000 0x1000>;
  301. 		};
  302.  
  303. 		sdhci@e0101000 {
  304. 			compatible = "arasan,sdhci-8.9a";
  305. 			status = "disabled";
  306. 			clock-names = "clk_xin", "clk_ahb";
  307. 			clocks = <0x1 0x16 0x1 0x21>;
  308. 			interrupt-parent = <0x4>;
  309. 			interrupts = <0x0 0x2f 0x4>;
  310. 			reg = <0xe0101000 0x1000>;
  311. 		};
  312.  
  313. 		slcr@f8000000 {
  314. 			#address-cells = <0x1>;
  315. 			#size-cells = <0x1>;
  316. 			compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
  317. 			reg = <0xf8000000 0x1000>;
  318. 			ranges;
  319. 			linux,phandle = <0x6>;
  320. 			phandle = <0x6>;
  321.  
  322. 			clkc@100 {
  323. 				#clock-cells = <0x1>;
  324. 				compatible = "xlnx,ps7-clkc";
  325. 				fclk-enable = <0x1>;
  326. 				clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb";
  327. 				reg = <0x100 0x100>;
  328. 				ps-clk-frequency = <0x2faf080>;
  329. 				linux,phandle = <0x1>;
  330. 				phandle = <0x1>;
  331. 			};
  332.  
  333. 			rstc@200 {
  334. 				compatible = "xlnx,zynq-reset";
  335. 				reg = <0x200 0x48>;
  336. 				#reset-cells = <0x1>;
  337. 				syscon = <0x6>;
  338. 			};
  339.  
  340. 			pinctrl@700 {
  341. 				compatible = "xlnx,pinctrl-zynq";
  342. 				reg = <0x700 0x200>;
  343. 				syscon = <0x6>;
  344. 			};
  345. 		};
  346.  
  347. 		dmac@f8003000 {
  348. 			compatible = "arm,pl330", "arm,primecell";
  349. 			reg = <0xf8003000 0x1000>;
  350. 			interrupt-parent = <0x4>;
  351. 			interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7";
  352. 			interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;
  353. 			#dma-cells = <0x1>;
  354. 			#dma-channels = <0x8>;
  355. 			#dma-requests = <0x4>;
  356. 			clocks = <0x1 0x1b>;
  357. 			clock-names = "apb_pclk";
  358. 		};
  359.  
  360. 		devcfg@f8007000 {
  361. 			compatible = "xlnx,zynq-devcfg-1.0";
  362. 			interrupt-parent = <0x4>;
  363. 			interrupts = <0x0 0x8 0x4>;
  364. 			reg = <0xf8007000 0x100>;
  365. 			clocks = <0x1 0xc 0x1 0xf 0x1 0x10 0x1 0x11 0x1 0x12>;
  366. 			clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
  367. 			syscon = <0x6>;
  368. 			linux,phandle = <0x3>;
  369. 			phandle = <0x3>;
  370. 		};
  371.  
  372. 		efuse@f800d000 {
  373. 			compatible = "xlnx,zynq-efuse";
  374. 			reg = <0xf800d000 0x20>;
  375. 		};
  376.  
  377. 		timer@f8f00200 {
  378. 			compatible = "arm,cortex-a9-global-timer";
  379. 			reg = <0xf8f00200 0x20>;
  380. 			interrupts = <0x1 0xb 0x301>;
  381. 			interrupt-parent = <0x4>;
  382. 			clocks = <0x1 0x4>;
  383. 		};
  384.  
  385. 		timer@f8001000 {
  386. 			interrupt-parent = <0x4>;
  387. 			interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;
  388. 			compatible = "cdns,ttc";
  389. 			clocks = <0x1 0x6>;
  390. 			reg = <0xf8001000 0x1000>;
  391. 		};
  392.  
  393. 		timer@f8002000 {
  394. 			interrupt-parent = <0x4>;
  395. 			interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;
  396. 			compatible = "cdns,ttc";
  397. 			clocks = <0x1 0x6>;
  398. 			reg = <0xf8002000 0x1000>;
  399. 		};
  400.  
  401. 		timer@f8f00600 {
  402. 			interrupt-parent = <0x4>;
  403. 			interrupts = <0x1 0xd 0x301>;
  404. 			compatible = "arm,cortex-a9-twd-timer";
  405. 			reg = <0xf8f00600 0x20>;
  406. 			clocks = <0x1 0x4>;
  407. 		};
  408.  
  409. 		usb@e0002000 {
  410. 			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
  411. 			status = "disabled";
  412. 			clocks = <0x1 0x1c>;
  413. 			interrupt-parent = <0x4>;
  414. 			interrupts = <0x0 0x15 0x4>;
  415. 			reg = <0xe0002000 0x1000>;
  416. 			phy_type = "ulpi";
  417. 		};
  418.  
  419. 		usb@e0003000 {
  420. 			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
  421. 			status = "disabled";
  422. 			clocks = <0x1 0x1d>;
  423. 			interrupt-parent = <0x4>;
  424. 			interrupts = <0x0 0x2c 0x4>;
  425. 			reg = <0xe0003000 0x1000>;
  426. 			phy_type = "ulpi";
  427. 		};
  428.  
  429. 		watchdog@f8005000 {
  430. 			clocks = <0x1 0x2d>;
  431. 			compatible = "cdns,wdt-r1p2";
  432. 			interrupt-parent = <0x4>;
  433. 			interrupts = <0x0 0x9 0x1>;
  434. 			reg = <0xf8005000 0x1000>;
  435. 			timeout-sec = <0xa>;
  436. 		};
  437. 	};
  438.  
  439. 	amba_pl {
  440. 		#address-cells = <0x1>;
  441. 		#size-cells = <0x1>;
  442. 		compatible = "simple-bus";
  443. 		ranges;
  444.  
  445. 		gpio@41200000 {
  446. 			#gpio-cells = <0x2>;
  447. 			compatible = "xlnx,xps-gpio-1.00.a";
  448. 			gpio-controller;
  449. 			reg = <0x41200000 0x10000>;
  450. 			xlnx,all-inputs = <0x0>;
  451. 			xlnx,all-inputs-2 = <0x0>;
  452. 			xlnx,all-outputs = <0x1>;
  453. 			xlnx,all-outputs-2 = <0x0>;
  454. 			xlnx,dout-default = <0x2>;
  455. 			xlnx,dout-default-2 = <0x0>;
  456. 			xlnx,gpio-width = <0x3>;
  457. 			xlnx,gpio2-width = <0x20>;
  458. 			xlnx,interrupt-present = <0x0>;
  459. 			xlnx,is-dual = <0x0>;
  460. 			xlnx,tri-default = <0xffffffff>;
  461. 			xlnx,tri-default-2 = <0xffffffff>;
  462. 		};
  463.  
  464. 		gpio@41210000 {
  465. 			#gpio-cells = <0x2>;
  466. 			compatible = "xlnx,xps-gpio-1.00.a";
  467. 			gpio-controller;
  468. 			reg = <0x41210000 0x10000>;
  469. 			xlnx,all-inputs = <0x0>;
  470. 			xlnx,all-inputs-2 = <0x0>;
  471. 			xlnx,all-outputs = <0x1>;
  472. 			xlnx,all-outputs-2 = <0x0>;
  473. 			xlnx,dout-default = <0x0>;
  474. 			xlnx,dout-default-2 = <0x0>;
  475. 			xlnx,gpio-width = <0xc>;
  476. 			xlnx,gpio2-width = <0x20>;
  477. 			xlnx,interrupt-present = <0x0>;
  478. 			xlnx,is-dual = <0x0>;
  479. 			xlnx,tri-default = <0xffffffff>;
  480. 			xlnx,tri-default-2 = <0xffffffff>;
  481. 		};
  482.  
  483. 		gpio@41220000 {
  484. 			#gpio-cells = <0x2>;
  485. 			compatible = "xlnx,xps-gpio-1.00.a";
  486. 			gpio-controller;
  487. 			reg = <0x41220000 0x10000>;
  488. 			xlnx,all-inputs = <0x0>;
  489. 			xlnx,all-inputs-2 = <0x0>;
  490. 			xlnx,all-outputs = <0x1>;
  491. 			xlnx,all-outputs-2 = <0x0>;
  492. 			xlnx,dout-default = <0xaa>;
  493. 			xlnx,dout-default-2 = <0x0>;
  494. 			xlnx,gpio-width = <0x8>;
  495. 			xlnx,gpio2-width = <0x20>;
  496. 			xlnx,interrupt-present = <0x0>;
  497. 			xlnx,is-dual = <0x0>;
  498. 			xlnx,tri-default = <0xffffffff>;
  499. 			xlnx,tri-default-2 = <0xffffffff>;
  500. 		};
  501.  
  502. 		gpio@41230000 {
  503. 			#gpio-cells = <0x2>;
  504. 			compatible = "xlnx,xps-gpio-1.00.a";
  505. 			gpio-controller;
  506. 			reg = <0x41230000 0x10000>;
  507. 			xlnx,all-inputs = <0x1>;
  508. 			xlnx,all-inputs-2 = <0x0>;
  509. 			xlnx,all-outputs = <0x0>;
  510. 			xlnx,all-outputs-2 = <0x0>;
  511. 			xlnx,dout-default = <0x0>;
  512. 			xlnx,dout-default-2 = <0x0>;
  513. 			xlnx,gpio-width = <0x6>;
  514. 			xlnx,gpio2-width = <0x20>;
  515. 			xlnx,interrupt-present = <0x0>;
  516. 			xlnx,is-dual = <0x0>;
  517. 			xlnx,tri-default = <0xffffffff>;
  518. 			xlnx,tri-default-2 = <0xffffffff>;
  519. 		};
  520.  
  521. 		gpio@41240000 {
  522. 			#gpio-cells = <0x2>;
  523. 			compatible = "xlnx,xps-gpio-1.00.a";
  524. 			gpio-controller;
  525. 			reg = <0x41240000 0x10000>;
  526. 			xlnx,all-inputs = <0x1>;
  527. 			xlnx,all-inputs-2 = <0x0>;
  528. 			xlnx,all-outputs = <0x0>;
  529. 			xlnx,all-outputs-2 = <0x0>;
  530. 			xlnx,dout-default = <0x0>;
  531. 			xlnx,dout-default-2 = <0x0>;
  532. 			xlnx,gpio-width = <0x6>;
  533. 			xlnx,gpio2-width = <0x20>;
  534. 			xlnx,interrupt-present = <0x0>;
  535. 			xlnx,is-dual = <0x0>;
  536. 			xlnx,tri-default = <0xffffffff>;
  537. 			xlnx,tri-default-2 = <0xffffffff>;
  538. 		};
  539.  
  540. 		gpio@41250000 {
  541. 			#gpio-cells = <0x2>;
  542. 			compatible = "xlnx,xps-gpio-1.00.a";
  543. 			gpio-controller;
  544. 			reg = <0x41250000 0x10000>;
  545. 			xlnx,all-inputs = <0x1>;
  546. 			xlnx,all-inputs-2 = <0x0>;
  547. 			xlnx,all-outputs = <0x0>;
  548. 			xlnx,all-outputs-2 = <0x0>;
  549. 			xlnx,dout-default = <0x0>;
  550. 			xlnx,dout-default-2 = <0x0>;
  551. 			xlnx,gpio-width = <0x4>;
  552. 			xlnx,gpio2-width = <0x20>;
  553. 			xlnx,interrupt-present = <0x0>;
  554. 			xlnx,is-dual = <0x0>;
  555. 			xlnx,tri-default = <0xffffffff>;
  556. 			xlnx,tri-default-2 = <0xffffffff>;
  557. 		};
  558.  
  559. 		gpio@41260000 {
  560. 			#gpio-cells = <0x2>;
  561. 			compatible = "xlnx,xps-gpio-1.00.a";
  562. 			gpio-controller;
  563. 			reg = <0x41260000 0x10000>;
  564. 			xlnx,all-inputs = <0x1>;
  565. 			xlnx,all-inputs-2 = <0x0>;
  566. 			xlnx,all-outputs = <0x0>;
  567. 			xlnx,all-outputs-2 = <0x0>;
  568. 			xlnx,dout-default = <0x0>;
  569. 			xlnx,dout-default-2 = <0x0>;
  570. 			xlnx,gpio-width = <0x2>;
  571. 			xlnx,gpio2-width = <0x20>;
  572. 			xlnx,interrupt-present = <0x0>;
  573. 			xlnx,is-dual = <0x0>;
  574. 			xlnx,tri-default = <0xffffffff>;
  575. 			xlnx,tri-default-2 = <0xffffffff>;
  576. 		};
  577.  
  578. 		gpio@41270000 {
  579. 			#gpio-cells = <0x2>;
  580. 			compatible = "xlnx,xps-gpio-1.00.a";
  581. 			gpio-controller;
  582. 			reg = <0x41270000 0x10000>;
  583. 			xlnx,all-inputs = <0x0>;
  584. 			xlnx,all-inputs-2 = <0x0>;
  585. 			xlnx,all-outputs = <0x1>;
  586. 			xlnx,all-outputs-2 = <0x0>;
  587. 			xlnx,dout-default = <0x0>;
  588. 			xlnx,dout-default-2 = <0x0>;
  589. 			xlnx,gpio-width = <0x2>;
  590. 			xlnx,gpio2-width = <0x20>;
  591. 			xlnx,interrupt-present = <0x0>;
  592. 			xlnx,is-dual = <0x0>;
  593. 			xlnx,tri-default = <0xffffffff>;
  594. 			xlnx,tri-default-2 = <0xffffffff>;
  595. 		};
  596.  
  597. 		gpio@41280000 {
  598. 			#gpio-cells = <0x2>;
  599. 			compatible = "xlnx,xps-gpio-1.00.a";
  600. 			gpio-controller;
  601. 			reg = <0x41280000 0x10000>;
  602. 			xlnx,all-inputs = <0x0>;
  603. 			xlnx,all-inputs-2 = <0x0>;
  604. 			xlnx,all-outputs = <0x1>;
  605. 			xlnx,all-outputs-2 = <0x0>;
  606. 			xlnx,dout-default = <0x1>;
  607. 			xlnx,dout-default-2 = <0x0>;
  608. 			xlnx,gpio-width = <0x1>;
  609. 			xlnx,gpio2-width = <0x20>;
  610. 			xlnx,interrupt-present = <0x0>;
  611. 			xlnx,is-dual = <0x0>;
  612. 			xlnx,tri-default = <0xffffffff>;
  613. 			xlnx,tri-default-2 = <0xffffffff>;
  614. 		};
  615.  
  616. 		axi_pwm@43c10000 {
  617. 			compatible = "xlnx,axi-pwm-1.0";
  618. 			reg = <0x43c10000 0x10000>;
  619. 			xlnx,s00-axi-addr-width = <0x6>;
  620. 			xlnx,s00-axi-data-width = <0x20>;
  621. 		};
  622.  
  623. 		xadc_wiz@43c00000 {
  624. 			clock-names = "ref_clk";
  625. 			clocks = <0x1 0x0>;
  626. 			compatible = "xlnx,axi-xadc-1.00.a";
  627. 			reg = <0x43c00000 0x10000>;
  628. 			xlnx,alarm-limit-r0 = <0xb5ed>;
  629. 			xlnx,alarm-limit-r1 = <0x57e4>;
  630. 			xlnx,alarm-limit-r10 = <0x5555>;
  631. 			xlnx,alarm-limit-r11 = <0x5111>;
  632. 			xlnx,alarm-limit-r12 = <0x9999>;
  633. 			xlnx,alarm-limit-r13 = <0x91eb>;
  634. 			xlnx,alarm-limit-r14 = <0x6aaa>;
  635. 			xlnx,alarm-limit-r15 = <0x6666>;
  636. 			xlnx,alarm-limit-r2 = <0xa147>;
  637. 			xlnx,alarm-limit-r3 = <0xca33>;
  638. 			xlnx,alarm-limit-r4 = <0xa93a>;
  639. 			xlnx,alarm-limit-r5 = <0x52c6>;
  640. 			xlnx,alarm-limit-r6 = <0x9555>;
  641. 			xlnx,alarm-limit-r7 = <0xae4e>;
  642. 			xlnx,alarm-limit-r8 = <0x5999>;
  643. 			xlnx,alarm-limit-r9 = <0x5111>;
  644. 			xlnx,configuration-r0 = <0x0>;
  645. 			xlnx,configuration-r1 = <0x2100>;
  646. 			xlnx,configuration-r2 = <0x400>;
  647. 			xlnx,dclk-frequency = <0x64>;
  648. 			xlnx,external-mux = "none";
  649. 			xlnx,external-mux-channel = "VP_VN";
  650. 			xlnx,external-muxaddr-enable = <0x0>;
  651. 			xlnx,fifo-depth = <0x7>;
  652. 			xlnx,has-axi = <0x1>;
  653. 			xlnx,has-axi4stream = <0x0>;
  654. 			xlnx,has-busy = <0x1>;
  655. 			xlnx,has-channel = <0x1>;
  656. 			xlnx,has-convst = <0x0>;
  657. 			xlnx,has-convstclk = <0x0>;
  658. 			xlnx,has-dclk = <0x1>;
  659. 			xlnx,has-drp = <0x0>;
  660. 			xlnx,has-eoc = <0x1>;
  661. 			xlnx,has-eos = <0x1>;
  662. 			xlnx,has-external-mux = <0x0>;
  663. 			xlnx,has-jtagbusy = <0x0>;
  664. 			xlnx,has-jtaglocked = <0x0>;
  665. 			xlnx,has-jtagmodified = <0x0>;
  666. 			xlnx,has-ot-alarm = <0x1>;
  667. 			xlnx,has-reset = <0x0>;
  668. 			xlnx,has-temp-bus = <0x0>;
  669. 			xlnx,has-user-temp-alarm = <0x1>;
  670. 			xlnx,has-vbram-alarm = <0x0>;
  671. 			xlnx,has-vccaux-alarm = <0x1>;
  672. 			xlnx,has-vccddro-alarm = <0x1>;
  673. 			xlnx,has-vccint-alarm = <0x1>;
  674. 			xlnx,has-vccpaux-alarm = <0x1>;
  675. 			xlnx,has-vccpint-alarm = <0x1>;
  676. 			xlnx,has-vn = <0x1>;
  677. 			xlnx,has-vp = <0x1>;
  678. 			xlnx,include-intr = <0x1>;
  679. 			xlnx,sampling-rate = "961538.4615384615";
  680. 			xlnx,sequence-r0 = <0x77e0>;
  681. 			xlnx,sequence-r1 = <0x9f77>;
  682. 			xlnx,sequence-r2 = <0x47e0>;
  683. 			xlnx,sequence-r3 = <0x9f77>;
  684. 			xlnx,sequence-r4 = <0x0>;
  685. 			xlnx,sequence-r5 = <0x0>;
  686. 			xlnx,sequence-r6 = <0x0>;
  687. 			xlnx,sequence-r7 = <0x9f77>;
  688. 			xlnx,sim-file-name = "design";
  689. 			xlnx,sim-file-rel-path = "./";
  690. 			xlnx,sim-file-sel = "Default";
  691. 			xlnx,vaux0 = <0x1>;
  692. 			xlnx,vaux1 = <0x1>;
  693. 			xlnx,vaux10 = <0x1>;
  694. 			xlnx,vaux11 = <0x1>;
  695. 			xlnx,vaux12 = <0x1>;
  696. 			xlnx,vaux13 = <0x0>;
  697. 			xlnx,vaux14 = <0x0>;
  698. 			xlnx,vaux15 = <0x1>;
  699. 			xlnx,vaux2 = <0x1>;
  700. 			xlnx,vaux3 = <0x0>;
  701. 			xlnx,vaux4 = <0x1>;
  702. 			xlnx,vaux5 = <0x1>;
  703. 			xlnx,vaux6 = <0x1>;
  704. 			xlnx,vaux7 = <0x0>;
  705. 			xlnx,vaux8 = <0x1>;
  706. 			xlnx,vaux9 = <0x1>;
  707. 		};
  708. 	};
  709.  
  710. 	chosen {
  711. 		bootargs = "earlycon";
  712. 		stdout-path = "serial0:115200n8";
  713. 	};
  714.  
  715. 	aliases {
  716. 		ethernet0 = "/amba/ethernet@e000b000";
  717. 		ethernet1 = "/amba/ethernet@e000c000";
  718. 		serial0 = "/amba/serial@e0000000";
  719. 		serial1 = "/amba/serial@e0001000";
  720. 		spi0 = "/amba/spi@e000d000";
  721. 	};
  722.  
  723. 	memory {
  724. 		device_type = "memory";
  725. 		reg = <0x0 0x40000000>;
  726. 	};
  727. };

 

4、内核配置

内核中需要包含下面两个驱动，一个是网卡驱动，一个是phy驱动

 

5、文件系统设置

文件系统中增加ethtool工具，方便对网卡进行各种配置

下载源码，解压，执行:

再make即可。然后将ethtool拷贝到ramdisk内

 

6、测试

系统启动后会出现错误，提示无法产生时钟，导致速率不对，如下

查阅xilinx论坛，链接见这里 发现需要关闭PCS/PMA的自协商，这时就需要用到ethtool工具了。

然后就可以ping通电脑了

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