搭建DDR3的仿真环境_error : the port "ddr3_dq[0]" is not aligned with

   /*****************************方式1***********************/
    wire  [63:0] ddr3_dq;
    wire   [7:0] ddr3_dqs_n;
    wire   [7:0] ddr3_dqs_p;
    wire  [14:0] ddr3_addr;
    wire   [2:0] ddr3_ba;
    wire         ddr3_ras_n;
    wire         ddr3_cas_n;
    wire         ddr3_we_n;
    wire         ddr3_reset_n;
    wire   [0:0] ddr3_ck_p;
    wire   [0:0] ddr3_ck_n;
    wire   [0:0] ddr3_cke;
    wire   [0:0] ddr3_cs_n;
    wire   [7:0] ddr3_dm;
    wire   [0:0] ddr3_odt;
 
 
    ddr3_model u_ddr3_model_0(
        .rst_n  (sys_rst),
        .ck     (ddr3_ck_p),
        .ck_n   (ddr3_ck_n),
        .cke    (ddr3_cke),
        .cs_n   (ddr3_cs_n),
        .ras_n  (ddr3_ras_n),
        .cas_n  (ddr3_cas_n),
        .we_n   (ddr3_we_n),
        .dm_tdqs(ddr3_dm[1:0]),
        .ba     (ddr3_ba),
        .addr   (ddr3_addr),
        .dq     (ddr3_dq[15:0]),
        .dqs    (ddr3_dqs_p[1:0]),
        .dqs_n  (ddr3_dqs_n[1:0]),
        .tdqs_n (),
        .odt    (ddr3_odt)
        );
 
        ddr3_model u_ddr3_model_1(
        .rst_n  (sys_rst),
        .ck     (ddr3_ck_p),
        .ck_n   (ddr3_ck_n),
        .cke    (ddr3_cke),
        .cs_n   (ddr3_cs_n),
        .ras_n  (ddr3_ras_n),
        .cas_n  (ddr3_cas_n),
        .we_n   (ddr3_we_n),
        .dm_tdqs(ddr3_dm[3:2]),
        .ba     (ddr3_ba),
        .addr   (ddr3_addr),
        .dq     (ddr3_dq[31:16]),
        .dqs    (ddr3_dqs_p[3:2]),
        .dqs_n  (ddr3_dqs_n[3:2]),
        .tdqs_n (),
        .odt    (ddr3_odt)
        );
 
        ddr3_model u_ddr3_model_2(
        .rst_n  (sys_rst),
        .ck     (ddr3_ck_p),
        .ck_n   (ddr3_ck_n),
        .cke    (ddr3_cke),
        .cs_n   (ddr3_cs_n),
        .ras_n  (ddr3_ras_n),
        .cas_n  (ddr3_cas_n),
        .we_n   (ddr3_we_n),
        .dm_tdqs(ddr3_dm[5:4]),
        .ba     (ddr3_ba),
        .addr   (ddr3_addr),
        .dq     (ddr3_dq[47:32]),
        .dqs    (ddr3_dqs_p[5:4]),
        .dqs_n  (ddr3_dqs_n[5:4]),
        .tdqs_n (),
        .odt    (ddr3_odt)
        );
 
        ddr3_model u_ddr3_model_3(
        .rst_n  (sys_rst),
        .ck     (ddr3_ck_p),
        .ck_n   (ddr3_ck_n),
        .cke    (ddr3_cke),
        .cs_n   (ddr3_cs_n),
        .ras_n  (ddr3_ras_n),
        .cas_n  (ddr3_cas_n),
        .we_n   (ddr3_we_n),
        .dm_tdqs(ddr3_dm[7:6]),
        .ba     (ddr3_ba),
        .addr   (ddr3_addr),
        .dq     (ddr3_dq[63:48]),
        .dqs    (ddr3_dqs_p[7:6]),
        .dqs_n  (ddr3_dqs_n[7:6]),
        .tdqs_n (),
        .odt    (ddr3_odt)
        );
/***************************方式2*********************/
    wire  [63:0] ddr3_dq;
    wire   [7:0] ddr3_dqs_n;
    wire   [7:0] ddr3_dqs_p;
    wire  [14:0] ddr3_addr;
    wire   [2:0] ddr3_ba;
    wire         ddr3_ras_n;
    wire         ddr3_cas_n;
    wire         ddr3_we_n;
    wire         ddr3_reset_n;
    wire   [0:0] ddr3_ck_p;
    wire   [0:0] ddr3_ck_n;
    wire   [0:0] ddr3_cke;
    wire   [0:0] ddr3_cs_n;
    wire   [7:0] ddr3_dm;
    wire   [0:0] ddr3_odt;
 
genvar i;
generate
	for (i=0;i<4;i=i+1) begin : gen_mem_0
	    ddr3_model u_ddr3_model_1
	    (
			.rst_n(sys_rst_n),
			.ck(ddr3_ck_p_0),
			.ck_n(ddr3_ck_n_0),
			.cke(ddr3_cke_0),
			.cs_n(ddr3_cs_n_0),
			.ras_n(ddr3_ras_n_0),
			.we_n(ddr3_we_n_0),
			.cas_n   (ddr3_cas_n_0),
			.dm_tdqs (ddr3_dm_0[(2*(i+1)-1):(2*i)]),
			.ba      (ddr3_ba_0),
			.addr    (ddr3_addr_0),
			.dq      (ddr3_dq_0[16*(i+1)-1:16*(i)]),
			.dqs     (ddr3_dqs_p_0[(2*(i+1)-1):(2*i)]),
			.dqs_n   (ddr3_dqs_n_0[(2*(i+1)-1):(2*i)]),
			.tdqs_n  (),
			.odt     (ddr3_odt_0)
		);
	end
endgenerate

此代码是仿真64位宽DDR的必要代码，在自己的仿真文件中加入进去即可

ddr3_model的位宽默认是16位的，可以例化多个来实现64位操作，仿真时只需要添加ddr3_model_parameters.v和ddr3_model.v即可，这两个文件在example design中可以找到，如果想仿真更多的地址，需要将ddr3_model_parameters.v中的MEM_BITS（默认为10）改大，2^MEM_BITS个地址