IC验证学习笔记（手撕代码）-3.1用verilog实现3.5分频电路_ic验证项目实例

module f35 (clk,rst,clk2);
	input clk,rst;
	output clk2;
	
	reg posedge_clk;
	reg negedge_clk;
	reg [2:0]posedge_count;
	reg [2:0]negedge_count;
	
	always@(posedge clk or negedge rst)begin
		if(!rst || posedge_count==3'd6)
			posedge_count<=0;
		else posedge_count<=posedge_count+1;
	end
	
	always@(negedge clk or negedge rst)begin
		if(!rst||negedge_count==3'd6)
			negedge_count<=0;
		else negedge_count<=negedge_count+1'd1;
	end
	
	always@(posedge clk or negedge rst)begin
		if(!rst)
			posedge_clk<=0;
		else if (posedge_count==0||posedge_count==3'd1)
			posedge_clk<=!posedge_clk;
		else
			posedge_clk<=posedge_clk;
	end
	
	always@(negedge clk or negedge rst)begin
		if(!rst)
			negedge_clk<=0;
		else if (negedge_count==3'd3||negedge_count==3'd4)
			negedge_clk<=!negedge_clk;
		else 
			negedge_clk<=negedge_clk;
	end
	
	assign clk2=posedge_clk||negedge_clk;
endmodule 

posedge_clk:在0、1翻转 negedge_clk:在3、4翻转 然后或操作

 testbench:

`timescale 1ns/1ps
module f35_tb();
	reg clk;
	reg rst;
	wire clk2;
	
	f35 u1(.clk(clk),.rst(rst),.clk2(clk2));
	always
		#5 clk=~clk;
		
	initial begin
		clk=0;
		rst=1;
	#15 rst=0;
	#30	rst=1;
	#300;
	$stop;
	end
endmodule

波形：