4.5交织_卷积交织原理

4.5.1分组交织器原理

4.5.2卷积交织器原理

4.5.3 802.11a中的交织

1、符号交织的实现

 

2、Data交织的实现

 

https://blog.csdn.net/weiweiliulu/article/details/48160057?locationNum=9&fps=1

代码：

module DATA_interleaver(DINT_DIN,DINT_ND,INDEX_IN,DINT_RST,DINT_CLK,MODE_CON,DINT_DOUT,DINT_RDY);
   
    input DINT_DIN;
    input DINT_ND;
    input [8:0] INDEX_IN;
    input [1:0] MODE_CON;
    input DINT_RST;
    input DINT_CLK;
    output DINT_DOUT;
    output DINT_RDY;
 
    reg DIN;             //register of input
    reg ND;					 //enable of output
    reg [8:0] INDEX;		 //register of index for output
    reg [1:0] MODE;		 
    reg [9:0] WA_1;      //DINT_RAM_1 write address
    reg DIN_1;           //DINT_RAM_1 input register
    reg REN_1;           //DINT_RAM_1 enable read 
	reg WEN_1;           //DINT_RAM_1 enable write
    reg WAC_1;		     //control write address of 1st interleaver
    reg DINT_RDY_1;      //DINT_RAM_1 enable output
    reg DIN_2;				 //DINT_RAM_2 input register
    reg [4:0] WA_2;		 //DINT_RAM_2 write address
    reg WEN_2;				 //DINT_RAM_2 enable write
    reg REN_2;				 //DINT_RAM_2 enable read
    reg WAC_2;				 //control write address of 2ed interleaver
    reg DINT_DV;         //enable output
    reg DINT_DOUT;		 //output register
    reg DINT_RDY;			 //synchronize with output
 
    wire [9:0] RA_1;     //DINT_RAM_1 read address
    wire [9:0] Q_1;		 //RCOUNT_1 counter of output
    wire DOUT_1;         //DINT_RAM_1 output
    wire RST;            //reset of IP core, enable under high leavel
    wire [4:0] Q_2;		 //RCOUNT_2 counter of output
    wire [4:0] RA_2;		 //DINT_RAM_2 read address
    wire DOUT_2;         //DINT_RAM_2 output
 
	assign RST=~DINT_RST;       
	assign RA_1=Q_1;				
 
/********************************************************************************/
/****************************   register for input   ****************************/
 
always @ (negedge DINT_RST or posedge DINT_CLK)	   
if (!DINT_RST)								 
  begin
	  DIN<=1'b0;
	  ND<=1'b0;
	  INDEX<=9'b000000000;
	  MODE<=2'b00;
  end
else
  begin
	  if (DINT_ND)
		begin
			DIN<=DINT_DIN;
			ND<=DINT_ND;
			INDEX<=INDEX_IN;
			MODE<=MODE_CON;
		end
	  else 
		begin
			DIN<=1'b0;
			ND<=1'b0;
			INDEX<=9'b000000000;
		end
  end
/**********************************************************************************/
/****************************       DINT_RAM_1   ****************************/
// BRAM: depth is 384 bits, the 1st interleaver BRAM to store the data which already adjust the order
DINT_RAM_1 dint_ram(
    .a(WA_1),
    .dpra(RA_1),
    .clk(DINT_CLK),
    .qdpo_clk(DINT_CLK),
    .d(DIN_1),
    .qdpo(DOUT_1),
    .qdpo_ce(REN_1),
    .qdpo_rst(RST),
    .we(WEN_1));
/***************************************************************************/
/****************************    RCOUNT_1    ****************************/
// counter cycle is 384 to generate read address of DINT_RAM_1
										  
rcount_1 RCOUNT_1(
    .Q(Q_1),
    .CLK(DINT_CLK),
    .CE(REN_1),                                           
    .SCLR(RST));
/**********************************************************************************/
/****************************       1st interleaver    ****************************/
always @ (negedge DINT_RST or posedge DINT_CLK)	   
if (!DINT_RST)								 
  begin
	  WAC_1<=1'b0;
	  WA_1<=10'b0000000000;
	  WEN_1<=1'b0;
	  DIN_1<=1'b0;
	  REN_1<=1'b0;
	  DINT_RDY_1<=1'b0;
  end
else
  begin
	  if (REN_1)                                               
		DINT_RDY_1<=1'b1;  				         		    
	  else										    
		DINT_RDY_1<=1'b0;
	  
	  case (MODE)									      
		  2'b10: 
			begin
				if (ND)                                                  
				  begin
					  if (!WAC_1)	
					       begin					// input data write in the BRAM first half part and the end alternatively, under control of WAC_1. 		
                             WA_1<=(INDEX[3:0]<<3)+(INDEX[3:0]<<2)+INDEX[8:4];
                             DIN_1<=DIN;
							 WEN_1<=1'b1;
						   end						
					  else	
                        begin					 
							WA_1<=(INDEX[3:0]<<3)+(INDEX[3:0]<<2)+INDEX[8:4]+192;                       														
							WEN_1<=1'b1;									                                       
							DIN_1<=DIN;			
                        end						
					 if(INDEX ==9'd192)
						begin
							WAC_1 <= ~WAC_1;
							REN_1 <= 1'b1;
						end
					 					 
				  end
				else 
				  begin
					  WA_1<=10'b0000000000;
					  WEN_1<=1'b0;														                                       
					  DIN_1<=1'b0;
				  end
				  
				if (Q_1==191 || Q_1==383)                  //finish read of BRAM
				  REN_1<=1'b0;								    
			end								              
	  endcase
 
	  
  end
 
 
/******************************************************************************/
/****************************       DINT_RAM_2     ****************************/
 
// BRAM: depth is 32bits, as 2ed interleaver, change the write address too
 
DINT_RAM_2 dint_ram2(
    .a(WA_2),
    .clk(DINT_CLK),
    .d(DIN_2),
    .we(WEN_2),
    .qdpo_ce(REN_2),
	.dpra(RA_2),
    .qdpo_clk(DINT_CLK),                                       
    .qdpo(DOUT_2),                                          
    .qdpo_rst(RST));
 
 
/***************************************************************************/
/****************************       WCOUNT_2    ****************************/
										  
count24 WCOUNT_2 (
    .Q(Q_2),
    .CLK(DINT_CLK),
    .CE(DINT_RDY_1),
    .SCLR(RST));
 
 
/**********************************************************************************/
/****************************       RCOUNT_2     ****************************/
 
										  
count24 RCOUNT_2 (
    .Q(RA_2),									   
    .CLK(DINT_CLK),
    .CE(REN_2),								    
    .SCLR(RST));
 
 
/**********************************************************************************/
/****************************      2ed interleaver     ****************************/
 
always @ (negedge DINT_RST or posedge DINT_CLK)	   
if (!DINT_RST)								 
  begin
	  WEN_2<=1'b0;
	  DIN_2<=1'b0;
	  WAC_2<=1'b0;
	  WA_2<=5'b00000; 
	  REN_2<=1'b0;
	  DINT_DV<=1'b0; 
	  DINT_DOUT<=1'b0;
	  DINT_RDY<=1'b0;
  end
else
  begin
	  case (MODE)									     
		  2'b10:
			  begin
				  if (DINT_RDY_1)								    //input data to the 2ed interleaver after finish the 1st interleaver
					begin
						WEN_2<=1'b1;								    
						DIN_2<=DOUT_1;							    
						if (WAC_2)									    //process the input data, change the write address or not with 12bits cycle alternatively, under control of WAC_2
						  begin 
							 WA_2[4:1]<=Q_2[4:1];						    
							 WA_2[0]<=~Q_2[0];
						  end
						else
						     WA_2<=Q_2;   								    
					end
				  else 
					begin
						WEN_2<=1'b0;
						DIN_2<=1'b0; 
					end
 
				  if (Q_2==11 || Q_2==23)						  //finish write, begin to read
					begin										    
						WAC_2<=~WAC_2;
						REN_2<=1'b1;
					end
				  if (RA_2==23 && !DINT_RDY_1)                             
					REN_2<=1'b0;								    
			  end										    
	  endcase										   
 
	  if (REN_2)                                               
		DINT_DV<=1'b1;
	  else
		DINT_DV<=1'b0;
	  if (DINT_DV)									     //data output
		begin										   
			DINT_DOUT<=DOUT_2;						        	    
			DINT_RDY<=1'b1;    							    
		end 										    
	  else
		begin
			DINT_DOUT<=1'b0;
			DINT_RDY<=1'b0;
		end
  end
endmodule

tb:

`timescale 1ns/1ns
module DATA_interleaver_tb();
    reg DINT_DIN;
    reg DINT_ND;
    reg [8:0] INDEX_IN;
    reg [1:0] MODE_CON;
    reg DINT_RST;
    reg DINT_CLK;
    wire DINT_DOUT;
    wire DINT_RDY;
    
    DATA_interleaver DATA_interleaver_inst(
    .DINT_DIN(DINT_DIN),
    .DINT_ND(DINT_ND),
    .INDEX_IN(INDEX_IN),
    .DINT_RST(DINT_RST),
    .DINT_CLK(DINT_CLK),
    .MODE_CON(MODE_CON),
    .DINT_DOUT(DINT_DOUT),
    .DINT_RDY(DINT_RDY)
    );
	
	integer i=0;
	integer j=0;
    initial begin
		DINT_RST=0;
		DINT_CLK=0;
		MODE_CON = 2'b00;
		INDEX_IN = 9'b000000000;
		DINT_ND = 0;
		DINT_DIN = 0;
		#20.1
		DINT_RST = 1;
		MODE_CON = 2'b10;
		DINT_ND = 1;
		#5
		for (i=0;j<2;j=j+1)
		    #1000
		    begin
				for (i=0;i<384;i=i+1)
					begin
						#5
						DINT_DIN = {$random} % 2;
						INDEX_IN = i + 9'd1;
						DINT_ND = 1;
					end
				DINT_ND = 0;
		    end
		
		#1000000
		$stop;
    end
 
    always #5 DINT_CLK =  ~DINT_CLK;
 
 
 
endmodule

 

 

第一级交织：交织公式的地址读入，顺序读出

第二级交织：每24个数据为一组，12个数据顺序不变，后12个数据每相邻两个交换位置

注意：采样时钟是否能采到相应的值，笔者进行测试的时候，采样时钟，未能采到191，后改正。