Verilog刷题_verlog刷题

HDLBits刷题–Edgecapture

题目叙述

For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. “Capture” means that the output will remain 1 until the register is reset (synchronous reset).

Each output bit behaves like a SR flip-flop: The output bit should be set (to 1) the cycle after a 1 to 0 transition occurs. The output bit should be reset (to 0) at the positive clock edge when reset is high. If both of the above events occur at the same time, reset has precedence. In the last 4 cycles of the example waveform below, the ‘reset’ event occurs one cycle earlier than the ‘set’ event, so there is no conflict here.

In the example waveform below, reset, in[1] and out[1] are shown again separately for clarity.
对于 32 位向量中的每一位，在输入信号从一个时钟周期的 1 变为下一个时钟周期的 0 时进行捕捉。“捕获”表示输出将保持为 1，直到寄存器复位（同步复位）。
每个输出位的行为类似于 SR 触发器：输出位应在 1 到 0 转换发生后的周期设置（为 1）。当复位为高电平时，输出位应在正时钟沿复位（为 0）。如果上述两个事件同时发生，则重置优先。在下面示例波形的最后 4 个周期中，“reset”事件比“set”事件早一个周期发生，因此这里不存在冲突。
在下面的示例波形中，为清楚起见，reset、in[1] 和 out[1] 再次分别显示如下。

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    reg [31:0] temp;
    reg [31:0] capture;
 
    //先检测输入信号的上升沿。
    always @ (posedge clk)
        begin
           temp <= in; 
            //capture = ~in & temp;
        end
    //这里如果采用reg的话会出现时序错误。
    assign capture = ~in & temp;
 
    //检测到上升沿之后，来确定输出
    always @ (posedge clk)
        begin
            if(reset)
                out <= 32'b0;
            else
                begin
                    for (int i=0; i<32; i=i+1)
                        begin
                            if(capture[i] == 1'b1)
                                out[i] <= 1'b1;
                        end
                end
        end
endmodule
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