FPGA入门学习—8位LED跑马灯设计_fpga 8位彩灯设计

FPGA入门学习—8位LED跑马灯设计：

• 在Verilog HDL的描述中，状态较少的电路适合用if…else…语句来描述，而状态较多的电路适合用case语句来描述

module设计文件：

`timescale 1ns / 1ps
module LED_Run_Horse(
    input clk,
    input rst_n,
    output reg [7:0]LED
    );
    //璺戦┈鐏?鏁堟灉(15绉嶇姸鎬?)
    //8'b0000_0000    0 鍏ㄧ伃

    //8'b0000_0001    1
    //8'b0000_0010    2
    //8'b0000_0100    3
    //8'b0000_1000    4
    //8'b0001_0000    5
    //8'b0010_0000    6
    //8'b0100_0000    7
    //8'b1000_0000    8
    //8'b0100_0000    9
    //8'b0010_0000    10
    //8'b0001_0000    11
    //8'b0000_1000    12
    //8'b0000_0100    13
    //8'b0000_0010    14
    //8'b0000_0001    15
    //...
    reg [3:0] state;
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
            state <= 4'd0;
        else if(state == 4'd16)
            state <= 4'd1;
        else if(state == 4'd0)
            state <= 4'd1;
        else
            state <= state + 1'd1;
    end
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)begin
                LED <= 8'd0;
            end
        else
            case (state)
                4'd1: LED <= 8'b0000_0001;
                4'd2: LED <= 8'b0000_0010;
                4'd3: LED <= 8'b0000_0100;
                4'd4: LED <= 8'b0000_1000;
                4'd5: LED <= 8'b0001_0000;
                4'd6: LED <= 8'b0010_0000;
                4'd7: LED <= 8'b0100_0000;
                4'd8: LED <= 8'b1000_0000;
                4'd9: LED <= 8'b0100_0000;
                4'd10: LED <= 8'b0010_0000;
                4'd11: LED <= 8'b0001_0000;
                4'd12: LED <= 8'b0000_1000;
                4'd13: LED <= 8'b0000_0100;
                4'd14: LED <= 8'b0000_0010;
                4'd15: LED <= 8'b0000_0001;
                default: LED <= 8'd0;
            endcase
    end
endmodule
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module仿真文件：

`timescale 1ns / 1ps
module tb_LED_Run_Horse;
reg clk;
reg rst_n;
wire [7:0] LED;
initial begin
clk = 0;
rst_n = 0;
#200; rst_n = 1;
end
always#20 clk = ~clk;
LED_Run_Horse u_LED_Run_Horse(
	.clk(clk),
	.rst_n(rst_n),
	.LED(LED)
);
endmodule
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仿真波形图：

综合原理图：