当前位置:   article > 正文

XINLINX原语学习 IDELAYE2

idelaye2

先看下原语的例化

 

 各个参数的属性

 

以下test bench测试结果

  1. `timescale 1ns / 1ps
  2. module led();
  3. reg ref_clk;
  4. reg rst;
  5. reg rx_frame;
  6. always #2.5 ref_clk = ~ref_clk;
  7. initial
  8. begin
  9. rx_frame = 0;
  10. ref_clk = 0;
  11. rst = 1;
  12. #10
  13. rst = 0;
  14. #1000
  15. rx_frame = 1;
  16. end
  17. IDELAYCTRL IDELAYCTRL_inst (
  18. .RDY(rdy), // 1-bit output: Ready output
  19. .REFCLK(ref_clk),// 1-bit input: Reference clock input
  20. .RST(rst) // 1-bit input: Active high reset input
  21. );
  22. IDELAYE2 #(
  23. .CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE)
  24. .DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
  25. .HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
  26. .IDELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
  27. .IDELAY_VALUE(0), // Input delay tap setting (0-31)
  28. .PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE
  29. .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz
  30. .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
  31. )
  32. IDELAYE2_inst_frame_delay (
  33. .CNTVALUEOUT(cnt_delay_tap),// 5-bit output: Counter value output
  34. .DATAOUT(rx_frame_delay), // 1-bit output: Delayed data output
  35. .C(ref_clk), // 1-bit input: Clock input
  36. .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
  37. .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
  38. .CNTVALUEIN(1'b0), // 5-bit input: Counter value input
  39. .DATAIN(1'b0), // 1-bit input: Internal delay data input
  40. .IDATAIN(rx_frame), // 1-bit input: Data input from the I/O
  41. .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
  42. .LD(1'b0), // 1-bit input: Load IDELAY_VALUE input
  43. .LDPIPEEN(1'b0), // 1-bit input: Enable PIPELINE register to load data input
  44. .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
  45. );
  46. endmodule

 当CNTVALUEIN= 0;延迟在600ps

 当CNTVALUEIN= 31,LD = 1延迟Tdelay=3.018ns=31x78(ps) +0.6ns;

 至此完成了IO的延迟。

声明:本文内容由网友自发贡献,版权归原作者所有,本站不承担相应法律责任。如您发现有侵权的内容,请联系我们。转载请注明出处:【wpsshop博客】
推荐阅读
相关标签
  

闽ICP备14008679号