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先看下原语的例化
各个参数的属性
以下test bench测试结果
- `timescale 1ns / 1ps
- module led();
-
- reg ref_clk;
- reg rst;
- reg rx_frame;
-
-
- always #2.5 ref_clk = ~ref_clk;
-
-
- initial
- begin
- rx_frame = 0;
- ref_clk = 0;
- rst = 1;
- #10
- rst = 0;
- #1000
- rx_frame = 1;
- end
- IDELAYCTRL IDELAYCTRL_inst (
- .RDY(rdy), // 1-bit output: Ready output
- .REFCLK(ref_clk),// 1-bit input: Reference clock input
- .RST(rst) // 1-bit input: Active high reset input
- );
-
- IDELAYE2 #(
- .CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE)
- .DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
- .HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
- .IDELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
- .IDELAY_VALUE(0), // Input delay tap setting (0-31)
- .PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE
- .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz
- .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
- )
- IDELAYE2_inst_frame_delay (
- .CNTVALUEOUT(cnt_delay_tap),// 5-bit output: Counter value output
- .DATAOUT(rx_frame_delay), // 1-bit output: Delayed data output
- .C(ref_clk), // 1-bit input: Clock input
- .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
- .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
- .CNTVALUEIN(1'b0), // 5-bit input: Counter value input
- .DATAIN(1'b0), // 1-bit input: Internal delay data input
- .IDATAIN(rx_frame), // 1-bit input: Data input from the I/O
- .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
- .LD(1'b0), // 1-bit input: Load IDELAY_VALUE input
- .LDPIPEEN(1'b0), // 1-bit input: Enable PIPELINE register to load data input
- .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
- );
-
- endmodule

当CNTVALUEIN= 0;延迟在600ps
当CNTVALUEIN= 31,LD = 1延迟Tdelay=3.018ns=31x78(ps) +0.6ns;
至此完成了IO的延迟。
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