Circuits--Build large --FSM

1. FSM: Enable shift register

module top_module (
    input clk,
    input reset,      // Synchronous reset
    output reg shift_ena);
    
    reg[2:0] count;
    
    always@(posedge clk)
        begin
            if(reset)
                begin
                count = 3'd0;
            	shift_ena = 1'b1;
                end
            else
                begin
                    if(count==3'd3)
                        shift_ena = 1'b0;
                    else 
                        begin
                           count = count +3'd1 ;
                           shift_ena = 1'b1;
                        end
                end
        end
    
endmodule

2.FSM : the complete FSM

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output shift_ena,
    output counting,
    input done_counting,
    output done,
    input ack );
    
    parameter S = 4'd0;
    parameter S1 = 4'd1;
    parameter S11 = 4'd2;
    parameter S110 = 4'd3;
    parameter B0 = 4'd4;
    parameter B1 = 4'd5;
    parameter B2 = 4'd6;
    parameter B3 = 4'd7;
    parameter Count = 4'd8;
    parameter Wait = 4'd9;
   
    reg[3:0] state;
    reg[3:0] next_state;
    
    always@(*)
        begin
            case(state)
               S:	next_state = data ? S1 : S;
               S1:	next_state = data ? S11 : S;
               S11:	next_state = data ? S11 : S110;
               S110: next_state = data ? B0 : S;
               B0 : next_state = B1;
               B1 : next_state = B2;
               B2 : next_state = B3;
               B3 : next_state = Count;
               Count : next_state = done_counting ? Wait : Count;
               Wait : next_state = ack ? S : Wait;
                
                
            endcase
        end
    
    always@(posedge clk)
        begin
            if(reset)
                state = S;
            else
                state = next_state;
        end
    
    assign shift_ena = (state == B0)|(state == B1)|(state == B2)|(state == B3);
    assign counting = (state == Count);
    assign done = (state == Wait);
    
    
 
endmodule

3.the complete timer

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output [3:0] count,
    output counting,
    output done,
    input ack );
    
    parameter S0 = 4'd0;
    parameter S1 = 4'd1;
    parameter S2 = 4'd2;
    parameter S3 = 4'd3;
    parameter C0 = 4'd4;
    parameter C1 = 4'd5;
    parameter C2 = 4'd6;
    parameter C3 = 4'd7;
    parameter Count_1000 = 4'd8;
    parameter Done = 4'd9;
    
    reg[3:0] state;
    reg[3:0] next_state;
    reg[15:0] num;
    reg[3:0] delay;
    reg[3:0] acount;
    
    wire count_state;
    assign count_state = (num == (delay + 1'b1)*1000) ? 1'b1 : 1'b0;
    
    always@(*)
        begin
            if(num <= 16'd1000)
                acount = 4'd0;
            else if(num > 16'd1000&&num <= 16'd2000)
                acount = 4'd1;
            else if(num > 16'd2000&&num <= 16'd3000)
                acount = 4'd2;
            else if(num > 16'd3000&&num <= 16'd4000)
                acount = 4'd3;
            else if(num > 16'd4000&&num <= 16'd5000)
                acount = 4'd4;
            else if(num > 16'd5000&&num <= 16'd6000)
                acount = 4'd5;
            else if(num > 16'd6000&&num <= 16'd7000)
                acount = 4'd6;
            else if(num > 16'd7000&&num <= 16'd8000)
                acount = 4'd7;
            else if(num > 16'd8000&&num <= 16'd9000)
                acount = 4'd8;
            else if(num > 16'd9000&&num <= 16'd10000)
                acount = 4'd9;
            else if(num > 16'd10000&&num <= 16'd11000)
                acount = 4'd10;
            else if(num > 16'd11000&&num <= 16'd12000)
                acount = 4'd11;
            else if(num > 16'd12000&&num <= 16'd13000)
                acount = 4'd12;
            else if(num > 16'd13000&&num <= 16'd14000)
                acount = 4'd13;
            else if(num > 16'd14000&&num <= 16'd15000)
                acount = 4'd14;
            else
                acount = 4'd15;
        end
    
    always@(posedge clk)
        begin
            if(reset)
                num <= 16'd0;
            else if(next_state == Done)
                num <= 16'd0;
            else if(next_state == Count_1000)
                num <= num + 16'd1;
        end
    
    always@(*)
        begin
            case(state)
                S0: next_state = data ? S1 : S0;
                S1: next_state = data ? S2 : S0;
                S2: next_state = data ? S2 : S3;
                S3: next_state = data ? C0 : S0;
                C0:
                    begin
                       next_state = C1;
                        delay[3] = data;
                    end
                C1:
                    begin
                       next_state = C2;
                        delay[2] = data;
                    end
                C2:
                    begin
                       next_state = C3;
                        delay[1] = data;
                    end
                C3:
                    begin
                       next_state = Count_1000;
                        delay[0] = data;
                    end
                Count_1000:
                    next_state = count_state ? Done : Count_1000;
                Done:
                    next_state = ack ? S0 : Done;
                default:
                    next_state = S0;
                
            endcase
        end
    
    always@(posedge clk)
        begin
            if(reset)
                state <= S0;
            else
                state <= next_state;
        end
    
    assign count = (state == Count_1000) ? (delay - acount) : 4'd0;
    assign counting = (state == Count_1000);
    assign done = (state == Done);
 
endmodule

4. FSM:one hot

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
); //
 
    // You may use these parameters to access state bits using e.g., state[B2] instead of state[6].
    parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9;
    assign B3_next = state[B2];
    assign S_next = ~d & state[S] | ~d & state[S1] | ~d & state[S110] | ack & state[Wait];
    assign S1_next = d & state[S];
    assign Count_next = state[B3] | ~done_counting & state[Count];
    assign Wait_next = done_counting & state[Count] | ~ack & state[Wait];
    assign done = state[Wait];
    assign counting = state[Count];
    assign shift_ena = state[B0] | state[B1] | state[B2] | state[B3];
 
 
endmodule