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《FPGA Verilog篇》Part 1 跑马灯例程的实现方法锦集

《FPGA Verilog篇》Part 1 跑马灯例程的实现方法锦集

Part 1 跑马灯例程的实现方法锦集                                                                                                                                                            

硬软件配置:
// Engineer: Test202_Led10flash_DEO_xxx
/// Create Date:    2016/3/12
// Module Name:   Led10flash_DEO_xxx
// Project Name:    Led10flash_DEO_xxx
// Target Devices: CycloneIII EP3C16F484C6N
// Tool versions: Quartus 11.0+Modelsim SE12.0
// Additional Comments: 25_000_000;
1、方法一:链接符移位操作实现跑马灯,源代码:
  1. //方法一:连接符移位操作实现跑马灯,在DEO上跑通//
  2. module Led10flash_DEO_shift(clk,rstn,led);
  3. input clk, rstn;
  4. output[9:0] led;
  5. reg[18:0] count;
  6. reg[7:0] cnt;
  7. //50MHz,20ns,20*500_000=10ms,2^19 count=[18:0]
  8. parameter dely1ms=500_000;
  9. always @(posedge clk or negedge rstn)
  10. begin
  11. if(!rstn) begin count<=18'd0;end
  12. else if(count==dely1ms) begin count<=16'd0; end
  13. else begin count<=count+1'd1;end
  14. end
  15. always @(posedge clk or negedge rstn)
  16. begin
  17. if(!rstn) begin cnt<=0;end
  18. else if(cnt==9) begin cnt<=0;end
  19. else if(count==dely1ms) begin cnt<=cnt+1'd1;end
  20. end
  21. //移位操作实现跑马灯
  22. reg[9:0] shiftR;
  23. always @(posedge clk or negedge rstn)
  24. begin
  25. if(!rstn) begin shiftR<=9'h01;end//初始化为9'h01很重要
  26. else if(cnt==9) begin shiftR<={shiftR[0],shiftR[9:1]};end
  27. else begin shiftR<=shiftR;end
  28. end
  29. assign led=shiftR;
  30. endmodule

2、方法二:移位运算符实现跑马灯,源代码:
  1. module Led10flash_DEO_Operator(clk,rstn,led);
  2. input clk, rstn;
  3. output[9:0] led;
  4. reg[18:0] count;
  5. reg[7:0] cnt;
  6. //50MHz,20ns,20*500_000=10ms,2^19 count=[18:0]
  7. parameter dely1ms=500_000;
  8. always @(posedge clk or negedge rstn)
  9. begin
  10. if(!rstn) begin count<=18'd0;end
  11. else if(count==dely1ms) begin count<=16'd0; end
  12. else begin count<=count+1'd1;end
  13. end
  14. always @(posedge clk or negedge rstn)
  15. begin
  16. if(!rstn) begin cnt<=0;end
  17. else if(cnt==9) begin cnt<=0;end
  18. else if(count==dely1ms) begin cnt<=cnt+1'd1;end
  19. end
  20. //移位实现跑马灯
  21. reg[9:0] shiftL;
  22. always @(posedge clk)
  23. begin
  24. if(!rstn)begin shiftL<=9'h01;end
  25. else if(cnt==9)begin shiftL<={shiftL<<1};end//移位运算符
  26. else if(shiftL==10'h400)begin shiftL<=10'h01;end
  27. //end
  28. else begin
  29. shiftL<=shiftL;
  30. end
  31. end
  32. assign led=shiftL;
  33. endmodule

3、方法三:case语句实现跑马灯,源代码:
  1. module Led10flash_DEO_case(clk,rstn,led);
  2. input clk,rstn;
  3. output[9:0] led;
  4. //reg[9:0] led;
  5. //50MHz,20ns,20*500_000=10ms,2^19 count=[18:0]
  6. parameter dely1ms=500_000;
  7. reg[18:0] count;
  8. reg[3:0] cnt;
  9. always @(posedge clk or negedge rstn)
  10. begin
  11. if(!rstn) begin count<=18'd0;end
  12. else if(count==dely1ms) begin count<=16'd0; end
  13. else begin count<=count+1'd1;end
  14. end
  15. always @(posedge clk or negedge rstn)
  16. begin
  17. if(!rstn) begin cnt<=0;end
  18. else if(cnt==9) begin cnt<=0;end
  19. else if(count==dely1ms) begin cnt<=cnt+1'd1;end
  20. end
  21. reg[9:0]shiftL;
  22. reg[3:0]i;
  23. always@(posedge clk or negedge rstn)
  24. begin
  25. if(!rstn)begin shiftL<=10'h01;i<=4'd0;end
  26. else begin
  27. case(i)//case语句循环
  28. 4'd0:begin
  29. if(cnt==9)begin i<=i+4'd1;shiftL<=10'h02;end
  30. else begin shiftL<=10'h01;end
  31. end
  32. 4'd1:begin
  33. if(cnt==9)begin i<=i+4'd1;shiftL<=10'h04;end
  34. else begin shiftL<=10'h02;end
  35. end
  36. 4'd2:begin
  37. if(cnt==9)begin i<=i+4'd1;shiftL<=10'h08;end
  38. else begin shiftL<=10'h04;end
  39. end
  40. 4'd3:begin
  41. if(cnt==9)begin i<=i+4'd1;shiftL<=10'h10;end
  42. else begin shiftL<=10'h08;end
  43. end
  44. 4'd4:begin
  45. if(cnt==9)begin i<=i+4'd1;shiftL<=10'h20;end
  46. else begin shiftL<=10'h10;end
  47. end
  48. 4'd5:begin
  49. if(cnt==9)begin i<=i+4'd1;shiftL<=10'h40;end
  50. else begin shiftL<=10'h20;end
  51. end
  52. 4'd6:begin
  53. if(cnt==9)begin i<=i+4'd1;shiftL<=10'h80;end
  54. else begin shiftL<=10'h40;end
  55. end
  56. 4'd7:begin
  57. if(cnt==9)begin i<=i+4'd1;shiftL<=10'h100;end
  58. else begin shiftL<=10'h80;end
  59. end
  60. 4'd8:begin
  61. if(cnt==9)begin i<=i+4'd1;shiftL<=10'h200;end
  62. else begin shiftL<=10'h100;end
  63. end
  64. 4'd9:begin
  65. if(cnt==9)begin i<=4'd0;shiftL<=10'h01;end
  66. else begin shiftL<=10'h200;end
  67. end
  68. default:begin shiftL<=10'h01;i=4'd0;end
  69. endcase
  70. end
  71. end
  72. assign led=shiftL;
  73. endmodule

4、方法四:case语句+连接符移位操作实现左循环右循环式跑马灯,源代码:
  1. module Led10flash_DEO_caseLR(clk,rstn,led);
  2. input clk,rstn;
  3. output[9:0] led;
  4. parameter dely=500_000;//19位,所以count为[18:0]
  5. reg[18:0]count;
  6. reg[3:0]cnt;
  7. always@(posedge clk or negedge rstn)
  8. begin
  9. if(!rstn) begin count<=18'd0;end
  10. else if(count==dely)begin count<=18'd0;end
  11. else count<=count+1'd1;
  12. end
  13. always@(posedge clk or negedge rstn)
  14. begin
  15. if(!rstn) begin cnt<=3'd0;end
  16. else if(cnt==9) begin cnt<=3'd0;end
  17. else if(count==dely)begin cnt<=cnt+1'd1;end
  18. end
  19. reg[9:0] shiftLR;
  20. reg[2:0] i;
  21. //连接符移位操作实现左右循环跑
  22. always @(posedge clk or negedge rstn)
  23. begin
  24. if(!rstn)begin i<=3'd0;shiftLR<=10'h01;end
  25. else if(cnt==9)begin//循环
  26. case(i)
  27. 3'd0:begin
  28. shiftLR<={shiftLR[8:0],shiftLR[9]}; //左移//if(cnt==9)
  29. if(shiftLR==10'h200) begin
  30. i=3'd1;
  31. shiftLR<=10'h100; //右移
  32. end
  33. end
  34. 3'd1:begin
  35. shiftLR<={shiftLR[0],shiftLR[9:1]};//右移 //if(cnt==9)
  36. if(shiftLR==10'h01)begin
  37. i=3'd0;
  38. shiftLR<=10'h02;//左移
  39. end
  40. end
  41. default:begin i<=3'd0; shiftLR<=10'h01;end
  42. endcase
  43. end
  44. end
  45. assign led=shiftLR;
  46. endmodule

5、方法五:Moore状态机实现跑马灯,源代码:
  1. ///*******************************
  2. //这个是在另DEO开发板上跑通的,所要注意引脚数目和引脚分配//
  3. ///******************************
  4. module led10flash_DEO(clk,rst,led);
  5. input clk,rst;
  6. output[9:0] led;
  7. reg[9:0] led;
  8. reg[3:0] state;
  9. reg[24:0] cnt;
  10. reg[11:0] count;
  11. parameter s0='d0,s1='d1,s2='d2,s3='d3,s4='d4,s5='d5,s6='d6,s7='d7,s8='d8,s9='d9,s10='d10,s11='d11;
  12. parameter led0=8'b1111_1111,led1=8'b0000_0000,led2=8'b1000_0000,led3=8'b0100_0000,led4=8'b0010_0000,
  13. led5=8'b0001_0000,led6=8'b0000_1000,led7=8'b0000_0100,led8=8'b0000_0010,led9=8'b0000_0001,
  14. led10=8'b1010_1010,led11=8'b0101_0101;
  15. parameter dely=250_000_000;//延时0.5s,25位,[24:0]
  16. wire clk2hz;
  17. always @(posedge clk)
  18. begin
  19. if(!rst) cnt<=1'b0;
  20. else if(cnt==dely) cnt<=1'b0;
  21. else cnt<=cnt+1'b1;
  22. end
  23. assign clk2hz=cnt[24];
  24. always @(posedge clk2hz )
  25. begin
  26. if(!rst) state<=s0;
  27. else if(count==11) begin count<=0;end
  28. // else if(cnt==dely) begin //count<=count+1'b1;
  29. else
  30. case(state)
  31. s0:begin if(count==0)begin count<= count+1'd1;state<=s1;end
  32. end
  33. s1:begin if(count==1)begin count<= count+1'd1; state<=s2;end
  34. else state<=s1;
  35. end
  36. s2:begin if(count==2)begin count<= count+1'd1; state<=s3;end
  37. else state<=s2;
  38. end
  39. s3:begin if(count==3)begin count<= count+1'd1; state<=s4;end
  40. else state<=s3;
  41. end
  42. s4:begin if(count==4)begin count<= count+1'd1; state<=s5;end
  43. else state<=s4;
  44. end
  45. s5:begin if(count==5)begin count<= count+1'd1; state<=s6;end
  46. else state<=s5;
  47. end
  48. s6:begin if(count==6)begin count<= count+1'd1; state<=s7;end
  49. else state<=s6;
  50. end
  51. s7:begin if(count==7)begin count<= count+1'd1; state<=s8;end
  52. else state<=s7;
  53. end
  54. s8:begin if(count==8)begin count<= count+1'd1; state<=s9;end
  55. else state<=s8;
  56. end
  57. s9:begin if(count==9)begin count<= count+1'd1; state<=s10;end
  58. else state<=s9;
  59. end
  60. s10:begin if(count==10)begin count<= count+1'd1; state<=s11;end
  61. else state<=s10;
  62. end
  63. s11:begin if(count==11)begin count<= count+1'd1; state<=s0;end
  64. else state<=s0;
  65. end
  66. default:state<=s0;
  67. endcase
  68. end
  69. always @(state)
  70. begin
  71. case(state)
  72. s0:led<=led0;
  73. s1:led<=led1;
  74. s2:led<=led2;
  75. s3:led<=led3;
  76. s4:led<=led4;
  77. s5:led<=led5;
  78. s6:led<=led6;
  79. s7:led<=led7;
  80. s8:led<=led8;
  81. s9:led<=led9;
  82. s10:led<=led10;
  83. s11:led<=led11;
  84. default:led<=led0;
  85. endcase
  86. end
  87. endmodule

6、方法六:Mealy状态机实现跑马灯,源代码:
  1. ///在DEO开发板上已经跑通了//
  2. module Led10flash_DEO(clk,rst,led);
  3. input clk,rst;
  4. output[9:0] led;
  5. reg[9:0] led;
  6. reg[6:0] state;
  7. //parameter s0='d0,s1='d1,s2='d2,s3='d3,s4='d4,s5='d5,s6='d6,s7='d7,
  8. // s8='d8,s9='d9,s10='d10,s11='d11,s12='d12,s13='d13,s14='d14,
  9. // s15='d15,s16='d16,s17='d17,s18='d18,s19='d19,s20='d20,s21='d21,
  10. // s22='d22,s23='d23,s24='d24,s25='d25,s26='d26,s27='d27,s28='d28,s29='d29;
  11. parameter s0='d0,s1='d1,s2='d2,s3='d3,s4='d4,s5='d5,s6='d6,s7='d7,s8='d8,s9='d9,s10='d10,s11='d11,s12='d12, s13='d13,s14='d14,s15='d15,s16='d16,s17='d17,s18='d18,s19='d19,s20='d20,s21='d21,s22='d22,s23='d23, s24='d24,s25='d25,s26='d26,s27='d27,s28='d28,s29='d29;
  12. parameter led0=10'b1111_1111_11,
  13. led1=10'b0000_0000_00,
  14. led2=10'b1000_0000_00,
  15. led3=10'b0100_0000_00,
  16. led4=10'b0010_0000_00,
  17. led5=10'b0001_0000_00,
  18. led6=10'b0000_1000_00,
  19. led7=10'b0000_0100_00,
  20. led8=10'b0000_0010_00,
  21. led9=10'b0000_0001_00,
  22. led10=10'b1010_1010_10,
  23. led11=10'b0000_0000_01,
  24. led12=10'b0000_1100_00,
  25. led13=10'b0001_1110_00,
  26. led14=10'b0011_1111_00,
  27. led15=10'b0111_1111_10,
  28. led16=10'b1111_1111_11,
  29. led17=10'b1000_0000_01,
  30. led18=10'b1100_0000_11,//中间到两边
  31. led19=10'b1110_0001_11,
  32. led20=10'b1111_0011_11,
  33. led21=10'b1111_1111_11,
  34. led22=10'b0111_1111_10,//两边到中间
  35. led23=10'b0011_1111_00,
  36. led24=10'b0001_1110_00,
  37. led25=10'b0000_1100_00,
  38. led26=10'b0011_1111_00,
  39. led27=10'b0111_1111_10,
  40. led28=10'b1010_1010_10,
  41. led29=10'b0101_0101_01;
  42. //parameter dely=250_000_000;//延时0.5s,25位,[24:0]
  43. parameter dely=25_000_000;
  44. reg[24:0] cnt;
  45. reg[6:0] count;
  46. wire clk2hz;
  47. always @(posedge clk)
  48. begin
  49. if(!rst)cnt<=1'b0;
  50. else if(cnt==dely) cnt<=1'b0;//延时5s,频率为0.2hz一定要计算好,计数25_000_000次,25位
  51. else cnt<=cnt+1;//若要分频成为4hz的时钟,则需要计数12500_000次,24位
  52. end
  53. assign clk2hz=cnt[24];
  54. always @(posedge clk2hz )
  55. begin
  56. if(!rst) state<=s0;
  57. else if(count==29) begin count<=0;end
  58. // else if(cnt==dely) begin //count<=count+1'b1;
  59. else
  60. case(state)
  61. s0:begin if(count==0)begin count<= count+1'd1;state<=s1;end
  62. end
  63. s1:begin if(count==1)begin count<= count+1'd1; state<=s2;end
  64. else state<=s1;
  65. end
  66. s2:begin if(count==2)begin count<= count+1'd1; state<=s3;end
  67. else state<=s2;
  68. end
  69. s3:begin if(count==3)begin count<= count+1'd1; state<=s4;end
  70. else state<=s3;
  71. end
  72. s4:begin if(count==4)begin count<= count+1'd1; state<=s5;end
  73. else state<=s4;
  74. end
  75. s5:begin if(count==5)begin count<= count+1'd1; state<=s6;end
  76. else state<=s5;
  77. end
  78. s6:begin if(count==6)begin count<= count+1'd1; state<=s7;end
  79. else state<=s6;
  80. end
  81. s7:begin if(count==7)begin count<= count+1'd1; state<=s8;end
  82. else state<=s7;
  83. end
  84. s8:begin if(count==8)begin count<= count+1'd1; state<=s9;end
  85. else state<=s8;
  86. end
  87. s9:begin if(count==9)begin count<= count+1'd1; state<=s10;end
  88. else state<=s9;
  89. end
  90. s10:begin if(count==10)begin count<= count+1'd1; state<=s11;end
  91. else state<=s10;
  92. end
  93. s11:begin if(count==11)begin count<= count+1'd1; state<=s12;end
  94. else state<=s11;
  95. end
  96. s12:begin if(count==12)begin count<= count+1'd1; state<=s13;end
  97. else state<=s12;
  98. end
  99. s13:begin if(count==13)begin count<= count+1'd1; state<=s14;end
  100. else state<=s13;
  101. end
  102. s14:begin if(count==14)begin count<= count+1'd1; state<=s15;end
  103. else state<=s14;
  104. end
  105. s15:begin if(count==15)begin count<= count+1'd1; state<=s16;end
  106. else state<=s15;
  107. end
  108. s16:begin if(count==16)begin count<= count+1'd1; state<=s17;end
  109. else state<=s16;
  110. end
  111. s17:begin if(count==17)begin count<= count+1'd1; state<=s18;end
  112. else state<=s17;
  113. end
  114. s18:begin if(count==18)begin count<= count+1'd1; state<=s19;end
  115. else state<=s18;
  116. end
  117. s19:begin if(count==19)begin count<= count+1'd1; state<=s20;end
  118. else state<=s19;
  119. end
  120. s20:begin if(count==20)begin count<= count+1'd1; state<=s21;end
  121. else state<=s20;
  122. end
  123. s21:begin if(count==21)begin count<= count+1'd1; state<=s22;end
  124. else state<=s21;
  125. end
  126. s22:begin if(count==22)begin count<= count+1'd1; state<=s23;end
  127. else state<=s22;
  128. end
  129. s23:begin if(count==23)begin count<= count+1'd1; state<=s24;end
  130. else state<=s23;
  131. end
  132. s24:begin if(count==24)begin count<= count+1'd1; state<=s25;end
  133. else state<=s24;
  134. end
  135. s25:begin if(count==25)begin count<= count+1'd1; state<=s26;end
  136. else state<=s25;
  137. end
  138. s26:begin if(count==26)begin count<= count+1'd1; state<=s27;end
  139. else state<=s26;
  140. end
  141. s27:begin if(count==27)begin count<= count+1'd1; state<=s28;end
  142. else state<=s27;
  143. end
  144. s28:begin if(count==28)begin count<= count+1'd1; state<=s29;end
  145. else state<=s28;
  146. end
  147. s29:begin if(count==29)begin count<= 0;state<=s0;end //可以直接begin count<=0;state<=s0;end
  148. else begin state<=s0;count<=0;end
  149. end
  150. default:begin state<=s0;end
  151. endcase
  152. end
  153. always @(state)
  154. begin
  155. case(state)
  156. s0:led<=led0;
  157. s1:led<=led1;
  158. s2:led<=led2;
  159. s3:led<=led3;
  160. s4:led<=led4;
  161. s5:led<=led5;
  162. s6:led<=led6;
  163. s7:led<=led7;
  164. s8:led<=led8;
  165. s9:led<=led9;
  166. s10:led<=led10;
  167. s11:led<=led11;
  168. s12:led<=led12;
  169. s13:led<=led13;
  170. s14:led<=led14;
  171. s15:led<=led15;
  172. s16:led<=led16;
  173. s17:led<=led17;
  174. s18:led<=led18;
  175. s19:led<=led19;
  176. s20:led<=led20;
  177. s21:led<=led21;
  178. s22:led<=led22;
  179. s23:led<=led23;
  180. s24:led<=led24;
  181. s25:led<=led25;
  182. s26:led<=led26;
  183. s27:led<=led27;
  184. s28:led<=led28;
  185. s29:led<=led29;
  186. default:led<=led0;
  187. endcase
  188. end
  189. endmodule


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