FPGA有符号数输入signed的类型设置_input signed

FPGA有符号数输入signed的类型设置

src & tb ：input signed的情况

module signed_verify (out_add,out_minus,out_mult,out_divide,out_compare,a,b);
output wire signed[15:0]out_add;
output wire signed[15:0]out_minus;
output wire signed[15:0]out_mult;
output wire signed[15:0]out_divide;
output wire signed[15:0]out_compare;
input signed [7:0] a;
input signed [7:0] b;

assign out_add = a+b;
assign out_minus = a-b;
assign out_mult = a*b;
assign out_divide = a/b;
assign out_compare =(a>b)?a:b;
endmodule

`timescale 1ns/1ps
module signed_tb;
reg [7:0] a=0;
reg [7:0] b=0;
wire[15:0] out_add,out_minus,out_mult,out_divide,out_compare;

signed_verify U0(
.out_add (out_add),
.out_minus (out_minus),
.out_mult (out_mult),
.out_divide (o