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- module freq_div #(
- parameter N = 3
- ) (
- input clk,
- input rst_n,
- output clk_out
- );
- //counter
- reg [3:0] cnt ;
- always @(posedge clk or negedge rst_n) begin
- if (~rst_n) begin
- cnt <= 0;
- end else if (cnt == 2) begin
- cnt <= 0;
- end else begin
- cnt <= cnt +1;
- end
- end
- //
- reg div1, div2;
- // assign tff_en1 = (cnt == 0) ? 1 : 0;
- // assign tff_en2 = (cnt == 2 )? 1 : 0;
-
- always @(posedge clk ) begin
- if (~rst_n) begin
- div1 <= 0;
- end else if (cnt == 0) begin
- div1 <= ~div1 ;
- end
- end
- always @(negedge clk ) begin
- if (~rst_n) begin
- div2 <= 0;
- end else if (cnt == 2 ) begin
- div2 <= ~div2;
- end
- end
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