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FPGA驱动0.96寸OLED（SSD1306）_fpga驱动oled

作者：Monodyee | 2024-05-29 04:36:23

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fpga驱动oled

目录 

一、七针0.96寸OLED驱动原理

二、SSD1306驱动时序

1、GDDRAM内部结构：

（1）页寻址

 （2）水平寻址

 （3）垂直寻址

2、初始化

3、清屏

4、发送数据

三、子模块源码

1、初始化

2、清屏

3、数据

四、top源码

五、仿真结果

六、板级验证

SPI主机写模式FPGA实现详细请见：FPGA实现SPI写模式（用于SSD1603的0.91寸OLED驱动）_LionelZhao的博客-CSDN博客https://blog.csdn.net/LionelZhao/article/details/128553379

一、七针0.96寸OLED驱动原理

        本实验所使用的七针OLED结构图和电路原理图如下：

         所使用的驱动芯片为SSD1306，通讯协议为4线SPI，七针名称与对应的功能列表如下：

 七根管脚分别为：GND、VCC、CS（片选 低电平有效）、DC（数据/命令控制 1数据，0命令）、D0（同步时钟信号sck）、D1（从机接收端MOSI）、RES（OLED清屏信号 低电平有效）：

        时序图如下：

二、SSD1306驱动时序

1、GDDRAM内部结构：

        GDDRAM（Graphic Display Data RAM ）内部结构如下所示：

         将128*64个像素按8行一个PAGE分为8个PAGE，列SEG0~SEG127，这样通过PAGE和SEG的数值就能将8位长的数据显示在对应的位置上，从上到下为低位到高位，如下图所示。

         GDDRAM三种寻址模式如下所示：

（1）页寻址

        SSD1306默认页寻址模式，通过“20H，02H”命令可以设置寻址模式为页寻址。
  页寻址模式下，寻址只在一页内进行，地址指针不会跳到其他页。每次向GDDRAM写入1Byte显示数据后，列指针会自动+1。当128列都寻址完之后，列指针会重新指向SEG0而页指针仍然保持不变。通过页寻址模式我们可以方便地对一个小区域内数据进行修改。

 （2）水平寻址

       水平寻址模式可以通过指令“20H,00H”来设置。
  水平寻址模式下，每次向GDDRAM写入1Byte数据后，列地址指针自动+1。列指针到达结束列之后会被重置到起始列，而页指针将会+1。页地址指针达到结束页之后，将会自动重置到起始页。

 （3）垂直寻址

       垂直寻址模式可以通过指令“20H,01H”来设置。
  垂直寻址模式下，每次向GDDRAM写入1byte数据之后，页地址指针将会自动+1。页指针到达结束页之后会被重置到0，而列指针将会+1。列地址指针达到结束页之后，将会自动重置到起始列。

2、初始化

        SSD1306驱动过程为：初始化->清屏->发送数据，常见命令如下：

        在上电开始就需要发送控制命令来初始化OLED。

3、清屏

        在发送这一帧数据之前需要先清楚上一帧的数据，只需要遍历PAGE和SEG的所有地址并发送数据8'h00就能实现清屏。

4、发送数据

        与清屏同理，在对应的PAGE和SEG选中的Byte发送相应的数据，这样就能拼凑出想要的图案。

三、子模块源码

1、初始化

        三段式状态机实现，需要配置多少个命令就添加对应数量的状态，在每一个状态发送响应的命令即可。

  1. module OLED_initial(
  2.     input clk,//输入时钟
  3.     input rst_n,//系统复位
  4.     input SPI_done,//SPI发送完成通知
  5.     output DC,//1数据 0命令
  6.     output initial_done,//初始化完成标志
  7.     output SPI_send,//通过SPI发送数据
  8.     output reg [7:0] SPI_data//SPI发送的数据
  9.     );
  10.     //定义初始化所需命令参数
  11.     parameter Display_on  = 8'haf;//开启显示
  12.     parameter Display_off = 8'hae;//关闭显示
  13.     parameter Set_display_clk_0 = 8'hd5;//显示时钟分频控制 命令头
  14.     parameter Set_display_clk_1 = 8'h80;//100帧/秒
  15.     parameter Set_charge_pump_0 = 8'h8d;//电荷泵 命令头
  16.     parameter Set_charge_pump_1 = 8'h14;//开启charge pump
  17.     parameter Set_contrast_0 = 8'h81;//对比度控制 命令头
  18.     parameter Set_contrast_1 = 8'hcf;//207
  19.     parameter Set_precharge_0 = 8'hd9;//预充电周期控制
  20.     parameter Set_precharge_1 = 8'hf1;//预充电15clk 放电1clk
  21.     parameter Set_normal  = 8'ha6;//正常显示
  22.     parameter Set_inverse = 8'ha7;//反转显示
  23.     //状态机参数定义
  24.     localparam S0  = 5'd0;
  25.     localparam S1  = 5'd1;
  26.     localparam S2  = 5'd2;
  27.     localparam S3  = 5'd3;
  28.     localparam S4  = 5'd4;
  29.     localparam S5  = 5'd5;
  30.     localparam S6  = 5'd6;
  31.     localparam S7  = 5'd7;
  32.     localparam S8  = 5'd8;
  33.     localparam S9  = 5'd9;
  34.     localparam S10 = 5'd10;
  35.     localparam S11 = 5'd11;
  36.  
  37.     //状态寄存器
  38.     reg [4:0] cstate,nstate;
  39.  
  40.     assign DC = 0;//发送恒为命令
  41.     assign initial_done = (cstate==S11)?1:0;//初始化完成
  42.     assign SPI_send = (cstate==S11)?0:1;//通过SPI发送数据
  43.  
  44.     //状态转移同步逻辑
  45.     always @(posedge clk or negedge rst_n) begin
  46.         if(!rst_n)begin
  47.             cstate <= S0;
  48.         end
  49.         else if(SPI_done)begin
  50.             cstate <= nstate;
  51.         end
  52.         else begin
  53.             cstate <= cstate;
  54.         end
  55.     end
  56.     //产生下一个状态组合逻辑
  57.     always @(*) begin
  58.         case(cstate)
  59.             S0:nstate = S1;
  60.             S1:nstate = S2;
  61.             S2:nstate = S3;
  62.             S3:nstate = S4;
  63.             S4:nstate = S5;
  64.             S5:nstate = S6;
  65.             S6:nstate = S7;
  66.             S7:nstate = S8;
  67.             S8:nstate = S9;
  68.             S9:nstate = S10;
  69.             S10:nstate= S11;
  70.             S11:nstate= S11;
  71.             default:nstate = S0;
  72.         endcase
  73.     end
  74.     //产生输出组合逻辑
  75.     always @(*) begin
  76.         case(cstate)
  77.             S0:SPI_data = Display_off;
  78.             S1:SPI_data = Set_display_clk_0;
  79.             S2:SPI_data = Set_display_clk_1;
  80.             S3:SPI_data = Set_charge_pump_0;
  81.             S4:SPI_data = Set_charge_pump_1;
  82.             S5:SPI_data = Set_contrast_0;
  83.             S6:SPI_data = Set_contrast_1;
  84.             S7:SPI_data = Set_precharge_0;
  85.             S8:SPI_data = Set_precharge_1;
  86.             S9:SPI_data = Set_inverse;
  87.             S10:SPI_data= Display_on;
  88.             S11:SPI_data= 0;
  89.             default:SPI_data= 0;
  90.         endcase
  91.     end
  92.     
  93. endmodule

2、清屏

        需要定义x_tmp和y_tmp计数器来遍历所有PAGE和SEG选中的一共8*128个Byte发送8'h00。

        发送数据的顺序是先发送PAGE，再发送列高地址然后列低地址，最后发送这一个位置的数据。

  1. module OLED_clear(
  2.     input clk,
  3.     input rst_n,
  4.     input clear_en,//清零使能信号
  5.     input SPI_done,//SPI发送完成通知
  6.     output DC,//1数据 0命令
  7.     output clear_done,//清零完成信号
  8.     output reg SPI_send,//通过SPI发送数据
  9.     output reg [7:0]SPI_data//SPI发送数据
  10.     );
  11.     //状态机状态编码
  12.     localparam S0 = 3'd0;
  13.     localparam S1 = 3'd1;
  14.     localparam S2 = 3'd2;
  15.     localparam S3 = 3'd3;
  16.     localparam S4 = 3'd4;
  17.     localparam S5 = 3'd5;
  18.     localparam S6 = 3'd6;
  19.     //状态寄存器定义
  20.     reg [2:0] cstate,nstate;
  21.     //内部寄存器和信号线声明
  22.     reg [7:0] x_tmp,y_tmp;
  23.     wire [7:0] Set_pos_0,Set_pos_1,Set_pos_2;
  24.  
  25.     assign Set_pos_0 = 8'hb0 | y_tmp;//PAGE地址
  26.     assign Set_pos_1 = (x_tmp[7:4] & 4'hf) | 8'h10;//高位列地址
  27.     assign Set_pos_2 = (x_tmp[3:0] & 4'hf);//低位列地址
  28.     assign DC = (cstate == S4)?1:0;
  29.     assign clear_done = (cstate == S6)?1:0;
  30.  
  31.     always @(posedge clk or negedge rst_n) begin
  32.         if(!rst_n)begin
  33.             x_tmp <= 8'd0;
  34.             y_tmp <= 8'd0;
  35.         end
  36.         else begin
  37.             case (cstate)
  38.                 S0:begin
  39.                     x_tmp <= 8'd0;
  40.                     y_tmp <= 8'd0;
  41.                 end
  42.                 S5:begin
  43.                     if(x_tmp == 130)begin
  44.                         x_tmp <= 8'd0;
  45.                         y_tmp <= y_tmp + 8'd1;
  46.                     end
  47.                     else begin
  48.                         x_tmp <= x_tmp + 8'd1;
  49.                         y_tmp <= y_tmp;
  50.                     end
  51.                 end
  52.                 default:begin
  53.                     x_tmp <= x_tmp;
  54.                     y_tmp <= y_tmp;
  55.                 end
  56.             endcase
  57.         end
  58.     end
  59.     //状态转移同步逻辑
  60.     always @(posedge clk or negedge rst_n) begin
  61.         if(!rst_n)begin
  62.             cstate <= S0;
  63.         end
  64.         else begin
  65.             case (cstate)
  66.                 S1,
  67.                 S2,
  68.                 S3,
  69.                 S4:cstate <= SPI_done?nstate:cstate;
  70.                 default:cstate <= nstate;
  71.             endcase
  72.         end
  73.     end
  74.     //产生下一个状态组合逻辑
  75.     always @(*) begin
  76.         nstate = cstate;
  77.         case(cstate)
  78.             S0:nstate = clear_en?S1:S0;
  79.             S1:nstate = S2;
  80.             S2:nstate = S3;
  81.             S3:nstate = S4;
  82.             S4:nstate = S5;
  83.             S5:nstate = (x_tmp==127 && y_tmp==7)?S6:S1;
  84.             S6:nstate = S0;
  85.             default:nstate = S0;
  86.         endcase
  87.     end
  88.     //产生输出组合逻辑
  89.     always @(*) begin
  90.         if(!rst_n)begin
  91.             SPI_data = 0;
  92.             SPI_send = 0;
  93.         end
  94.         else begin
  95.             case(cstate)
  96.                 S1:begin
  97.                     SPI_data = Set_pos_0;
  98.                     SPI_send = 1;
  99.                 end
  100.                 S2:begin
  101.                     SPI_data = Set_pos_1;
  102.                     SPI_send = 1;
  103.                 end
  104.                 S3:begin
  105.                     SPI_data = Set_pos_2;
  106.                     SPI_send = 1;
  107.                 end
  108.                 S4:begin
  109.                     SPI_data = 0;
  110.                     SPI_send = 1;
  111.                 end
  112.                 default:begin
  113.                     SPI_data = 0;
  114.                     SPI_send = 0;
  115.                 end
  116.             endcase
  117.         end
  118.     end
  119. endmodule
  120.

3、数据

        这里要显示图片：

        需要先取模然后存放到ROM中，将取模软件得到的字模使用coe文件初始化ROM：

  1. ; This .COE file specifies the contents for a block memory of depth=64, and width=128.
  2. memory_initialization_radix=16;
  3. memory_initialization_vector=
  4. 0000000000000000,0000000000000000,
  5. 0000000000000000,0000000000000000,
  6. 0000000000000000,000000001E1E3E3E,
  7. 7CFCF8F0E08080E0,F8F8FC7E3E1F1F1F,
  8. 1F1F3E3E7EFCF8F0,E080000000000000,
  9. 000000001E3E3E7E,FCFCF8F0E0000000,
  10. 0000000000000000,0000000000000000,
  11. 0000000000000000,0000000000000000,
  12. 0000000000000000,0000000000000000,
  13. 0000000000000000,0000000000000000,
  14. 00003CFCFCFCF0C0,8000000000000080,
  15. C0F3FFFFFF3F3FFF,FFFFF1C080000000,
  16. 0000000000030707,07077CFCFCFCF0C0,
  17. 8000000000000080,C0FFFFFFFF3F0000,
  18. 0000000000000000,0000000000000000,
  19. 0000000000000000,0000000000000000,
  20. 0000000000000000,0000000000000000,
  21. 0000000000000000,0000000000000000,
  22. 000000000103070F,0F0F1FDFDFDFCFCF,
  23. 8F87030100000000,0307070F0F0F1FDF,
  24. E0E0E0C0C0800000,000000010387C7CF,
  25. CFFFFFFFFFFFCFCF,8F87030100000000,
  26. 0000000000000000,0000000000000000,
  27. 0000000000000000,0000000000000000,
  28. 0000000000000000,0000000000000000,
  29. 0000000000000000,0000000000000000,
  30. 0000808080800000,000000030307070F,
  31. 1FFFFFFEF8E08080,8080000000000001,
  32. 030303070FFFFFFE,FCF0F8FEFFFF1F0F,
  33. 070303030303070F,1FFFFFFEF8000000,
  34. 0000000000000000,0000000000000000,
  35. 0000000000000000,0000000000000000,
  36. 0000000000000000,0000000000000000,
  37. 0000000000000000,0000000000000000,
  38. 00000F3F7FFFFEF8,F0E0E0C0C0E0E0F0,
  39. F8FFFF7F1F070F1F,3F7FFCF8F0F0E0E0,
  40. E0E0F0F8FCFF7F3F,0F030F3F7FFFFCF8,
  41. F0E0E0E000000000,0000000000000000
  42. 0000000000000000,0000000000000000,
  43. 0000000000000000,0000000000000000,
  44. 0000000000000000,0000000000000000,
  45. 0000000000000000,0000000000000000,
  46. 00000080C0E0F1F1,FBFB7B7B03030303,
  47. 0100000000000000,C0E0E0F1F1F9F9F9,
  48. F9F9F9F1F0E0E0C0,00000080C0E0F0F1,
  49. F9F97B7B00000000,0000000000000000,
  50. 0000000000000000,0000000000000000,
  51. 0000000000000000,0000000000000000,
  52. 0000000000000000,0000000000000000,
  53. 0000000000000000,0000000000000000,
  54. 0000FEFFFFFFC701,0000000000000000,
  55. 00C0F0F0F0E0FCFF,FFFFDF0301000000,
  56. 00000001031F3F3F,3F3CFEFFFFFF8701,
  57. 0000000000000000,00E0F0F0F0E00000,
  58. 0000000000000000,0000000000000000,
  59. 0000000000000000,0000000000000000,
  60. 0000000000000000,0000000000000000,
  61. 0000000000000000,0000000000000000,
  62. 000001070F1F3F3F,7E7C7C7C7C7C7C7E,
  63. 3F3F1F0F07010003,0F1F3F3F7C7C7878,
  64. 3000000000000000,000001070F1F3F3F,
  65. 7E7C7C7C7C7C7C7E,3F1F1F0F03000000,
  66. 0000000000000000,0000000000000000,
  67. 0000000000000000,0000000000000000;

        例化一个 ROM的IP，配置如下：

         将coe文件添加并初始化：

         数据发送模块，每次从ROM中读取64位数据分8次发送：

  1. module OLED_write_data(
  2.     input clk,
  3.     input rst_n,
  4.     input write_en,
  5.     input SPI_done,
  6.     input [63:0]write_data,//需要发送的数据
  7.     input [6:0]set_pos_x,
  8.     input [2:0]set_pos_y,
  9.     output DC,
  10.     output write_done,//写数据完成标志
  11.     output reg SPI_send,//SPI传输使能
  12.     output reg [7:0] SPI_data//需要SPI发送的字节数据
  13.     );
  14.     //状态机状态编码
  15.     localparam IDLE = 3'd0;//空闲状态
  16.     localparam POS0 = 3'd1;//设置页地址
  17.     localparam POS1 = 3'd2;//设置列高地址
  18.     localparam POS2 = 3'd3;//设置列低地址
  19.     localparam DATA = 3'd4;//发送对应的数据
  20.     localparam JUDGE= 3'd5;//判断是否发送完成
  21.     localparam STOP = 3'd6;//停止发送
  22.     //状态寄存器
  23.     reg [2:0] cstate,nstate;
  24.     //内部寄存器和信号线声明
  25.     reg [2:0] count;//发送循环数计数器
  26.     reg [63:0] write_data_reg;//暂存需要发送的数据
  27.     reg [7:0] x_tmp,y_tmp;
  28.     wire [7:0] Set_pos_0,Set_pos_1,Set_pos_2;
  29.  
  30.     assign Set_pos_0 = 8'hb0 | y_tmp;              //页地址
  31.     assign Set_pos_1 = (x_tmp[7:4] & 4'hf) | 8'h10;//高位列地址
  32.     assign Set_pos_2 = (x_tmp[3:0] & 4'hf);        //低位列地址
  33.     
  34.     assign DC = (cstate == DATA)?1:0;
  35.     assign write_done = (cstate == STOP)?1:0;
  36.  
  37.     always @(posedge clk or negedge rst_n) begin
  38.         if(!rst_n)begin
  39.             x_tmp <= 8'd0;
  40.             y_tmp <= 8'd0;
  41.             write_data_reg <= 0;
  42.             count <= 0;
  43.         end
  44.         else begin
  45.             case (cstate)
  46.                 IDLE:begin
  47.                     x_tmp <= {1'b0,set_pos_x};
  48.                     y_tmp <= {5'd0,set_pos_y};
  49.                     write_data_reg <= write_data;
  50.                     count <= 0;
  51.                 end
  52.                 JUDGE:begin
  53.                     x_tmp <= x_tmp + 8'd1;
  54.                     // y_tmp <= y_tmp;
  55.                     // if(x_tmp>122) y_tmp<=y_tmp+1;
  56.                     write_data_reg <= (write_data_reg<<8);
  57.                     count <= count + 1;
  58.                 end
  59.                 default:begin
  60.                     x_tmp <= x_tmp;
  61.                     y_tmp <= y_tmp;
  62.                     write_data_reg <= write_data_reg;
  63.                     count <= count;
  64.                 end
  65.             endcase
  66.         end
  67.     end
  68.  
  69.     //状态转移同步逻辑
  70.     always @(posedge clk or negedge rst_n) begin
  71.         if(!rst_n)begin
  72.             cstate <= IDLE;
  73.         end
  74.         else begin
  75.             case (cstate)
  76.                 POS0,
  77.                 POS1,
  78.                 POS2,
  79.                 DATA:cstate <= SPI_done?nstate:cstate;
  80.                 default:cstate <= nstate;
  81.             endcase
  82.         end
  83.     end
  84.  
  85.     //产生下一个状态组合逻辑
  86.     always @(*) begin
  87.         case(cstate)
  88.             IDLE:nstate = write_en?POS0:IDLE;
  89.             POS0:nstate = POS1;
  90.             POS1:nstate = POS2;
  91.             POS2:nstate = DATA;
  92.             DATA:nstate = JUDGE;
  93.             JUDGE:nstate = (&count)?STOP:POS0;
  94.             STOP:nstate = IDLE;
  95.             default:nstate = IDLE;
  96.         endcase
  97.     end
  98.     
  99.     //产生输出组合逻辑
  100.     always @(*)begin
  101.         if(!rst_n)begin
  102.             SPI_data = 0;
  103.             SPI_send = 0;
  104.         end
  105.         else begin
  106.             case(cstate)
  107.                 IDLE:begin
  108.                     SPI_data = 0;
  109.                     SPI_send = 0;
  110.                 end
  111.                 POS0:begin
  112.                     SPI_data = Set_pos_0;
  113.                     SPI_send = 1;
  114.                 end
  115.                 POS1:begin
  116.                     SPI_data = Set_pos_1;
  117.                     SPI_send = 1;
  118.                 end
  119.                 POS2:begin
  120.                     SPI_data = Set_pos_2;
  121.                     SPI_send = 1;
  122.                 end
  123.                 DATA:begin
  124.                     SPI_data = write_data_reg[63:56];
  125.                     SPI_send = 1;
  126.                 end
  127.                 JUDGE:begin
  128.                     SPI_data = SPI_data;
  129.                     SPI_send = 0;
  130.                 end
  131.                 STOP:begin
  132.                     SPI_data = SPI_data;
  133.                     SPI_send = SPI_send;
  134.                 end
  135.                 default:begin
  136.                     SPI_data = 0;
  137.                     SPI_send = 0;
  138.                 end
  139.             endcase
  140.         end
  141.     end
  142.     
  143. endmodule

四、top源码

        由于需要发送8*128=1024个Byte的数据，而发送数据模块一次从ROM中读取1*8个Byte，因此需要读取ROM128次，这就需要128个读数据状态和一个初始化状态、一个清屏状态和一个停止发送状态，使用格雷码来编码状态机并使用脚本来生成top代码。

  1. module top(
  2.     input sys_clk,//系统时钟 100MHz
  3.     input sys_rst_n,//系统复位
  5.     output sclk,//同步时钟 
  6.     output sck,
  7.     output reg res=0,//OLED清屏信号 低电平有效
  8.     output MOSI,//主机输出 从机输入
  9.     output CS,//片选信号 低电平有效
  10.     output DC//1数据 0命令
  11.     );
  12.     //状态编码
  13.     localparam INIT= 9'b000000000;//初始化
  14.     localparam CLR = 9'b000000001;//清屏
  15.     localparam D0  = 9'b000000011;//发送数据周期
  16.     localparam D1  = 9'b000000010;
  17.     localparam D2  = 9'b000000110;
  18.     localparam D3  = 9'b000000111;
  19.     localparam D4  = 9'b000000101;
  20.     localparam D5  = 9'b000000100;
  21.     localparam D6  = 9'b000001100;
  22.     localparam D7  = 9'b000001101;
  23.     localparam D8  = 9'b000001111;
  24.     localparam D9  = 9'b000001110;
  25.     localparam D10 = 9'b000001010;
  26.     localparam D11 = 9'b000001011;
  27.     localparam D12 = 9'b000001001;
  28.     localparam D13 = 9'b000001000;
  29.     localparam D14 = 9'b000011000;
  30.     localparam D15 = 9'b000011001;
  31.     localparam D16 = 9'b000011011;
  32.     localparam D17 = 9'b000011010;
  33.     localparam D18 = 9'b000011110;
  34.     localparam D19 = 9'b000011111;
  35.     localparam D20 = 9'b000011101;
  36.     localparam D21 = 9'b000011100;
  37.     localparam D22 = 9'b000010100;
  38.     localparam D23 = 9'b000010101;
  39.     localparam D24 = 9'b000010111;
  40.     localparam D25 = 9'b000010110;
  41.     localparam D26 = 9'b000010010;
  42.     localparam D27 = 9'b000010011;
  43.     localparam D28 = 9'b000010001;
  44.     localparam D29 = 9'b000010000;
  45.     localparam D30 = 9'b000110000;
  46.     localparam D31 = 9'b000110001;
  47.     localparam D32 = 9'b000110011;
  48.     localparam D33 = 9'b000110010;
  49.     localparam D34 = 9'b000110110;
  50.     localparam D35 = 9'b000110111;
  51.     localparam D36 = 9'b000110101;
  52.     localparam D37 = 9'b000110100;
  53.     localparam D38 = 9'b000111100;
  54.     localparam D39 = 9'b000111101;
  55.     localparam D40 = 9'b000111111;
  56.     localparam D41 = 9'b000111110;
  57.     localparam D42 = 9'b000111010;
  58.     localparam D43 = 9'b000111011;
  59.     localparam D44 = 9'b000111001;
  60.     localparam D45 = 9'b000111000;
  61.     localparam D46 = 9'b000101000;
  62.     localparam D47 = 9'b000101001;
  63.     localparam D48 = 9'b000101011;
  64.     localparam D49 = 9'b000101010;
  65.     localparam D50 = 9'b000101110;
  66.     localparam D51 = 9'b000101111;
  67.     localparam D52 = 9'b000101101;
  68.     localparam D53 = 9'b000101100;
  69.     localparam D54 = 9'b000100100;
  70.     localparam D55 = 9'b000100101;
  71.     localparam D56 = 9'b000100111;
  72.     localparam D57 = 9'b000100110;
  73.     localparam D58 = 9'b000100010;
  74.     localparam D59 = 9'b000100011;
  75.     localparam D60 = 9'b000100001;
  76.     localparam D61 = 9'b000100000;
  77.     localparam D62 = 9'b001100000;
  78.     localparam D63 = 9'b001100001;
  79.     localparam D64 = 9'b001100011;
  80.     localparam D65 = 9'b001100010;
  81.     localparam D66 = 9'b001100110;
  82.     localparam D67 = 9'b001100111;
  83.     localparam D68 = 9'b001100101;
  84.     localparam D69 = 9'b001100100;
  85.     localparam D70 = 9'b001101100;
  86.     localparam D71 = 9'b001101101;
  87.     localparam D72 = 9'b001101111;
  88.     localparam D73 = 9'b001101110;
  89.     localparam D74 = 9'b001101010;
  90.     localparam D75 = 9'b001101011;
  91.     localparam D76 = 9'b001101001;
  92.     localparam D77 = 9'b001101000;
  93.     localparam D78 = 9'b001111000;
  94.     localparam D79 = 9'b001111001;
  95.     localparam D80 = 9'b001111011;
  96.     localparam D81 = 9'b001111010;
  97.     localparam D82 = 9'b001111110;
  98.     localparam D83 = 9'b001111111;
  99.     localparam D84 = 9'b001111101;
  100.     localparam D85 = 9'b001111100;
  101.     localparam D86 = 9'b001110100;
  102.     localparam D87 = 9'b001110101;
  103.     localparam D88 = 9'b001110111;
  104.     localparam D89 = 9'b001110110;
  105.     localparam D90 = 9'b001110010;
  106.     localparam D91 = 9'b001110011;
  107.     localparam D92 = 9'b001110001;
  108.     localparam D93 = 9'b001110000;
  109.     localparam D94 = 9'b001010000;
  110.     localparam D95 = 9'b001010001;
  111.     localparam D96 = 9'b001010011;
  112.     localparam D97 = 9'b001010010;
  113.     localparam D98 = 9'b001010110;
  114.     localparam D99 = 9'b001010111;
  115.     localparam D100 = 9'b001010101;
  116.     localparam D101 = 9'b001010100;
  117.     localparam D102 = 9'b001011100;
  118.     localparam D103 = 9'b001011101;
  119.     localparam D104 = 9'b001011111;
  120.     localparam D105 = 9'b001011110;
  121.     localparam D106 = 9'b001011010;
  122.     localparam D107 = 9'b001011011;
  123.     localparam D108 = 9'b001011001;
  124.     localparam D109 = 9'b001011000;
  125.     localparam D110 = 9'b001001000;
  126.     localparam D111 = 9'b001001001;
  127.     localparam D112 = 9'b001001011;
  128.     localparam D113 = 9'b001001010;
  129.     localparam D114 = 9'b001001110;
  130.     localparam D115 = 9'b001001111;
  131.     localparam D116 = 9'b001001101;
  132.     localparam D117 = 9'b001001100;
  133.     localparam D118 = 9'b001000100;
  134.     localparam D119 = 9'b001000101;
  135.     localparam D120 = 9'b001000111;
  136.     localparam D121 = 9'b001000110;
  137.     localparam D122 = 9'b001000010;
  138.     localparam D123 = 9'b001000011;
  139.     localparam D124 = 9'b001000001;
  140.     localparam D125 = 9'b001000000;
  141.     localparam D126 = 9'b011000000;
  142.     localparam D127 = 9'b011000001;
  143.     localparam STOP = 9'b011000011;//发送结束
  144.  
  145.     //从ROM中读取需要发送的数据
  146.     reg [6:0]ROM_addr=0;//ROM访问地址
  147.     wire [63:0]ROM_data;//ROM输出数据
  148.  
  149.     blk_mem_gen_0 rom(
  150.         .clka(sys_clk),   // input wire clka
  151.         .addra(ROM_addr), // input wire [6 : 0] addra
  152.         .douta(ROM_data)  // output wire [63 : 0] douta
  153.     );
  154.     
  155.     //状泰寄存器
  156.     reg [8:0] cstate,nstate=0;
  157.     reg [31:0]reset_cnt=0;//复位控制计数�??
  158.     reg rst_n=0;
  159.  
  160.     //上电复位逻辑
  161.     always @(posedge sys_clk) begin
  162.       if(reset_cnt >= 30000)
  163.             reset_cnt <= 30000;
  164.         else
  165.             reset_cnt <= reset_cnt + 1;
  166.     end
  167.  
  168.     always @(posedge sys_clk) begin
  169.         if(reset_cnt == 10)begin
  170.             res <= 1;
  171.             rst_n <= 1;
  172.         end
  173.         else if(reset_cnt == 10000)begin
  174.             res <= 0;
  175.             rst_n <= 0;
  176.         end
  177.         else if(reset_cnt == 20000)begin
  178.             res <= 1;
  179.             rst_n <= rst_n;
  180.         end
  181.         else if(reset_cnt == 30000)begin
  182.             res <= res;
  183.             rst_n <= 1;
  184.         end
  185.         else begin
  186.             res <= res;
  187.             rst_n <= rst_n;
  188.         end
  189.     end
  190.  
  191.     //SPI主机例化
  192.     reg SPI_send=0;//SPI发�?�使能信�??
  193.     reg [7:0] SPI_data=0;//SPI�??要发送的字节数据
  194.     wire SPI_done;//SPI发�?�完成标�??
  195.     reg DC_in=0;//数据/命令控制�??
  196.  
  197.     SPI_Master SPI_Master_(
  198.         .sys_clk (sys_clk),
  199.         .rst_n(1'b1),
  200.         .SPI_send (SPI_send),
  201.         .SPI_data (SPI_data),
  202.         .DC_in (DC_in),
  203.         .DC_out (DC),
  204.         .sclk (sclk),
  205.         .MOSI (MOSI),
  206.         .CS (CS),
  207.         .SPI_done (SPI_done),
  208.         .sck (sck)
  209.     );
  210.   
  211.     //OLED初始化模块实例化
  212.     wire SPI_send_init;
  213.     wire DC_init;
  214.     wire [7:0] SPI_data_init;
  215.     wire initial_done;
  216.                                     
  217.     OLED_initial OLED_initial_(
  218.         .clk (sclk),
  219.         .rst_n (rst_n),
  220.         .SPI_done (SPI_done),
  221.         .DC (DC_init),
  222.         .initial_done (initial_done),
  223.         .SPI_send (SPI_send_init),
  224.         .SPI_data (SPI_data_init)
  225.     );
  226.  
  227.     //OLED写信号模块实例化,讲输入的64位向量拆分发送
  228.     reg [6:0]set_pos_x=0;//列的索引 0->127
  229.     reg [2:0]set_pos_y=0;//PAGE的索引 0->7
  230.     wire write_en;
  231.     wire DC_write;
  232.     wire write_done;
  233.     reg [63:0]write_data=0;
  234.     wire SPI_send_write;
  235.     wire [7:0] SPI_data_write;
  236.  
  237.     assign write_en = (cstate==INIT || cstate == CLR || cstate == STOP)?0:1;
  238.  
  239.     OLED_write_data OLED_write_(
  240.         .clk (sclk),
  241.         .rst_n (rst_n),
  242.         .write_en (write_en),
  243.         .SPI_done (SPI_done),
  244.         .write_data (write_data),
  245.         .set_pos_x (set_pos_x),
  246.         .set_pos_y (set_pos_y),
  247.         .DC (DC_write),
  248.         .write_done (write_done),
  249.         .SPI_send (SPI_send_write),
  250.         .SPI_data  (SPI_data_write)
  251.     );
  252.  
  253.     //OLED清屏模块实例化
  254.     wire clear_en;
  255.     wire DC_clear;
  256.     wire clear_done;
  257.     wire SPI_send_clear;
  258.     wire [7:0]SPI_data_clear;
  259.  
  260.     assign clear_en = (cstate==CLR)?1:0;
  261.  
  262.     OLED_clear OLED_clear_(
  263.         .clk (sclk),
  264.         .rst_n (rst_n),
  265.         .clear_en (clear_en),
  266.         .SPI_done (SPI_done),
  267.         .DC (DC_clear),
  268.         .clear_done (clear_done),
  269.         .SPI_send (SPI_send_clear),
  270.         .SPI_data (SPI_data_clear)
  271.     );
  272.  
  273.     //状态转移同步逻辑
  274.     always @(posedge sclk) begin
  275.         if(!rst_n)begin
  276.             cstate <= INIT;
  277.         end
  278.         else begin
  279.             cstate <= nstate;
  280.         end
  281.     end
  282.     //产生下一个状态组合逻辑
  283.     always @(*) begin
  284.         case(cstate)
  285.             INIT:nstate = initial_done?CLR:INIT;
  286.             CLR :nstate = clear_done?D0:CLR;
  287.             D0:nstate = write_done?D1:D0;
  288.             D1:nstate = write_done?D2:D1;
  289.             D2:nstate = write_done?D3:D2;
  290.             D3:nstate = write_done?D4:D3;
  291.             D4:nstate = write_done?D5:D4;
  292.             D5:nstate = write_done?D6:D5;
  293.             D6:nstate = write_done?D7:D6;
  294.             D7:nstate = write_done?D8:D7;
  295.             D8:nstate = write_done?D9:D8;
  296.             D9:nstate = write_done?D10:D9;
  297.             D10:nstate = write_done?D11:D10;
  298.             D11:nstate = write_done?D12:D11;
  299.             D12:nstate = write_done?D13:D12;
  300.             D13:nstate = write_done?D14:D13;
  301.             D14:nstate = write_done?D15:D14;
  302.             D15:nstate = write_done?D16:D15;
  303.             D16:nstate = write_done?D17:D16;
  304.             D17:nstate = write_done?D18:D17;
  305.             D18:nstate = write_done?D19:D18;
  306.             D19:nstate = write_done?D20:D19;
  307.             D20:nstate = write_done?D21:D20;
  308.             D21:nstate = write_done?D22:D21;
  309.             D22:nstate = write_done?D23:D22;
  310.             D23:nstate = write_done?D24:D23;
  311.             D24:nstate = write_done?D25:D24;
  312.             D25:nstate = write_done?D26:D25;
  313.             D26:nstate = write_done?D27:D26;
  314.             D27:nstate = write_done?D28:D27;
  315.             D28:nstate = write_done?D29:D28;
  316.             D29:nstate = write_done?D30:D29;
  317.             D30:nstate = write_done?D31:D30;
  318.             D31:nstate = write_done?D32:D31;
  319.             D32:nstate = write_done?D33:D32;
  320.             D33:nstate = write_done?D34:D33;
  321.             D34:nstate = write_done?D35:D34;
  322.             D35:nstate = write_done?D36:D35;
  323.             D36:nstate = write_done?D37:D36;
  324.             D37:nstate = write_done?D38:D37;
  325.             D38:nstate = write_done?D39:D38;
  326.             D39:nstate = write_done?D40:D39;
  327.             D40:nstate = write_done?D41:D40;
  328.             D41:nstate = write_done?D42:D41;
  329.             D42:nstate = write_done?D43:D42;
  330.             D43:nstate = write_done?D44:D43;
  331.             D44:nstate = write_done?D45:D44;
  332.             D45:nstate = write_done?D46:D45;
  333.             D46:nstate = write_done?D47:D46;
  334.             D47:nstate = write_done?D48:D47;
  335.             D48:nstate = write_done?D49:D48;
  336.             D49:nstate = write_done?D50:D49;
  337.             D50:nstate = write_done?D51:D50;
  338.             D51:nstate = write_done?D52:D51;
  339.             D52:nstate = write_done?D53:D52;
  340.             D53:nstate = write_done?D54:D53;
  341.             D54:nstate = write_done?D55:D54;
  342.             D55:nstate = write_done?D56:D55;
  343.             D56:nstate = write_done?D57:D56;
  344.             D57:nstate = write_done?D58:D57;
  345.             D58:nstate = write_done?D59:D58;
  346.             D59:nstate = write_done?D60:D59;
  347.             D60:nstate = write_done?D61:D60;
  348.             D61:nstate = write_done?D62:D61;
  349.             D62:nstate = write_done?D63:D62;
  350.             D63:nstate = write_done?D64:D63;
  351.             D64:nstate = write_done?D65:D64;
  352.             D65:nstate = write_done?D66:D65;
  353.             D66:nstate = write_done?D67:D66;
  354.             D67:nstate = write_done?D68:D67;
  355.             D68:nstate = write_done?D69:D68;
  356.             D69:nstate = write_done?D70:D69;
  357.             D70:nstate = write_done?D71:D70;
  358.             D71:nstate = write_done?D72:D71;
  359.             D72:nstate = write_done?D73:D72;
  360.             D73:nstate = write_done?D74:D73;
  361.             D74:nstate = write_done?D75:D74;
  362.             D75:nstate = write_done?D76:D75;
  363.             D76:nstate = write_done?D77:D76;
  364.             D77:nstate = write_done?D78:D77;
  365.             D78:nstate = write_done?D79:D78;
  366.             D79:nstate = write_done?D80:D79;
  367.             D80:nstate = write_done?D81:D80;
  368.             D81:nstate = write_done?D82:D81;
  369.             D82:nstate = write_done?D83:D82;
  370.             D83:nstate = write_done?D84:D83;
  371.             D84:nstate = write_done?D85:D84;
  372.             D85:nstate = write_done?D86:D85;
  373.             D86:nstate = write_done?D87:D86;
  374.             D87:nstate = write_done?D88:D87;
  375.             D88:nstate = write_done?D89:D88;
  376.             D89:nstate = write_done?D90:D89;
  377.             D90:nstate = write_done?D91:D90;
  378.             D91:nstate = write_done?D92:D91;
  379.             D92:nstate = write_done?D93:D92;
  380.             D93:nstate = write_done?D94:D93;
  381.             D94:nstate = write_done?D95:D94;
  382.             D95:nstate = write_done?D96:D95;
  383.             D96:nstate = write_done?D97:D96;
  384.             D97:nstate = write_done?D98:D97;
  385.             D98:nstate = write_done?D99:D98;
  386.             D99:nstate = write_done?D100:D99;
  387.             D100:nstate = write_done?D101:D100;
  388.             D101:nstate = write_done?D102:D101;
  389.             D102:nstate = write_done?D103:D102;
  390.             D103:nstate = write_done?D104:D103;
  391.             D104:nstate = write_done?D105:D104;
  392.             D105:nstate = write_done?D106:D105;
  393.             D106:nstate = write_done?D107:D106;
  394.             D107:nstate = write_done?D108:D107;
  395.             D108:nstate = write_done?D109:D108;
  396.             D109:nstate = write_done?D110:D109;
  397.             D110:nstate = write_done?D111:D110;
  398.             D111:nstate = write_done?D112:D111;
  399.             D112:nstate = write_done?D113:D112;
  400.             D113:nstate = write_done?D114:D113;
  401.             D114:nstate = write_done?D115:D114;
  402.             D115:nstate = write_done?D116:D115;
  403.             D116:nstate = write_done?D117:D116;
  404.             D117:nstate = write_done?D118:D117;
  405.             D118:nstate = write_done?D119:D118;
  406.             D119:nstate = write_done?D120:D119;
  407.             D120:nstate = write_done?D121:D120;
  408.             D121:nstate = write_done?D122:D121;
  409.             D122:nstate = write_done?D123:D122;
  410.             D123:nstate = write_done?D124:D123;
  411.             D124:nstate = write_done?D125:D124;
  412.             D125:nstate = write_done?D126:D125;
  413.             D126:nstate = write_done?D127:D126;
  414.             D127:nstate = write_done?STOP:D127;
  415.             STOP:nstate = sys_rst_n?STOP:INIT;
  416.             default:nstate = INIT;
  417.         endcase
  418.     end
  419.  
  420.     //根据状态提供相应的输出
  421.     wire PAGE_inc_flag = (&set_pos_x)?1:0;
  422.     always @(*) begin
  423.         if(!rst_n)begin
  424.             set_pos_x = 0;
  425.             set_pos_y = 0;
  426.             write_data= 64'd0;
  427.         end
  428.         else begin
  429.             case (cstate)
  430. //PAGE0
  431.                 D0:begin
  432.                     set_pos_x = 0;
  433.                     set_pos_y = 0;
  434.                     write_data  = ROM_data;
  435.                     ROM_addr = 0;
  436.                 end
  437.                 D1:begin
  438.                     set_pos_x = 8;
  439.                     set_pos_y = 0;
  440.                     write_data  = ROM_data;
  441.                     ROM_addr = 1;
  442.                 end
  443.                 D2:begin
  444.                     set_pos_x = 16;
  445.                     set_pos_y = 0;
  446.                     write_data  = ROM_data;
  447.                     ROM_addr = 2;
  448.                 end
  449.                 D3:begin
  450.                     set_pos_x = 24;
  451.                     set_pos_y = 0;
  452.                     write_data  = ROM_data;
  453.                     ROM_addr = 3;
  454.                 end
  455.                 D4:begin
  456.                     set_pos_x = 32;
  457.                     set_pos_y = 0;
  458.                     write_data  = ROM_data;
  459.                     ROM_addr = 4;
  460.                 end
  461.                 D5:begin
  462.                     set_pos_x = 40;
  463.                     set_pos_y = 0;
  464.                     write_data  = ROM_data;
  465.                     ROM_addr = 5;
  466.                 end
  467.                 D6:begin
  468.                     set_pos_x = 48;
  469.                     set_pos_y = 0;
  470.                     write_data  = ROM_data;
  471.                     ROM_addr = 6;
  472.                 end
  473.                 D7:begin
  474.                     set_pos_x = 56;
  475.                     set_pos_y = 0;
  476.                     write_data  = ROM_data;
  477.                     ROM_addr = 7;
  478.                 end
  479.                 D8:begin
  480.                     set_pos_x = 64;
  481.                     set_pos_y = 0;
  482.                     write_data  = ROM_data;
  483.                     ROM_addr = 8;
  484.                 end
  485.                 D9:begin
  486.                     set_pos_x = 72;
  487.                     set_pos_y = 0;
  488.                     write_data  = ROM_data;
  489.                     ROM_addr = 9;
  490.                 end
  491.                 D10:begin
  492.                     set_pos_x = 80;
  493.                     set_pos_y = 0;
  494.                     write_data  = ROM_data;
  495.                     ROM_addr = 10;
  496.                 end
  497.                 D11:begin
  498.                     set_pos_x = 88;
  499.                     set_pos_y = 0;
  500.                     write_data  = ROM_data;
  501.                     ROM_addr = 11;
  502.                 end
  503.                 D12:begin
  504.                     set_pos_x = 96;
  505.                     set_pos_y = 0;
  506.                     write_data  = ROM_data;
  507.                     ROM_addr = 12;
  508.                 end
  509.                 D13:begin
  510.                     set_pos_x = 104;
  511.                     set_pos_y = 0;
  512.                     write_data  = ROM_data;
  513.                     ROM_addr = 13;
  514.                 end
  515.                 D14:begin
  516.                     set_pos_x = 112;
  517.                     set_pos_y = 0;
  518.                     write_data  = ROM_data;
  519.                     ROM_addr = 14;
  520.                 end
  521.                 D15:begin
  522.                     set_pos_x = 120;
  523.                     set_pos_y = 0;
  524.                     write_data  = ROM_data;
  525.                     ROM_addr = 15;
  526.                 end
  527. //PAGE1
  528.                 D16:begin
  529.                     set_pos_x = 0;
  530.                     set_pos_y = 1;
  531.                     write_data  = ROM_data;
  532.                     ROM_addr = 16;
  533.                 end
  534.                 D17:begin
  535.                     set_pos_x = 8;
  536.                     set_pos_y = 1;
  537.                     write_data  = ROM_data;
  538.                     ROM_addr = 17;
  539.                 end
  540.                 D18:begin
  541.                     set_pos_x = 16;
  542.                     set_pos_y = 1;
  543.                     write_data  = ROM_data;
  544.                     ROM_addr = 18;
  545.                 end
  546.                 D19:begin
  547.                     set_pos_x = 24;
  548.                     set_pos_y = 1;
  549.                     write_data  = ROM_data;
  550.                     ROM_addr = 19;
  551.                 end
  552.                 D20:begin
  553.                     set_pos_x = 32;
  554.                     set_pos_y = 1;
  555.                     write_data  = ROM_data;
  556.                     ROM_addr = 20;
  557.                 end
  558.                 D21:begin
  559.                     set_pos_x = 40;
  560.                     set_pos_y = 1;
  561.                     write_data  = ROM_data;
  562.                     ROM_addr = 21;
  563.                 end
  564.                 D22:begin
  565.                     set_pos_x = 48;
  566.                     set_pos_y = 1;
  567.                     write_data  = ROM_data;
  568.                     ROM_addr = 22;
  569.                 end
  570.                 D23:begin
  571.                     set_pos_x = 56;
  572.                     set_pos_y = 1;
  573.                     write_data  = ROM_data;
  574.                     ROM_addr = 23;
  575.                 end
  576.                 D24:begin
  577.                     set_pos_x = 64;
  578.                     set_pos_y = 1;
  579.                     write_data  = ROM_data;
  580.                     ROM_addr = 24;
  581.                 end
  582.                 D25:begin
  583.                     set_pos_x = 72;
  584.                     set_pos_y = 1;
  585.                     write_data  = ROM_data;
  586.                     ROM_addr = 25;
  587.                 end
  588.                 D26:begin
  589.                     set_pos_x = 80;
  590.                     set_pos_y = 1;
  591.                     write_data  = ROM_data;
  592.                     ROM_addr = 26;
  593.                 end
  594.                 D27:begin
  595.                     set_pos_x = 88;
  596.                     set_pos_y = 1;
  597.                     write_data  = ROM_data;
  598.                     ROM_addr = 27;
  599.                 end
  600.                 D28:begin
  601.                     set_pos_x = 96;
  602.                     set_pos_y = 1;
  603.                     write_data  = ROM_data;
  604.                     ROM_addr = 28;
  605.                 end                
  606.                 D29:begin
  607.                     set_pos_x = 104;
  608.                     set_pos_y = 1;
  609.                     write_data  = ROM_data;
  610.                     ROM_addr = 29;
  611.                 end
  612.                 D30:begin
  613.                     set_pos_x = 112;
  614.                     set_pos_y = 1;
  615.                     write_data  = ROM_data;
  616.                     ROM_addr = 30;
  617.                 end
  618.                 D31:begin
  619.                     set_pos_x = 120;
  620.                     set_pos_y = 1;
  621.                     write_data  = ROM_data;
  622.                     ROM_addr = 31;
  623.                 end
  624. //PAGE2
  625.                 D32:begin
  626.                     set_pos_x = 0;
  627.                     set_pos_y = 2;
  628.                     write_data  = ROM_data;
  629.                     ROM_addr = 32;
  630.                 end
  631.                 D33:begin
  632.                     set_pos_x = 8;
  633.                     set_pos_y = 2;
  634.                     write_data  = ROM_data;
  635.                     ROM_addr = 33;
  636.                 end
  637.                 D34:begin
  638.                     set_pos_x = 16;
  639.                     set_pos_y = 2;
  640.                     write_data  = ROM_data;
  641.                     ROM_addr = 34;
  642.                 end
  643.                 D35:begin
  644.                     set_pos_x = 24;
  645.                     set_pos_y = 2;
  646.                     write_data  = ROM_data;
  647.                     ROM_addr = 35;
  648.                 end
  649.                 D36:begin
  650.                     set_pos_x = 32;
  651.                     set_pos_y = 2;
  652.                     write_data  = ROM_data;
  653.                     ROM_addr = 36;
  654.                 end
  655.                 D37:begin
  656.                     set_pos_x = 40;
  657.                     set_pos_y = 2;
  658.                     write_data  = ROM_data;
  659.                     ROM_addr = 37;
  660.                 end
  661.                 D38:begin
  662.                     set_pos_x = 48;
  663.                     set_pos_y = 2;
  664.                     write_data  = ROM_data;
  665.                     ROM_addr = 38;
  666.                 end
  667.                 D39:begin
  668.                     set_pos_x = 56;
  669.                     set_pos_y = 2;
  670.                     write_data  = ROM_data;
  671.                     ROM_addr = 39;
  672.                 end
  673.                 D40:begin
  674.                     set_pos_x = 64;
  675.                     set_pos_y = 2;
  676.                     write_data  = ROM_data;
  677.                     ROM_addr = 40;
  678.                 end
  679.                 D41:begin
  680.                     set_pos_x = 72;
  681.                     set_pos_y = 2;
  682.                     write_data  = ROM_data;
  683.                     ROM_addr = 41;
  684.                 end
  685.                 D42:begin
  686.                     set_pos_x = 80;
  687.                     set_pos_y = 2;
  688.                     write_data  = ROM_data;
  689.                     ROM_addr = 42;
  690.                 end
  691.                 D43:begin
  692.                     set_pos_x = 88;
  693.                     set_pos_y = 2;
  694.                     write_data  = ROM_data;
  695.                     ROM_addr = 43;
  696.                 end
  697.                 D44:begin
  698.                     set_pos_x = 96;
  699.                     set_pos_y = 2;
  700.                     write_data  = ROM_data;
  701.                     ROM_addr = 44;
  702.                 end
  703.                 D45:begin
  704.                     set_pos_x = 104;
  705.                     set_pos_y = 2;
  706.                     write_data  = ROM_data;
  707.                     ROM_addr = 45;
  708.                 end
  709.                 D46:begin
  710.                     set_pos_x = 112;
  711.                     set_pos_y = 2;
  712.                     write_data  = ROM_data;
  713.                     ROM_addr = 46;
  714.                 end
  715.                 D47:begin
  716.                     set_pos_x = 120;
  717.                     set_pos_y = 2;
  718.                     write_data  = ROM_data;
  719.                     ROM_addr = 47;
  720.                 end
  721. //PAGE3
  722.                 D48:begin
  723.                     set_pos_x = 0;
  724.                     set_pos_y = 3;
  725.                     write_data  = ROM_data;
  726.                     ROM_addr = 48;
  727.                 end
  728.                 D49:begin
  729.                     set_pos_x = 8;
  730.                     set_pos_y = 3;
  731.                     write_data  = ROM_data;
  732.                     ROM_addr = 49;
  733.                 end
  734.                 D50:begin
  735.                     set_pos_x = 16;
  736.                     set_pos_y = 3;
  737.                     write_data  = ROM_data;
  738.                     ROM_addr = 50;
  739.                 end
  740.                 D51:begin
  741.                     set_pos_x = 24;
  742.                     set_pos_y = 3;
  743.                     write_data  = ROM_data;
  744.                     ROM_addr = 51;
  745.                 end
  746.                 D52:begin
  747.                     set_pos_x = 32;
  748.                     set_pos_y = 3;
  749.                     write_data  = ROM_data;
  750.                     ROM_addr = 52;
  751.                 end
  752.                 D53:begin
  753.                     set_pos_x = 40;
  754.                     set_pos_y = 3;
  755.                     write_data  = ROM_data;
  756.                     ROM_addr = 53;
  757.                 end
  758.                 D54:begin
  759.                     set_pos_x = 48;
  760.                     set_pos_y = 3;
  761.                     write_data  = ROM_data;
  762.                     ROM_addr = 54;
  763.                 end
  764.                 D55:begin
  765.                     set_pos_x = 56;
  766.                     set_pos_y = 3;
  767.                     write_data  = ROM_data;
  768.                     ROM_addr = 55;
  769.                 end
  770.                 D56:begin
  771.                     set_pos_x = 64;
  772.                     set_pos_y = 3;
  773.                     write_data  = ROM_data;
  774.                     ROM_addr = 56;
  775.                 end
  776.                 D57:begin
  777.                     set_pos_x = 72;
  778.                     set_pos_y = 3;
  779.                     write_data  = ROM_data;
  780.                     ROM_addr = 57;
  781.                 end
  782.                 D58:begin
  783.                     set_pos_x = 80;
  784.                     set_pos_y = 3;
  785.                     write_data  = ROM_data;
  786.                     ROM_addr = 58;
  787.                 end
  788.                 D59:begin
  789.                     set_pos_x = 88;
  790.                     set_pos_y = 3;
  791.                     write_data  = ROM_data;
  792.                     ROM_addr = 59;
  793.                 end
  794.                 D60:begin
  795.                     set_pos_x = 96;
  796.                     set_pos_y = 3;
  797.                     write_data  = ROM_data;
  798.                     ROM_addr = 60;
  799.                 end
  800.                 D61:begin
  801.                     set_pos_x = 104;
  802.                     set_pos_y = 3;
  803.                     write_data  = ROM_data;
  804.                     ROM_addr = 61;
  805.                 end
  806.                 D62:begin
  807.                     set_pos_x = 112;
  808.                     set_pos_y = 3;
  809.                     write_data  = ROM_data;
  810.                     ROM_addr = 62;
  811.                 end
  812.                 D63:begin
  813.                     set_pos_x = 120;
  814.                     set_pos_y = 3;
  815.                     write_data  = ROM_data;
  816.                     ROM_addr = 63;
  817.                 end
  818. //PAGE4
  819.                 D64:begin
  820.                     set_pos_x = 0;
  821.                     set_pos_y = 4;
  822.                     write_data  = ROM_data;
  823.                     ROM_addr = 64;
  824.                 end
  825.                 D65:begin
  826.                     set_pos_x = 8;
  827.                     set_pos_y = 4;
  828.                     write_data  = ROM_data;
  829.                     ROM_addr = 65;
  830.                 end
  831.                 D66:begin
  832.                     set_pos_x = 16;
  833.                     set_pos_y = 4;
  834.                     write_data  = ROM_data;
  835.                     ROM_addr = 66;
  836.                 end
  837.                 D67:begin
  838.                     set_pos_x = 24;
  839.                     set_pos_y = 4;
  840.                     write_data  = ROM_data;
  841.                     ROM_addr = 67;
  842.                 end                
  843.                 D68:begin
  844.                     set_pos_x = 32;
  845.                     set_pos_y = 4;
  846.                     write_data  = ROM_data;
  847.                     ROM_addr = 68;
  848.                 end
  849.                 D69:begin
  850.                     set_pos_x = 40;
  851.                     set_pos_y = 4;
  852.                     write_data  = ROM_data;
  853.                     ROM_addr = 69;
  854.                 end
  855.                 D70:begin
  856.                     set_pos_x = 48;
  857.                     set_pos_y = 4;
  858.                     write_data  = ROM_data;
  859.                     ROM_addr = 70;
  860.                 end
  861.                 D71:begin
  862.                     set_pos_x = 56;
  863.                     set_pos_y = 4;
  864.                     write_data  = ROM_data;
  865.                     ROM_addr = 71;
  866.                 end
  867.                 D72:begin
  868.                     set_pos_x = 64;
  869.                     set_pos_y = 4;
  870.                     write_data  = ROM_data;
  871.                     ROM_addr = 72;
  872.                 end
  873.                 D73:begin
  874.                     set_pos_x = 72;
  875.                     set_pos_y = 4;
  876.                     write_data  = ROM_data;
  877.                     ROM_addr = 73;
  878.                 end
  879.                 D74:begin
  880.                     set_pos_x = 80;
  881.                     set_pos_y = 4;
  882.                     write_data  = ROM_data;
  883.                     ROM_addr = 74;
  884.                 end
  885.                 D75:begin
  886.                     set_pos_x = 88;
  887.                     set_pos_y = 4;
  888.                     write_data  = ROM_data;
  889.                     ROM_addr = 75;
  890.                 end                
  891.                 D76:begin
  892.                     set_pos_x = 96;
  893.                     set_pos_y = 4;
  894.                     write_data  = ROM_data;
  895.                     ROM_addr = 76;
  896.                 end
  897.                 D77:begin
  898.                     set_pos_x = 104;
  899.                     set_pos_y = 4;
  900.                     write_data  = ROM_data;
  901.                     ROM_addr = 77;
  902.                 end
  903.                 D78:begin
  904.                     set_pos_x = 112;
  905.                     set_pos_y = 4;
  906.                     write_data  = ROM_data;
  907.                     ROM_addr = 78;
  908.                 end
  909.                 D79:begin
  910.                     set_pos_x = 120;
  911.                     set_pos_y = 4;
  912.                     write_data  = ROM_data;
  913.                     ROM_addr = 79;
  914.                 end
  915. //PAGGE5
  916.                 D80:begin
  917.                     set_pos_x = 0;
  918.                     set_pos_y = 5;
  919.                     write_data  = ROM_data;
  920.                     ROM_addr = 80;
  921.                 end
  922.                 D81:begin
  923.                     set_pos_x = 8;
  924.                     set_pos_y = 5;
  925.                     write_data  = ROM_data;
  926.                     ROM_addr = 81;
  927.                 end
  928.                 D82:begin
  929.                     set_pos_x = 16;
  930.                     set_pos_y = 5;
  931.                     write_data  = ROM_data;
  932.                     ROM_addr = 82;
  933.                 end
  934.                 D83:begin
  935.                     set_pos_x = 24;
  936.                     set_pos_y = 5;
  937.                     write_data  = ROM_data;
  938.                     ROM_addr = 83;
  939.                 end
  940.                 D84:begin
  941.                     set_pos_x = 32;
  942.                     set_pos_y = 5;
  943.                     write_data  = ROM_data;
  944.                     ROM_addr = 84;
  945.                 end
  946.                 D85:begin
  947.                     set_pos_x = 40;
  948.                     set_pos_y = 5;
  949.                     write_data  = ROM_data;
  950.                     ROM_addr = 85;
  951.                 end
  952.                 D86:begin
  953.                     set_pos_x = 48;
  954.                     set_pos_y = 5;
  955.                     write_data  = ROM_data;
  956.                     ROM_addr = 86;
  957.                 end
  958.                 D87:begin
  959.                     set_pos_x = 56;
  960.                     set_pos_y = 5;
  961.                     write_data  = ROM_data;
  962.                     ROM_addr = 87;
  963.                 end
  964.                 D88:begin
  965.                     set_pos_x = 64;
  966.                     set_pos_y = 5;
  967.                     write_data  = ROM_data;
  968.                     ROM_addr = 88;
  969.                 end
  970.                 D89:begin
  971.                     set_pos_x = 72;
  972.                     set_pos_y = 5;
  973.                     write_data  = ROM_data;
  974.                     ROM_addr = 89;
  975.                 end
  976.                 D90:begin
  977.                     set_pos_x = 80;
  978.                     set_pos_y = 5;
  979.                     write_data  = ROM_data;
  980.                     ROM_addr = 90;
  981.                 end
  982.                 D91:begin
  983.                     set_pos_x = 88;
  984.                     set_pos_y = 5;
  985.                     write_data  = ROM_data;
  986.                     ROM_addr = 91;
  987.                 end
  988.                 D92:begin
  989.                     set_pos_x = 96;
  990.                     set_pos_y = 5;
  991.                     write_data  = ROM_data;
  992.                     ROM_addr = 92;
  993.                 end
  994.                 D93:begin
  995.                     set_pos_x = 104;
  996.                     set_pos_y = 5;
  997.                     write_data  = ROM_data;
  998.                     ROM_addr = 93;
  999.                 end
  1000.                 D94:begin
  1001.                     set_pos_x = 112;
  1002.                     set_pos_y = 5;
  1003.                     write_data  = ROM_data;
  1004.                     ROM_addr = 94;
  1005.                 end
  1006.                 D95:begin
  1007.                     set_pos_x = 120;
  1008.                     set_pos_y = 5;
  1009.                     write_data  = ROM_data;
  1010.                     ROM_addr = 95;
  1011.                 end
  1012. //PAGE6
  1013.                 D96:begin
  1014.                     set_pos_x = 0;
  1015.                     set_pos_y = 6;
  1016.                     write_data  = ROM_data;
  1017.                     ROM_addr = 96;
  1018.                 end
  1019.                 D97:begin
  1020.                     set_pos_x = 8;
  1021.                     set_pos_y = 6;
  1022.                     write_data  = ROM_data;
  1023.                     ROM_addr = 97;
  1024.                 end
  1025.                 D98:begin
  1026.                     set_pos_x = 16;
  1027.                     set_pos_y = 6;
  1028.                     write_data  = ROM_data;
  1029.                     ROM_addr = 98;
  1030.                 end
  1031.                 D99:begin
  1032.                     set_pos_x = 24;
  1033.                     set_pos_y = 6;
  1034.                     write_data  = ROM_data;
  1035.                     ROM_addr = 99;
  1036.                 end
  1037.                 D100:begin
  1038.                     set_pos_x = 32;
  1039.                     set_pos_y = 6;
  1040.                     write_data  = ROM_data;
  1041.                     ROM_addr = 100;
  1042.                 end
  1043.                 D101:begin
  1044.                     set_pos_x = 40;
  1045.                     set_pos_y = 6;
  1046.                     write_data  = ROM_data;
  1047.                     ROM_addr = 101;
  1048.                 end
  1049.                 D102:begin
  1050.                     set_pos_x = 48;
  1051.                     set_pos_y = 6;
  1052.                     write_data  = ROM_data;
  1053.                     ROM_addr = 102;
  1054.                 end
  1055.                 D103:begin
  1056.                     set_pos_x = 56;
  1057.                     set_pos_y = 6;
  1058.                     write_data  = ROM_data;
  1059.                     ROM_addr = 103;
  1060.                 end
  1061.                 D104:begin
  1062.                     set_pos_x = 64;
  1063.                     set_pos_y = 6;
  1064.                     write_data  = ROM_data;
  1065.                     ROM_addr = 104;
  1066.                 end
  1067.                 D105:begin
  1068.                     set_pos_x = 72;
  1069.                     set_pos_y = 6;
  1070.                     write_data  = ROM_data;
  1071.                     ROM_addr = 105;
  1072.                 end
  1073.                 D106:begin
  1074.                     set_pos_x = 80;
  1075.                     set_pos_y = 6;
  1076.                     write_data  = ROM_data;
  1077.                     ROM_addr = 106;
  1078.                 end
  1079.                 D107:begin
  1080.                     set_pos_x = 88;
  1081.                     set_pos_y = 6;
  1082.                     write_data  = ROM_data;
  1083.                     ROM_addr = 107;
  1084.                 end
  1085.                 D108:begin
  1086.                     set_pos_x = 96;
  1087.                     set_pos_y = 6;
  1088.                     write_data  = ROM_data;
  1089.                     ROM_addr = 108;
  1090.                 end
  1091.                 D109:begin
  1092.                     set_pos_x = 104;
  1093.                     set_pos_y = 6;
  1094.                     write_data  = ROM_data;
  1095.                     ROM_addr = 109;
  1096.                 end
  1097.                 D110:begin
  1098.                     set_pos_x = 112;
  1099.                     set_pos_y = 6;
  1100.                     write_data  = ROM_data;
  1101.                     ROM_addr = 110;
  1102.                 end
  1103.                 D111:begin
  1104.                     set_pos_x = 120;
  1105.                     set_pos_y = 6;
  1106.                     write_data  = ROM_data;
  1107.                     ROM_addr = 111;
  1108.                 end
  1109. //PAGE7
  1110.                 D112:begin
  1111.                     set_pos_x = 0;
  1112.                     set_pos_y = 7;
  1113.                     write_data  = ROM_data;
  1114.                     ROM_addr = 112;
  1115.                 end
  1116.                 D113:begin
  1117.                     set_pos_x = 8;
  1118.                     set_pos_y = 7;
  1119.                     write_data  = ROM_data;
  1120.                     ROM_addr = 113;
  1121.                 end
  1122.                 D114:begin
  1123.                     set_pos_x = 16;
  1124.                     set_pos_y = 7;
  1125.                     write_data  = ROM_data;
  1126.                     ROM_addr = 114;
  1127.                 end
  1128.                 D115:begin
  1129.                     set_pos_x = 24;
  1130.                     set_pos_y = 7;
  1131.                     write_data  = ROM_data;
  1132.                     ROM_addr = 115;
  1133.                 end
  1134.                 D116:begin
  1135.                     set_pos_x = 32;
  1136.                     set_pos_y = 7;
  1137.                     write_data  = ROM_data;
  1138.                     ROM_addr = 116;
  1139.                 end
  1140.                 D117:begin
  1141.                     set_pos_x = 40;
  1142.                     set_pos_y = 7;
  1143.                     write_data  = ROM_data;
  1144.                     ROM_addr = 117;
  1145.                 end
  1146.                 D118:begin
  1147.                     set_pos_x = 48;
  1148.                     set_pos_y = 7;
  1149.                     write_data  = ROM_data;
  1150.                     ROM_addr = 118;
  1151.                 end
  1152.                 D119:begin
  1153.                     set_pos_x = 56;
  1154.                     set_pos_y = 7;
  1155.                     write_data  = ROM_data;
  1156.                     ROM_addr = 119;
  1157.                 end
  1158.                 D120:begin
  1159.                     set_pos_x = 64;
  1160.                     set_pos_y = 7;
  1161.                     write_data  = ROM_data;
  1162.                     ROM_addr = 120;
  1163.                 end
  1164.                 D121:begin
  1165.                     set_pos_x = 72;
  1166.                     set_pos_y = 7;
  1167.                     write_data  = ROM_data;
  1168.                     ROM_addr = 121;
  1169.                 end
  1170.                 D122:begin
  1171.                     set_pos_x = 80;
  1172.                     set_pos_y = 7;
  1173.                     write_data  = ROM_data;
  1174.                     ROM_addr = 122;
  1175.                 end
  1176.                 D123:begin
  1177.                     set_pos_x = 88;
  1178.                     set_pos_y = 7;
  1179.                     write_data  = ROM_data;
  1180.                     ROM_addr = 123;
  1181.                 end
  1182.                 D124:begin
  1183.                     set_pos_x = 96;
  1184.                     set_pos_y = 7;
  1185.                     write_data  = ROM_data;
  1186.                     ROM_addr = 124;
  1187.                 end
  1188.                 D125:begin
  1189.                     set_pos_x = 104;
  1190.                     set_pos_y = 7;
  1191.                     write_data  = ROM_data;
  1192.                     ROM_addr = 125;
  1193.                 end
  1194.                 D126:begin
  1195.                     set_pos_x = 112;
  1196.                     set_pos_y = 7;
  1197.                     write_data  = ROM_data;
  1198.                     ROM_addr = 126;
  1199.                 end
  1200.                 D127:begin
  1201.                     set_pos_x = 120;
  1202.                     set_pos_y = 7;
  1203.                     write_data  = ROM_data;
  1204.                     ROM_addr = 127;
  1205.                 end
  1206.                 default: begin
  1207.                     set_pos_x = 0;
  1208.                     set_pos_y = 0;
  1209.                     write_data= 64'd0;
  1210.                 end
  1211.             endcase
  1212.         end
  1213.     end
  1214.  
  1215.     //初始化写使能、发送的数据控制
  1216.     always @(*) begin
  1217.         if(!rst_n)begin
  1218.             DC_in = 0;
  1219.             SPI_data = 0;
  1220.             SPI_send = 0;
  1221.         end
  1222.         else begin
  1223.             case(cstate)
  1224.                 INIT:begin
  1225.                     DC_in    = DC_init;
  1226.                     SPI_data = SPI_data_init;
  1227.                     SPI_send = SPI_send_init;
  1228.                 end
  1229.                 CLR:begin
  1230.                     DC_in    = DC_clear;
  1231.                     SPI_data = SPI_data_clear;
  1232.                     SPI_send = SPI_send_clear;
  1233.                 end
  1234.                 D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,
  1235.                 D10,D11,D12,D13,D14,D15,D16,D17,D18,D19,
  1236.                 D20,D21,D22,D23,D24,D25,D26,D27,D28,D29,
  1237.                 D30,D31,D32,D33,D34,D35,D36,D37,D38,D39,
  1238.                 D40,D41,D42,D43,D44,D45,D46,D47,D48,D49,
  1239.                 D50,D51,D52,D53,D54,D55,D56,D57,D58,D59,
  1240.                 D60,D61,D62,D63,D64,D65,D66,D67,D68,D69,
  1241.                 D70,D71,D72,D73,D74,D75,D76,D77,D78,D79,
  1242.                 D80,D81,D82,D83,D84,D85,D86,D87,D88,D89,
  1243.                 D90,D91,D92,D93,D94,D95,D96,D97,D98,D99,
  1244.                 D100,D101,D102,D103,D104,D105,D106,D107,D108,D109,
  1245.                 D110,D111,D112,D113,D114,D115,D116,D117,D118,D119,
  1246.                 D120,D121,D122,D123,D124,D125,D126,D127:begin
  1247.                     DC_in    = DC_write;
  1248.                     SPI_data = SPI_data_write;
  1249.                     SPI_send = SPI_send_write;
  1250.                 end
  1251.                 default:begin
  1252.                     DC_in = 0;
  1253.                     SPI_data = 0;
  1254.                     SPI_send = 0;
  1255.                 end
  1256.             endcase
  1257.         end 
  1258.     end
  1259.  
  1260. endmodule

五、仿真结果

初始化

 清屏后发送数据

 testbench：

  1. module top_tb;
  2.  
  3.     // Ports
  4.     reg sys_clk = 0;
  5.     reg sys_rst_n = 0;
  6.     wire sclk;
  7.     wire sck;
  8.     wire res;
  9.     wire MOSI;
  10.     wire CS;
  11.     wire DC;
  12.  
  13.     top top_dut(
  14.         .sys_clk(sys_clk),
  15.         .sys_rst_n(sys_rst_n),
  16.         .sclk(sclk),
  17.         .sck(sck),
  18.         .res(res),
  19.         .MOSI(MOSI),
  20.         .CS(CS),
  21.         .DC(DC)
  22.     );
  23.  
  24.     initial begin
  25.     begin
  26.         #10000;
  27.         sys_rst_n = 1;
  28.         // $finish;
  29.     end
  30.     end
  31.    always #5 sys_clk = ! sys_clk ;
  32.  
  33. endmodule
  34.

六、板级验证

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