VHDL编写3-8译码器_三八译码器vhdl代码

VHDL编写3-8译码器

3-8译码器是由3个输入端和8个输出端组成的译码器，实现3位二进制数转换成10进制的输出（用高低电平来表示输入输出）真值表如下：

本文用两种方法来实现译码器（case和with-select)

因此在设计时，定义3个输入端和两个8个输出端的实体（分别时case语言和with-select语言），分别设计两个结构体HA和HB,在结构体中分别实现case语言和选择信号赋值语句，最后由配置语句选择执行with-select语句。（具体代码如下）

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY homework1 IS
	PORT(A:IN STD_LOGIC_VECTOR(2 DOWNTO 0);               --输入端
		LED8S1,LED8S2:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));  --输出端（LED8S1是HA的输出，LED8S2是HB的输出）
END homework1;

ARCHITECTURE HA OF homework1 IS      --HA实现CASE语句
BEGIN
PROCESS(A)                           --顺序执行
BEGIN
CASE A IS
WHEN "000" =>LED8S1<="11111110";
WHEN "001" =>LED8S1<="11111101";
WHEN "010" =>LED8S1<="11111011";
WHEN "011" =>LED8S1<="11110111";
WHEN "100" =>LED8S1<="11101111";
WHEN "101" =>LED8S1<="11011111";
WHEN "110" =>LED8S1<="10111111";
WHEN "111" =>LED8S1<="01111111";
WHEN OTHERS=>NULL;                    
END CASE;
END PROCESS;
END HA;

ARCHITECTURE HB OF homework1 IS            --HB实现选择赋值语句
SIGNAL tmp :STD_LOGIC_VECTOR(2 DOWNTO 0);  --定义一个信号数组
BEGIN
tmp<=A;                                    --将实体中A的值赋值给tmp
WITH tmp SELECT
LED8S2<="11111110" WHEN "000",
	   "11111101" WHEN "001",
	   "11111011" WHEN "010",
	   "11110111" WHEN "011",
	   "11101111" WHEN "100",
	   "11011111" WHEN "101",
	   "10111111" WHEN "110",
	   "01111111" WHEN "111",
	   "11111111" WHEN OTHERS;
END HB;

CONFIGURATION S OF homework1 IS             --配置
FOR HB
END FOR;
END CONFIGURATION S;



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其中CONFIGURATION是用来选择使用的结构体（本文选用的是结构体HB）
接下来就是仿真了

要注意实体ENTITY中的DOWNTO顺序哦(๑•́ ₃ •̀๑)