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FPGA 以太网传输ov5640视频

作者：weixin_40725706 | 2024-04-29 01:20:40

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FPGA 以太网传输ov5640视频

1 实验任务

使用 DFZU4EV MPSoC 开发板及双目 OV5640 摄像头其中一个摄像头实现图像采集，并通过开发板上的以太网接口发送给上位机实时显示。

2 系统框架

时钟模块用于为 I2C 驱动模块、以太网顶层模块和开始传输控制模块提供驱动时钟；I2C 驱动模块和 I2C 配置模块用于初始化 OV5640 图像传感器；摄像头采集模块负责采集摄像头图像数据，并且把图像数据连接至图像数据封装模块，图像数据封装模块将输入的图像数据进行位拼接，并添加图像的帧头和行场分辨率；以太网顶层模块实现以太网数据的收发；开始传输控制模块控制以太网顶层模块开始/ 停止发送数据。

 

FPGA 顶层模块（ ov5640_udp_pc ）例化了以下 7 个模块：时钟模块（ clk_wiz_0 ）、 I2C 配置模块（i2c_ov5640_rgb565_cfg ）、 I2C 驱动模块（ i2c_dri ）、摄像头数据采集模块（ cmos_capture_data ）、开始传输控制模块（start_transfer_ctrl ）、图像数据封装模块（ img_data_pkt ）和以太网顶层模块模块（ eth_top ）。时钟模块（clk_wiz_0 ）：时钟 IP 核模块通过调用 MMCM IP 核来实现，总共输出 2 个时钟，频率分别为 100Mhz 、 200Mhz 时钟。 100Mhz 时钟 I2C 驱动模块的驱动时钟； 200Mhz 时钟作为 IDELAYCTRL 源语的参考时钟。I2C 驱动模块（ i2c_dri ）： I2C 驱动模块负责驱动 OV5640 SCCB 接口总线，用户可根据该模块提供的
用户接口可以很方便的对 OV5640 的寄存器进行配置，该模块和“ I2C 读写实验”章节中用到的 I2C 驱动模块为同一个模块 。
I2C 配置模块（ i2c_ov5640_rgb565_cfg ）： I2C 配置模块的驱动时钟是由 I2C 驱动模块输出的时钟提供的，这样方便了 I2C 驱动模块和 I2C 配置模块之间的数据交互。该模块寄存需要配置的寄存器地址、数据以及控制初始化的开始与结束，同时该模块输出 OV5640 的寄存器地址和数据以及控制 I2C 驱动模块开始执行的控制信号，直接连接到 I2C 驱动模块的用户接口，从而完成对 OV5640 传感器的初始化。
摄像头图像采集模块（ cmos_capture_data ）：摄像头采集模块在像素时钟的驱动下将传感器输出的场同步信号、行同步信号以及 8 位数据转换成 DDR 读写控制模块的写使能信号和 16 位写数据信号，完成对OV5640 传感器图像的采集。
开始传输控制模块（ start_transfer_ctrl ）：该模块解析以太网顶层模块接收到的数据，如果收到 1 个字节的 ASCII 码“ 1 ”，则表示以太网开始传输图像数据；如果收到 1 个字节的 ASCII 码“ 0 ”，则表示以太网停止传输图像数据。
图像数据封装模块（ img_data_pkt ）：图像数据封装模块负责将输入 16 位的图像数据，拼接成 32 位数据，以及添加图像数据的帧头和行场分辨率。该模块控制着以太网发送模块发送的字节数，单次发送一行图像数据的字节数，模块内部例化了一个异步 FIFO 模块，用于缓存待发送的图像数据。
以太网顶层模块（ eth_top ）：该模块例化了一个时钟 ip 核，输出一个偏移 90 度的 125Mhz 时钟作为以太网顶层模块发送模块的驱动时钟，以太网顶层模块实现以太网通信的收发功能。

 3 FPGA代码

3.1 顶层模块

  1. `timescale 1ns / 1ps
  2. // Descriptions:OV6540以太网传输视频顶层模块
  3.  
  4.  
  5. module ov5640_udp_pc (
  6.     input        sys_clk_p,   //系统时钟  
  7.     input        sys_clk_n,   //系统时钟
  8.     input        sys_rst_n,   //系统复位信号，低电平有效 
  9.     //以太网接口
  10.     input        eth_rxc,     //RGMII接收数据时钟
  11.     input        eth_rx_ctl,  //RGMII输入数据有效信号
  12.     input  [3:0] eth_rxd,     //RGMII输入数据
  13.     output       eth_txc,     //RGMII发送数据时钟    
  14.     output       eth_tx_ctl,  //RGMII输出数据有效信号
  15.     output [3:0] eth_txd,     //RGMII输出数据           
  16.  
  17.     //摄像头接口                       
  18.     input        cam_pclk,   //cmos 数据像素时钟
  19.     input        cam_vsync,  //cmos 场同步信号
  20.     input        cam_href,   //cmos 行同步信号
  21.     input  [7:0] cam_data,   //cmos 数据
  22.     output       cam_rst_n,  //cmos 复位信号，低电平有效
  23.     output       cam_pwdn,   //电源休眠模式选择 0：正常模式 1：电源休眠模式
  24.     output       cam_scl,    //cmos SCCB_SCL线
  25.     inout        cam_sda     //cmos SCCB_SDA线      
  26. );
  27.  
  28.   //parameter define
  29.   //开发板MAC地址 00-11-22-33-44-55
  30.   parameter BOARD_MAC = 48'h00_11_22_33_44_55;
  31.   //开发板IP地址 192.168.1.10
  32.   parameter BOARD_IP = {8'd192, 8'd168, 8'd1, 8'd10};
  33.   //目的MAC地址 ff_ff_ff_ff_ff_ff
  34.   parameter DES_MAC = 48'hd2_ab_d5_e9_c6_86;
  35.   //目的IP地址 192.168.1.102     
  36.   parameter DES_IP = {8'd192, 8'd168, 8'd1, 8'd102};
  37.  
  38.   parameter H_CMOS_DISP = 11'd640;  //CMOS分辨率640行
  39.   parameter V_CMOS_DISP = 11'd480;  //CMOS分辨率480列	
  40.   parameter TOTAL_H_PIXEL = H_CMOS_DISP + 12'd1216;  //水平总像素大小
  41.   parameter TOTAL_V_PIXEL = V_CMOS_DISP + 12'd504;  //垂直总像素大小
  42.  
  43.   parameter SLAVE_ADDR = 7'h3c;  //OV5640的器件地址7'h3c
  44.   parameter BIT_CTRL = 1'b1;  //OV5640的字节地址为16位  0:8位 1:16位
  45.   parameter CLK_FREQ = 27'd50_000_000;  //i2c_dri模块的驱动时钟频率 
  46.   parameter I2C_FREQ = 20'd250_000;  //I2C的SCL时钟频率,不超过400KHz
  48.   //wire define
  49.   wire        clk_100m;  //100Mhz时钟
  50.   wire        eth_tx_clk;  //以太网发送时钟
  51.   wire        locked;
  52.   wire        rst_n;
  53.   wire        i2c_dri_clk;  //I2C操作时钟
  54.   wire        i2c_done;  //I2C读写完成信号
  55.   wire [ 7:0] i2c_data_r;  //I2C读到的数据
  56.   wire        i2c_exec;  //I2C触发信号
  57.   wire [23:0] i2c_data;  //I2C写地址+数据
  58.   wire        i2c_rh_wl;  //I2C读写控制信号
  59.   wire        cam_init_done;  //摄像头出初始化完成信号 
  60.   wire        cmos_frame_vsync;  //输出帧有效场同步信号   
  61.   wire        img_data_en;  //摄像头图像有效信号
  62.   wire [15:0] img_data;  //摄像头图像有效数据
  63.   wire        transfer_flag;  //图像开始传输标志,0:开始传输 1:停止传输
  64.   wire        eth_rx_clk;  //以太网接收时钟
  65.   wire        udp_tx_start_en;  //以太网开始发送信号
  66.   wire [15:0] udp_tx_byte_num;  //以太网发送的有效字节数
  67.   wire [31:0] udp_tx_data;  //以太网发送的数据    
  68.   wire        udp_rec_pkt_done;  //以太网单包数据接收完成信号
  69.   wire        udp_rec_en;  //以太网接收使能信号
  70.   wire [31:0] udp_rec_data;  //以太网接收到的数据
  71.   wire [15:0] udp_rec_byte_num;  //以太网接收到的字节个数
  72.   wire        udp_tx_req;  //以太网发送请求数据信号
  73.   wire        udp_tx_done;  //以太网发送完成信号
  75.   //*****************************************************
  76.   //**                    main code
  77.   //*****************************************************
  79.   assign rst_n = sys_rst_n & locked;
  80.   //电源休眠模式选择 0：正常模式 1：电源休眠模式
  81.   assign cam_pwdn = 1'b0;
  82.   assign cam_rst_n = 1'b1;
  84.   //例化时钟IP核   
  85.   clk_wiz_0 u_clk_wiz_0 (
  86.       // Clock out ports
  87.       .clk_out1 (clk_100m),    // output clk_out1
  88.       // Status and control signals
  89.       .reset    (~sys_rst_n),  // input reset
  90.       .locked   (locked),      // output locked
  91.       // Clock in ports
  92.       .clk_in1_p(sys_clk_p),   // input clk_in1_p
  93.       .clk_in1_n(sys_clk_n)    // input clk_in1_n 
  94.   );
  96.   //I2C配置模块    
  97.   i2c_ov5640_rgb565_cfg u_i2c_cfg (
  98.       .clk          (i2c_dri_clk),
  99.       .rst_n        (rst_n),
  100.       .i2c_done     (i2c_done),
  101.       .i2c_data_r   (i2c_data_r),
  102.       .cmos_h_pixel (H_CMOS_DISP),
  103.       .cmos_v_pixel (V_CMOS_DISP),
  104.       .total_h_pixel(TOTAL_H_PIXEL),
  105.       .total_v_pixel(TOTAL_V_PIXEL),
  106.       .i2c_exec     (i2c_exec),
  107.       .i2c_data     (i2c_data),
  108.       .i2c_rh_wl    (i2c_rh_wl),
  109.       .init_done    (cam_init_done)
  110.   );
  112.   //I2C驱动模块
  113.   i2c_dri #(
  114.       .SLAVE_ADDR(SLAVE_ADDR),  //参数传递
  115.       .CLK_FREQ  (CLK_FREQ),
  116.       .I2C_FREQ  (I2C_FREQ)
  117.   ) u_i2c_dri (
  118.       .clk       (clk_100m),
  119.       .rst_n     (rst_n),
  120.       //i2c interface
  121.       .i2c_exec  (i2c_exec),
  122.       .bit_ctrl  (BIT_CTRL),
  123.       .i2c_rh_wl (i2c_rh_wl),
  124.       .i2c_addr  (i2c_data[23:8]),
  125.       .i2c_data_w(i2c_data[7:0]),
  126.       .i2c_data_r(i2c_data_r),
  127.       .i2c_done  (i2c_done),
  128.       .i2c_ack   (),
  129.       .scl       (cam_scl),
  130.       .sda       (cam_sda),
  131.       //user interface
  132.       .dri_clk   (i2c_dri_clk)      //I2C操作时钟
  133.   );
  135.   //摄像头数据采集模块
  136.   cmos_capture_data u_cmos_capture_data (
  138.       .rst_n           (rst_n & cam_init_done),
  139.       .cam_pclk        (cam_pclk),
  140.       .cam_vsync       (cam_vsync),
  141.       .cam_href        (cam_href),
  142.       .cam_data        (cam_data),
  143.       .cmos_frame_vsync(cmos_frame_vsync),
  144.       .cmos_frame_href (),
  145.       .cmos_frame_valid(img_data_en),
  146.       .cmos_frame_data (img_data)
  147.   );
  149.   //开始传输控制模块   
  150.   start_transfer_ctrl u_start_transfer_ctrl (
  151.       .clk             (eth_rx_clk),
  152.       .rst_n           (rst_n),
  153.       .udp_rec_pkt_done(udp_rec_pkt_done),
  154.       .udp_rec_en      (udp_rec_en),
  155.       .udp_rec_data    (udp_rec_data),
  156.       .udp_rec_byte_num(udp_rec_byte_num),
  157.       .transfer_flag   (transfer_flag)      //图像开始传输标志,1:开始传输 0:停止传输
  158.   );
  160.   //图像封装模块     
  161.   img_data_pkt u_img_data_pkt (
  162.       .rst_n          (rst_n),
  163.       .cam_pclk       (cam_pclk),
  164.       .img_vsync      (cmos_frame_vsync),
  165.       .img_data_en    (img_data_en),
  166.       .img_data       (img_data),
  167.       .transfer_flag  (transfer_flag),
  168.       .eth_tx_clk     (eth_tx_clk),
  169.       .udp_tx_req     (udp_tx_req),
  170.       .udp_tx_done    (udp_tx_done),
  171.       .udp_tx_start_en(udp_tx_start_en),
  172.       .udp_tx_data    (udp_tx_data),
  173.       .udp_tx_byte_num(udp_tx_byte_num)
  174.   );
  176.   //以太网顶层模块    
  177.   eth_top #(
  178.       .BOARD_MAC(BOARD_MAC),  //参数例化
  179.       .BOARD_IP (BOARD_IP),
  180.       .DES_MAC  (DES_MAC),
  181.       .DES_IP   (DES_IP)
  182.   ) u_eth_top (
  183.       .sys_rst_n (rst_n),       //系统复位信号，低电平有效            
  184.       //以太网RGMII接口             
  185.       .eth_rxc   (eth_rxc),     //RGMII接收数据时钟
  186.       .eth_rx_ctl(eth_rx_ctl),  //RGMII输入数据有效信号
  187.       .eth_rxd   (eth_rxd),     //RGMII输入数据
  188.       .eth_txc   (eth_txc),     //RGMII发送数据时钟    
  189.       .eth_tx_ctl(eth_tx_ctl),  //RGMII输出数据有效信号
  190.       .eth_txd   (eth_txd),     //RGMII输出数据          
  192.       .gmii_rx_clk    (eth_rx_clk),
  193.       .gmii_tx_clk    (eth_tx_clk),
  194.       .udp_tx_start_en(udp_tx_start_en),
  195.       .tx_data        (udp_tx_data),
  196.       .tx_byte_num    (udp_tx_byte_num),
  197.       .udp_tx_done    (udp_tx_done),
  198.       .tx_req         (udp_tx_req),
  199.       .rec_pkt_done   (udp_rec_pkt_done),
  200.       .rec_en         (udp_rec_en),
  201.       .rec_data       (udp_rec_data),
  202.       .rec_byte_num   (udp_rec_byte_num)
  203.   );
  205. endmodule

 

 

3.2 iic配置模块

  1. `timescale 1ns / 1ps
  2. // Descriptions:        iic配置
  3.  
  4.  
  5. module i2c_ov5640_rgb565_cfg (
  6.     input clk,   //时钟信号
  7.     input rst_n, //复位信号，低电平有效
  8.  
  9.     input      [ 7:0] i2c_data_r,     //I2C读出的数据
  10.     input             i2c_done,       //I2C寄存器配置完成信号
  11.     input      [12:0] cmos_h_pixel,
  12.     input      [12:0] cmos_v_pixel,
  13.     input      [12:0] total_h_pixel,  //水平总像素大小
  14.     input      [12:0] total_v_pixel,  //垂直总像素大小
  15.     output reg        i2c_exec,       //I2C触发执行信号   
  16.     output reg [23:0] i2c_data,       //I2C要配置的地址与数据(高16位地址,低8位数据)
  17.     output reg        i2c_rh_wl,      //I2C读写控制信号
  18.     output reg        init_done       //初始化完成信号
  19. );
  20.  
  21.   //parameter define
  22.   localparam REG_NUM = 8'd250;  //总共需要配置的寄存器个数
  24.   //reg define
  25.   reg [14:0] start_init_cnt;  //等待延时计数器
  26.   reg [ 7:0] init_reg_cnt;  //寄存器配置个数计数器
  28.   //*****************************************************
  29.   //**                    main code
  30.   //*****************************************************
  32.   SCL配置成250KHz，输入的clk时钟频率为1Mhz,周期为1us 20000*1us = 20ms
  33.   //OV5640上电到开始配置SCCB至少等待20ms
  34.   always @(posedge clk or negedge rst_n) begin
  35.     if (!rst_n) start_init_cnt <= 1'b0;
  36.     else if (start_init_cnt < 15'd20000) begin
  37.       start_init_cnt <= start_init_cnt + 1'b1;
  38.     end
  39.   end
  40.  
  41.   //寄存器配置个数计数    
  42.   always @(posedge clk or negedge rst_n) begin
  43.     if (!rst_n) init_reg_cnt <= 8'd0;
  44.     else if (i2c_exec) init_reg_cnt <= init_reg_cnt + 8'b1;
  45.   end
  46.  
  47.   //i2c触发执行信号   
  48.   always @(posedge clk or negedge rst_n) begin
  49.     if (!rst_n) i2c_exec <= 1'b0;
  50.     else if (start_init_cnt == 15'd20000 - 1'b1) i2c_exec <= 1'b1;
  51.     else if (i2c_done && (init_reg_cnt < REG_NUM)) i2c_exec <= 1'b1;
  52.     else i2c_exec <= 1'b0;
  53.   end
  54.  
  55.   //配置I2C读写控制信号
  56.   always @(posedge clk or negedge rst_n) begin
  57.     if (!rst_n) i2c_rh_wl <= 1'b1;
  58.     else if (init_reg_cnt == 8'd2) i2c_rh_wl <= 1'b0;
  59.   end
  61.   //初始化完成信号
  62.   always @(posedge clk or negedge rst_n) begin
  63.     if (!rst_n) init_done <= 1'b0;
  64.     else if ((init_reg_cnt == REG_NUM) && i2c_done) init_done <= 1'b1;
  65.   end
  67.   //配置寄存器地址与数据
  68.   always @(posedge clk or negedge rst_n) begin
  69.     if (!rst_n) i2c_data <= 24'b0;
  70.     else begin
  71.       case (init_reg_cnt)
  72.         //先读OV5640 ID
  73.         8'd0: i2c_data <= {16'h300a, 8'h0};  //
  74.         8'd1: i2c_data <= {16'h300b, 8'h0};  //
  75.         8'd2: i2c_data <= {16'h3008, 8'h82};  //Bit[7]:复位 Bit[6]:电源休眠
  76.         8'd3: i2c_data <= {16'h3008, 8'h02};  //正常工作模式
  77.         8'd4: i2c_data <= {16'h3103, 8'h02};  //Bit[1]:1 PLL Clock
  78.         //引脚输入/输出控制 FREX/VSYNC/HREF/PCLK/D[9:6]
  79.         8'd5: i2c_data <= {8'h30, 8'h17, 8'hff};
  80.         //引脚输入/输出控制 D[5:0]/GPIO1/GPIO0 
  81.         8'd6: i2c_data <= {16'h3018, 8'hff};
  82.         8'd7: i2c_data <= {16'h3037, 8'h13};  //PLL分频控制
  83.         8'd8: i2c_data <= {16'h3108, 8'h01};  //系统根分频器
  84.         8'd9: i2c_data <= {16'h3630, 8'h36};
  85.         8'd10: i2c_data <= {16'h3631, 8'h0e};
  86.         8'd11: i2c_data <= {16'h3632, 8'he2};
  87.         8'd12: i2c_data <= {16'h3633, 8'h12};
  88.         8'd13: i2c_data <= {16'h3621, 8'he0};
  89.         8'd14: i2c_data <= {16'h3704, 8'ha0};
  90.         8'd15: i2c_data <= {16'h3703, 8'h5a};
  91.         8'd16: i2c_data <= {16'h3715, 8'h78};
  92.         8'd17: i2c_data <= {16'h3717, 8'h01};
  93.         8'd18: i2c_data <= {16'h370b, 8'h60};
  94.         8'd19: i2c_data <= {16'h3705, 8'h1a};
  95.         8'd20: i2c_data <= {16'h3905, 8'h02};
  96.         8'd21: i2c_data <= {16'h3906, 8'h10};
  97.         8'd22: i2c_data <= {16'h3901, 8'h0a};
  98.         8'd23: i2c_data <= {16'h3731, 8'h12};
  99.         8'd24: i2c_data <= {16'h3600, 8'h08};  //VCM控制,用于自动聚焦
  100.         8'd25: i2c_data <= {16'h3601, 8'h33};  //VCM控制,用于自动聚焦
  101.         8'd26: i2c_data <= {16'h302d, 8'h60};  //系统控制
  102.         8'd27: i2c_data <= {16'h3620, 8'h52};
  103.         8'd28: i2c_data <= {16'h371b, 8'h20};
  104.         8'd29: i2c_data <= {16'h471c, 8'h50};
  105.         8'd30: i2c_data <= {16'h3a13, 8'h43};  //AEC(自动曝光控制)
  106.         8'd31: i2c_data <= {16'h3a18, 8'h00};  //AEC 增益上限
  107.         8'd32: i2c_data <= {16'h3a19, 8'hf8};  //AEC 增益上限
  108.         8'd33: i2c_data <= {16'h3635, 8'h13};
  109.         8'd34: i2c_data <= {16'h3636, 8'h03};
  110.         8'd35: i2c_data <= {16'h3634, 8'h40};
  111.         8'd36: i2c_data <= {16'h3622, 8'h01};
  112.         8'd37: i2c_data <= {16'h3c01, 8'h34};
  113.         8'd38: i2c_data <= {16'h3c04, 8'h28};
  114.         8'd39: i2c_data <= {16'h3c05, 8'h98};
  115.         8'd40: i2c_data <= {16'h3c06, 8'h00};  //light meter 1 阈值[15:8]
  116.         8'd41: i2c_data <= {16'h3c07, 8'h08};  //light meter 1 阈值[7:0]
  117.         8'd42: i2c_data <= {16'h3c08, 8'h00};  //light meter 2 阈值[15:8]
  118.         8'd43: i2c_data <= {16'h3c09, 8'h1c};  //light meter 2 阈值[7:0]
  119.         8'd44: i2c_data <= {16'h3c0a, 8'h9c};  //sample number[15:8]
  120.         8'd45: i2c_data <= {16'h3c0b, 8'h40};  //sample number[7:0]
  121.         8'd46: i2c_data <= {16'h3810, 8'h00};  //Timing Hoffset[11:8]
  122.         8'd47: i2c_data <= {16'h3811, 8'h10};  //Timing Hoffset[7:0]
  123.         8'd48: i2c_data <= {16'h3812, 8'h00};  //Timing Voffset[10:8]
  124.         8'd49: i2c_data <= {16'h3708, 8'h64};
  125.         8'd50: i2c_data <= {16'h4001, 8'h02};  //BLC(黑电平校准)补偿起始行号
  126.         8'd51: i2c_data <= {16'h4005, 8'h1a};  //BLC(黑电平校准)补偿始终更新
  127.         8'd52: i2c_data <= {16'h3000, 8'h00};  //系统块复位控制
  128.         8'd53: i2c_data <= {16'h3004, 8'hff};  //时钟使能控制
  129.         8'd54: i2c_data <= {16'h4300, 8'h61};  //格式控制 RGB565
  130.         8'd55: i2c_data <= {16'h501f, 8'h01};  //ISP RGB
  131.         8'd56: i2c_data <= {16'h440e, 8'h00};
  132.         8'd57: i2c_data <= {16'h5000, 8'ha7};  //ISP控制
  133.         8'd58: i2c_data <= {16'h3a0f, 8'h30};  //AEC控制;stable range in high
  134.         8'd59: i2c_data <= {16'h3a10, 8'h28};  //AEC控制;stable range in low
  135.         8'd60: i2c_data <= {16'h3a1b, 8'h30};  //AEC控制;stable range out high
  136.         8'd61: i2c_data <= {16'h3a1e, 8'h26};  //AEC控制;stable range out low
  137.         8'd62: i2c_data <= {16'h3a11, 8'h60};  //AEC控制; fast zone high
  138.         8'd63: i2c_data <= {16'h3a1f, 8'h14};  //AEC控制; fast zone low
  139.         //LENC(镜头校正)控制 16'h5800~16'h583d
  140.         8'd64: i2c_data <= {16'h5800, 8'h23};
  141.         8'd65: i2c_data <= {16'h5801, 8'h14};
  142.         8'd66: i2c_data <= {16'h5802, 8'h0f};
  143.         8'd67: i2c_data <= {16'h5803, 8'h0f};
  144.         8'd68: i2c_data <= {16'h5804, 8'h12};
  145.         8'd69: i2c_data <= {16'h5805, 8'h26};
  146.         8'd70: i2c_data <= {16'h5806, 8'h0c};
  147.         8'd71: i2c_data <= {16'h5807, 8'h08};
  148.         8'd72: i2c_data <= {16'h5808, 8'h05};
  149.         8'd73: i2c_data <= {16'h5809, 8'h05};
  150.         8'd74: i2c_data <= {16'h580a, 8'h08};
  151.         8'd75: i2c_data <= {16'h580b, 8'h0d};
  152.         8'd76: i2c_data <= {16'h580c, 8'h08};
  153.         8'd77: i2c_data <= {16'h580d, 8'h03};
  154.         8'd78: i2c_data <= {16'h580e, 8'h00};
  155.         8'd79: i2c_data <= {16'h580f, 8'h00};
  156.         8'd80: i2c_data <= {16'h5810, 8'h03};
  157.         8'd81: i2c_data <= {16'h5811, 8'h09};
  158.         8'd82: i2c_data <= {16'h5812, 8'h07};
  159.         8'd83: i2c_data <= {16'h5813, 8'h03};
  160.         8'd84: i2c_data <= {16'h5814, 8'h00};
  161.         8'd85: i2c_data <= {16'h5815, 8'h01};
  162.         8'd86: i2c_data <= {16'h5816, 8'h03};
  163.         8'd87: i2c_data <= {16'h5817, 8'h08};
  164.         8'd88: i2c_data <= {16'h5818, 8'h0d};
  165.         8'd89: i2c_data <= {16'h5819, 8'h08};
  166.         8'd90: i2c_data <= {16'h581a, 8'h05};
  167.         8'd91: i2c_data <= {16'h581b, 8'h06};
  168.         8'd92: i2c_data <= {16'h581c, 8'h08};
  169.         8'd93: i2c_data <= {16'h581d, 8'h0e};
  170.         8'd94: i2c_data <= {16'h581e, 8'h29};
  171.         8'd95: i2c_data <= {16'h581f, 8'h17};
  172.         8'd96: i2c_data <= {16'h5820, 8'h11};
  173.         8'd97: i2c_data <= {16'h5821, 8'h11};
  174.         8'd98: i2c_data <= {16'h5822, 8'h15};
  175.         8'd99: i2c_data <= {16'h5823, 8'h28};
  176.         8'd100: i2c_data <= {16'h5824, 8'h46};
  177.         8'd101: i2c_data <= {16'h5825, 8'h26};
  178.         8'd102: i2c_data <= {16'h5826, 8'h08};
  179.         8'd103: i2c_data <= {16'h5827, 8'h26};
  180.         8'd104: i2c_data <= {16'h5828, 8'h64};
  181.         8'd105: i2c_data <= {16'h5829, 8'h26};
  182.         8'd106: i2c_data <= {16'h582a, 8'h24};
  183.         8'd107: i2c_data <= {16'h582b, 8'h22};
  184.         8'd108: i2c_data <= {16'h582c, 8'h24};
  185.         8'd109: i2c_data <= {16'h582d, 8'h24};
  186.         8'd110: i2c_data <= {16'h582e, 8'h06};
  187.         8'd111: i2c_data <= {16'h582f, 8'h22};
  188.         8'd112: i2c_data <= {16'h5830, 8'h40};
  189.         8'd113: i2c_data <= {16'h5831, 8'h42};
  190.         8'd114: i2c_data <= {16'h5832, 8'h24};
  191.         8'd115: i2c_data <= {16'h5833, 8'h26};
  192.         8'd116: i2c_data <= {16'h5834, 8'h24};
  193.         8'd117: i2c_data <= {16'h5835, 8'h22};
  194.         8'd118: i2c_data <= {16'h5836, 8'h22};
  195.         8'd119: i2c_data <= {16'h5837, 8'h26};
  196.         8'd120: i2c_data <= {16'h5838, 8'h44};
  197.         8'd121: i2c_data <= {16'h5839, 8'h24};
  198.         8'd122: i2c_data <= {16'h583a, 8'h26};
  199.         8'd123: i2c_data <= {16'h583b, 8'h28};
  200.         8'd124: i2c_data <= {16'h583c, 8'h42};
  201.         8'd125: i2c_data <= {16'h583d, 8'hce};
  202.         //AWB(自动白平衡控制) 16'h5180~16'h519e
  203.         8'd126: i2c_data <= {16'h5180, 8'hff};
  204.         8'd127: i2c_data <= {16'h5181, 8'hf2};
  205.         8'd128: i2c_data <= {16'h5182, 8'h00};
  206.         8'd129: i2c_data <= {16'h5183, 8'h14};
  207.         8'd130: i2c_data <= {16'h5184, 8'h25};
  208.         8'd131: i2c_data <= {16'h5185, 8'h24};
  209.         8'd132: i2c_data <= {16'h5186, 8'h09};
  210.         8'd133: i2c_data <= {16'h5187, 8'h09};
  211.         8'd134: i2c_data <= {16'h5188, 8'h09};
  212.         8'd135: i2c_data <= {16'h5189, 8'h75};
  213.         8'd136: i2c_data <= {16'h518a, 8'h54};
  214.         8'd137: i2c_data <= {16'h518b, 8'he0};
  215.         8'd138: i2c_data <= {16'h518c, 8'hb2};
  216.         8'd139: i2c_data <= {16'h518d, 8'h42};
  217.         8'd140: i2c_data <= {16'h518e, 8'h3d};
  218.         8'd141: i2c_data <= {16'h518f, 8'h56};
  219.         8'd142: i2c_data <= {16'h5190, 8'h46};
  220.         8'd143: i2c_data <= {16'h5191, 8'hf8};
  221.         8'd144: i2c_data <= {16'h5192, 8'h04};
  222.         8'd145: i2c_data <= {16'h5193, 8'h70};
  223.         8'd146: i2c_data <= {16'h5194, 8'hf0};
  224.         8'd147: i2c_data <= {16'h5195, 8'hf0};
  225.         8'd148: i2c_data <= {16'h5196, 8'h03};
  226.         8'd149: i2c_data <= {16'h5197, 8'h01};
  227.         8'd150: i2c_data <= {16'h5198, 8'h04};
  228.         8'd151: i2c_data <= {16'h5199, 8'h12};
  229.         8'd152: i2c_data <= {16'h519a, 8'h04};
  230.         8'd153: i2c_data <= {16'h519b, 8'h00};
  231.         8'd154: i2c_data <= {16'h519c, 8'h06};
  232.         8'd155: i2c_data <= {16'h519d, 8'h82};
  233.         8'd156: i2c_data <= {16'h519e, 8'h38};
  234.         //Gamma(伽马)控制 16'h5480~16'h5490
  235.         8'd157: i2c_data <= {16'h5480, 8'h01};
  236.         8'd158: i2c_data <= {16'h5481, 8'h08};
  237.         8'd159: i2c_data <= {16'h5482, 8'h14};
  238.         8'd160: i2c_data <= {16'h5483, 8'h28};
  239.         8'd161: i2c_data <= {16'h5484, 8'h51};
  240.         8'd162: i2c_data <= {16'h5485, 8'h65};
  241.         8'd163: i2c_data <= {16'h5486, 8'h71};
  242.         8'd164: i2c_data <= {16'h5487, 8'h7d};
  243.         8'd165: i2c_data <= {16'h5488, 8'h87};
  244.         8'd166: i2c_data <= {16'h5489, 8'h91};
  245.         8'd167: i2c_data <= {16'h548a, 8'h9a};
  246.         8'd168: i2c_data <= {16'h548b, 8'haa};
  247.         8'd169: i2c_data <= {16'h548c, 8'hb8};
  248.         8'd170: i2c_data <= {16'h548d, 8'hcd};
  249.         8'd171: i2c_data <= {16'h548e, 8'hdd};
  250.         8'd172: i2c_data <= {16'h548f, 8'hea};
  251.         8'd173: i2c_data <= {16'h5490, 8'h1d};
  252.         //CMX(彩色矩阵控制) 16'h5381~16'h538b
  253.         8'd174: i2c_data <= {16'h5381, 8'h1e};
  254.         8'd175: i2c_data <= {16'h5382, 8'h5b};
  255.         8'd176: i2c_data <= {16'h5383, 8'h08};
  256.         8'd177: i2c_data <= {16'h5384, 8'h0a};
  257.         8'd178: i2c_data <= {16'h5385, 8'h7e};
  258.         8'd179: i2c_data <= {16'h5386, 8'h88};
  259.         8'd180: i2c_data <= {16'h5387, 8'h7c};
  260.         8'd181: i2c_data <= {16'h5388, 8'h6c};
  261.         8'd182: i2c_data <= {16'h5389, 8'h10};
  262.         8'd183: i2c_data <= {16'h538a, 8'h01};
  263.         8'd184: i2c_data <= {16'h538b, 8'h98};
  264.         //SDE(特殊数码效果)控制 16'h5580~16'h558b
  265.         8'd185: i2c_data <= {16'h5580, 8'h06};
  266.         8'd186: i2c_data <= {16'h5583, 8'h40};
  267.         8'd187: i2c_data <= {16'h5584, 8'h10};
  268.         8'd188: i2c_data <= {16'h5589, 8'h10};
  269.         8'd189: i2c_data <= {16'h558a, 8'h00};
  270.         8'd190: i2c_data <= {16'h558b, 8'hf8};
  271.         8'd191: i2c_data <= {16'h501d, 8'h40};  //ISP MISC
  272.         //CIP(颜色插值)控制 (16'h5300~16'h530c)
  273.         8'd192: i2c_data <= {16'h5300, 8'h08};
  274.         8'd193: i2c_data <= {16'h5301, 8'h30};
  275.         8'd194: i2c_data <= {16'h5302, 8'h10};
  276.         8'd195: i2c_data <= {16'h5303, 8'h00};
  277.         8'd196: i2c_data <= {16'h5304, 8'h08};
  278.         8'd197: i2c_data <= {16'h5305, 8'h30};
  279.         8'd198: i2c_data <= {16'h5306, 8'h08};
  280.         8'd199: i2c_data <= {16'h5307, 8'h16};
  281.         8'd200: i2c_data <= {16'h5309, 8'h08};
  282.         8'd201: i2c_data <= {16'h530a, 8'h30};
  283.         8'd202: i2c_data <= {16'h530b, 8'h04};
  284.         8'd203: i2c_data <= {16'h530c, 8'h06};
  285.         8'd204: i2c_data <= {16'h5025, 8'h00};
  286.         //系统时钟分频 Bit[7:4]:系统时钟分频 input clock =24Mhz, PCLK = 48Mhz
  287.         8'd205: i2c_data <= {16'h3035, 8'h11};
  288.         8'd206: i2c_data <= {16'h3036, 8'h3c};  //PLL倍频
  289.         8'd207: i2c_data <= {16'h3c07, 8'h08};
  290.         //时序控制 16'h3800~16'h3821
  291.         8'd208: i2c_data <= {16'h3820, 8'h46};
  292.         8'd209: i2c_data <= {16'h3821, 8'h01};
  293.         8'd210: i2c_data <= {16'h3814, 8'h31};
  294.         8'd211: i2c_data <= {16'h3815, 8'h31};
  295.         8'd212: i2c_data <= {16'h3800, 8'h00};
  296.         8'd213: i2c_data <= {16'h3801, 8'h00};
  297.         8'd214: i2c_data <= {16'h3802, 8'h00};
  298.         8'd215: i2c_data <= {16'h3803, 8'h04};
  299.         8'd216: i2c_data <= {16'h3804, 8'h0a};
  300.         8'd217: i2c_data <= {16'h3805, 8'h3f};
  301.         8'd218: i2c_data <= {16'h3806, 8'h07};
  302.         8'd219: i2c_data <= {16'h3807, 8'h9b};
  303.         //设置输出像素个数
  304.         //DVP 输出水平像素点数高4位
  305.         8'd220: i2c_data <= {16'h3808, {4'd0, cmos_h_pixel[11:8]}};
  306.         //DVP 输出水平像素点数低8位
  307.         8'd221: i2c_data <= {16'h3809, cmos_h_pixel[7:0]};
  308.         //DVP 输出垂直像素点数高3位
  309.         8'd222: i2c_data <= {16'h380a, {5'd0, cmos_v_pixel[10:8]}};
  310.         //DVP 输出垂直像素点数低8位
  311.         8'd223: i2c_data <= {16'h380b, cmos_v_pixel[7:0]};
  312.         //水平总像素大小高5位
  313.         8'd224: i2c_data <= {16'h380c, {3'd0, total_h_pixel[12:8]}};
  314.         //水平总像素大小低8位 
  315.         8'd225: i2c_data <= {16'h380d, total_h_pixel[7:0]};
  316.         //垂直总像素大小高5位 
  317.         8'd226: i2c_data <= {16'h380e, {3'd0, total_v_pixel[12:8]}};
  318.         //垂直总像素大小低8位     
  319.         8'd227: i2c_data <= {16'h380f, total_v_pixel[7:0]};
  320.         8'd228: i2c_data <= {16'h3813, 8'h06};
  321.         8'd229: i2c_data <= {16'h3618, 8'h00};
  322.         8'd230: i2c_data <= {16'h3612, 8'h29};
  323.         8'd231: i2c_data <= {16'h3709, 8'h52};
  324.         8'd232: i2c_data <= {16'h370c, 8'h03};
  325.         8'd233: i2c_data <= {16'h3a02, 8'h17};  //60Hz max exposure
  326.         8'd234: i2c_data <= {16'h3a03, 8'h10};  //60Hz max exposure
  327.         8'd235: i2c_data <= {16'h3a14, 8'h17};  //50Hz max exposure
  328.         8'd236: i2c_data <= {16'h3a15, 8'h10};  //50Hz max exposure
  329.         8'd237: i2c_data <= {16'h4004, 8'h02};  //BLC(背光) 2 lines
  330.         8'd238: i2c_data <= {16'h4713, 8'h03};  //JPEG mode 3
  331.         8'd239: i2c_data <= {16'h4407, 8'h04};  //量化标度
  332.         8'd240: i2c_data <= {16'h460c, 8'h22};
  333.         8'd241: i2c_data <= {16'h4837, 8'h22};  //DVP CLK divider
  334.         8'd242: i2c_data <= {16'h3824, 8'h02};  //DVP CLK divider
  335.         8'd243: i2c_data <= {16'h5001, 8'ha3};  //ISP 控制
  336.         8'd244: i2c_data <= {16'h3b07, 8'h0a};  //帧曝光模式  
  337.         //彩条测试使能 
  338.         8'd245: i2c_data <= {16'h503d, 8'h00};  //8'h00:正常模式 8'h80:彩条显示
  339.         //测试闪光灯功能
  340.         8'd246: i2c_data <= {16'h3016, 8'h02};
  341.         8'd247: i2c_data <= {16'h301c, 8'h02};
  342.         8'd248: i2c_data <= {16'h3019, 8'h02};  //打开闪光灯
  343.         8'd249: i2c_data <= {16'h3019, 8'h00};  //关闭闪光灯
  344.         //只读存储器,防止在case中没有列举的情况，之前的寄存器被重复改写
  345.         default: i2c_data <= {16'h300a, 8'h00};  //器件ID高8位
  346.       endcase
  347.     end
  348.   end
  350. endmodule

3.3 iic驱动模块

  1. `timescale 1ns / 1ps
  2. //IIC驱动模块
  3.  
  4.  
  5. module i2c_dri #(
  6.     parameter   SLAVE_ADDR = 7'b1010000   ,  //EEPROM从机地址
  7.     parameter   CLK_FREQ   = 26'd50_000_000, //模块输入的时钟频率
  8.     parameter   I2C_FREQ   = 18'd250_000     //IIC_SCL的时钟频率
  9. ) (
  10.     input clk,
  11.     input rst_n,
  13.     //i2c interface                      
  14.     input             i2c_exec,    //I2C触发执行信号
  15.     input             bit_ctrl,    //字地址位控制(16b/8b)
  16.     input             i2c_rh_wl,   //I2C读写控制信号
  17.     input      [15:0] i2c_addr,    //I2C器件内地址
  18.     input      [ 7:0] i2c_data_w,  //I2C要写的数据
  19.     output reg [ 7:0] i2c_data_r,  //I2C读出的数据
  20.     output reg        i2c_done,    //I2C一次操作完成
  21.     output reg        i2c_ack,     //I2C应答标志 0:应答 1:未应答
  22.     output reg        scl,         //I2C的SCL时钟信号
  23.     inout             sda,         //I2C的SDA信号
  25.     //user interface                   
  26.     output reg dri_clk  //驱动I2C操作的驱动时钟
  27. );
  29.   //localparam define
  30.   localparam st_idle = 8'b0000_0001;  //空闲状态
  31.   localparam st_sladdr = 8'b0000_0010;  //发送器件地址(slave address)
  32.   localparam st_addr16 = 8'b0000_0100;  //发送16位字地址
  33.   localparam st_addr8 = 8'b0000_1000;  //发送8位字地址
  34.   localparam st_data_wr = 8'b0001_0000;  //写数据(8 bit)
  35.   localparam st_addr_rd = 8'b0010_0000;  //发送器件地址读
  36.   localparam st_data_rd = 8'b0100_0000;  //读数据(8 bit)
  37.   localparam st_stop = 8'b1000_0000;  //结束I2C操作
  39.   //reg define
  40.   reg         sda_dir;  //I2C数据(SDA)方向控制
  41.   reg         sda_out;  //SDA输出信号
  42.   reg         st_done;  //状态结束
  43.   reg         wr_flag;  //写标志
  44.   reg  [ 6:0] cnt;  //计数
  45.   reg  [ 7:0] cur_state;  //状态机当前状态
  46.   reg  [ 7:0] next_state;  //状态机下一状态
  47.   reg  [15:0] addr_t;  //地址
  48.   reg  [ 7:0] data_r;  //读取的数据
  49.   reg  [ 7:0] data_wr_t;  //I2C需写的数据的临时寄存
  50.   reg  [ 9:0] clk_cnt;  //分频时钟计数
  52.   //wire define
  53.   wire        sda_in;  //SDA输入信号
  54.   wire [ 8:0] clk_divide;  //模块驱动时钟的分频系数
  56.   //*****************************************************
  57.   //**                    main code
  58.   //*****************************************************
  60.   //SDA控制
  61.   assign sda        = sda_dir ? sda_out : 1'bz;  //SDA数据输出或高阻
  62.   assign sda_in     = sda;  //SDA数据输入
  63.   assign clk_divide = (CLK_FREQ / I2C_FREQ) >> 2'd2;  //模块驱动时钟的分频系数
  65.   //生成I2C的SCL的四倍频率的驱动时钟用于驱动i2c的操作
  66.   always @(posedge clk or negedge rst_n) begin
  67.     if (!rst_n) begin
  68.       dri_clk <= 1'b0;
  69.       clk_cnt <= 10'd0;
  70.     end else if (clk_cnt == clk_divide[8:1] - 1'd1) begin
  71.       clk_cnt <= 10'd0;
  72.       dri_clk <= ~dri_clk;
  73.     end else clk_cnt <= clk_cnt + 1'b1;
  74.   end
  76.   //(三段式状态机)同步时序描述状态转移
  77.   always @(posedge dri_clk or negedge rst_n) begin
  78.     if (!rst_n) cur_state <= st_idle;
  79.     else cur_state <= next_state;
  80.   end
  82.   //组合逻辑判断状态转移条件
  83.   always @(*) begin
  84.     next_state = st_idle;
  85.     case (cur_state)
  86.       st_idle: begin  //空闲状态
  87.         if (i2c_exec) begin
  88.           next_state = st_sladdr;
  89.         end else next_state = st_idle;
  90.       end
  91.       st_sladdr: begin
  92.         if (st_done) begin
  93.           if (bit_ctrl)  //判断是16位还是8位字地址
  94.             next_state = st_addr16;
  95.           else next_state = st_addr8;
  96.         end else next_state = st_sladdr;
  97.       end
  98.       st_addr16: begin  //写16位字地址
  99.         if (st_done) begin
  100.           next_state = st_addr8;
  101.         end else begin
  102.           next_state = st_addr16;
  103.         end
  104.       end
  105.       st_addr8: begin  //8位字地址
  106.         if (st_done) begin
  107.           if (wr_flag == 1'b0)  //读写判断
  108.             next_state = st_data_wr;
  109.           else next_state = st_addr_rd;
  110.         end else begin
  111.           next_state = st_addr8;
  112.         end
  113.       end
  114.       st_data_wr: begin  //写数据(8 bit)
  115.         if (st_done) next_state = st_stop;
  116.         else next_state = st_data_wr;
  117.       end
  118.       st_addr_rd: begin  //写地址以进行读数据
  119.         if (st_done) begin
  120.           next_state = st_data_rd;
  121.         end else begin
  122.           next_state = st_addr_rd;
  123.         end
  124.       end
  125.       st_data_rd: begin  //读取数据(8 bit)
  126.         if (st_done) next_state = st_stop;
  127.         else next_state = st_data_rd;
  128.       end
  129.       st_stop: begin  //结束I2C操作
  130.         if (st_done) next_state = st_idle;
  131.         else next_state = st_stop;
  132.       end
  133.       default: next_state = st_idle;
  134.     endcase
  135.   end
  136.  
  137.   //时序电路描述状态输出
  138.   always @(posedge dri_clk or negedge rst_n) begin
  139.     //复位初始化
  140.     if (!rst_n) begin
  141.       scl        <= 1'b1;
  142.       sda_out    <= 1'b1;
  143.       sda_dir    <= 1'b1;
  144.       i2c_done   <= 1'b0;
  145.       i2c_ack    <= 1'b0;
  146.       cnt        <= 1'b0;
  147.       st_done    <= 1'b0;
  148.       data_r     <= 1'b0;
  149.       i2c_data_r <= 1'b0;
  150.       wr_flag    <= 1'b0;
  151.       addr_t     <= 1'b0;
  152.       data_wr_t  <= 1'b0;
  153.     end else begin
  154.       st_done <= 1'b0;
  155.       cnt     <= cnt + 1'b1;
  156.       case (cur_state)
  157.         st_idle: begin  //空闲状态
  158.           scl      <= 1'b1;
  159.           sda_out  <= 1'b1;
  160.           sda_dir  <= 1'b1;
  161.           i2c_done <= 1'b0;
  162.           cnt      <= 7'b0;
  163.           if (i2c_exec) begin
  164.             wr_flag   <= i2c_rh_wl ;
  165.             addr_t    <= i2c_addr  ;
  166.             data_wr_t <= i2c_data_w;
  167.             i2c_ack <= 1'b0;
  168.           end
  169.         end
  170.         st_sladdr: begin  //写地址(器件地址和字地址)
  171.           case (cnt)
  172.             7'd1:    sda_out <= 1'b0;  //开始I2C
  173.             7'd3:    scl <= 1'b0;
  174.             7'd4:    sda_out <= SLAVE_ADDR[6];  //传送器件地址
  175.             7'd5:    scl <= 1'b1;
  176.             7'd7:    scl <= 1'b0;
  177.             7'd8:    sda_out <= SLAVE_ADDR[5];
  178.             7'd9:    scl <= 1'b1;
  179.             7'd11:   scl <= 1'b0;
  180.             7'd12:   sda_out <= SLAVE_ADDR[4];
  181.             7'd13:   scl <= 1'b1;
  182.             7'd15:   scl <= 1'b0;
  183.             7'd16:   sda_out <= SLAVE_ADDR[3];
  184.             7'd17:   scl <= 1'b1;
  185.             7'd19:   scl <= 1'b0;
  186.             7'd20:   sda_out <= SLAVE_ADDR[2];
  187.             7'd21:   scl <= 1'b1;
  188.             7'd23:   scl <= 1'b0;
  189.             7'd24:   sda_out <= SLAVE_ADDR[1];
  190.             7'd25:   scl <= 1'b1;
  191.             7'd27:   scl <= 1'b0;
  192.             7'd28:   sda_out <= SLAVE_ADDR[0];
  193.             7'd29:   scl <= 1'b1;
  194.             7'd31:   scl <= 1'b0;
  195.             7'd32:   sda_out <= 1'b0;  //0:写
  196.             7'd33:   scl <= 1'b1;
  197.             7'd35:   scl <= 1'b0;
  198.             7'd36: begin
  199.               sda_dir <= 1'b0;
  200.               sda_out <= 1'b1;
  201.             end
  202.             7'd37:   scl <= 1'b1;
  203.             7'd38: begin  //从机应答 
  204.               st_done <= 1'b1;
  205.               if (sda_in == 1'b1)  //高电平表示未应答
  206.                 i2c_ack <= 1'b1;  //拉高应答标志位     
  207.             end
  208.             7'd39: begin
  209.               scl <= 1'b0;
  210.               cnt <= 1'b0;
  211.             end
  212.             default: ;
  213.           endcase
  214.         end
  215.         st_addr16: begin
  216.           case (cnt)
  217.             7'd0: begin
  218.               sda_dir <= 1'b1;
  219.               sda_out <= addr_t[15];  //传送字地址
  220.             end
  221.             7'd1:    scl <= 1'b1;
  222.             7'd3:    scl <= 1'b0;
  223.             7'd4:    sda_out <= addr_t[14];
  224.             7'd5:    scl <= 1'b1;
  225.             7'd7:    scl <= 1'b0;
  226.             7'd8:    sda_out <= addr_t[13];
  227.             7'd9:    scl <= 1'b1;
  228.             7'd11:   scl <= 1'b0;
  229.             7'd12:   sda_out <= addr_t[12];
  230.             7'd13:   scl <= 1'b1;
  231.             7'd15:   scl <= 1'b0;
  232.             7'd16:   sda_out <= addr_t[11];
  233.             7'd17:   scl <= 1'b1;
  234.             7'd19:   scl <= 1'b0;
  235.             7'd20:   sda_out <= addr_t[10];
  236.             7'd21:   scl <= 1'b1;
  237.             7'd23:   scl <= 1'b0;
  238.             7'd24:   sda_out <= addr_t[9];
  239.             7'd25:   scl <= 1'b1;
  240.             7'd27:   scl <= 1'b0;
  241.             7'd28:   sda_out <= addr_t[8];
  242.             7'd29:   scl <= 1'b1;
  243.             7'd31:   scl <= 1'b0;
  244.             7'd32: begin
  245.               sda_dir <= 1'b0;
  246.               sda_out <= 1'b1;
  247.             end
  248.             7'd33:   scl <= 1'b1;
  249.             7'd34: begin  //从机应答
  250.               st_done <= 1'b1;
  251.               if (sda_in == 1'b1)  //高电平表示未应答
  252.                 i2c_ack <= 1'b1;  //拉高应答标志位    
  253.             end
  254.             7'd35: begin
  255.               scl <= 1'b0;
  256.               cnt <= 1'b0;
  257.             end
  258.             default: ;
  259.           endcase
  260.         end
  261.         st_addr8: begin
  262.           case (cnt)
  263.             7'd0: begin
  264.               sda_dir <= 1'b1;
  265.               sda_out <= addr_t[7];  //字地址
  266.             end
  267.             7'd1:    scl <= 1'b1;
  268.             7'd3:    scl <= 1'b0;
  269.             7'd4:    sda_out <= addr_t[6];
  270.             7'd5:    scl <= 1'b1;
  271.             7'd7:    scl <= 1'b0;
  272.             7'd8:    sda_out <= addr_t[5];
  273.             7'd9:    scl <= 1'b1;
  274.             7'd11:   scl <= 1'b0;
  275.             7'd12:   sda_out <= addr_t[4];
  276.             7'd13:   scl <= 1'b1;
  277.             7'd15:   scl <= 1'b0;
  278.             7'd16:   sda_out <= addr_t[3];
  279.             7'd17:   scl <= 1'b1;
  280.             7'd19:   scl <= 1'b0;
  281.             7'd20:   sda_out <= addr_t[2];
  282.             7'd21:   scl <= 1'b1;
  283.             7'd23:   scl <= 1'b0;
  284.             7'd24:   sda_out <= addr_t[1];
  285.             7'd25:   scl <= 1'b1;
  286.             7'd27:   scl <= 1'b0;
  287.             7'd28:   sda_out <= addr_t[0];
  288.             7'd29:   scl <= 1'b1;
  289.             7'd31:   scl <= 1'b0;
  290.             7'd32: begin
  291.               sda_dir <= 1'b0;
  292.               sda_out <= 1'b1;
  293.             end
  294.             7'd33:   scl <= 1'b1;
  295.             7'd34: begin  //从机应答
  296.               st_done <= 1'b1;
  297.               if (sda_in == 1'b1)  //高电平表示未应答
  298.                 i2c_ack <= 1'b1;  //拉高应答标志位    
  299.             end
  300.             7'd35: begin
  301.               scl <= 1'b0;
  302.               cnt <= 1'b0;
  303.             end
  304.             default: ;
  305.           endcase
  306.         end
  307.         st_data_wr: begin  //写数据(8 bit)
  308.           case (cnt)
  309.             7'd0: begin
  310.               sda_out <= data_wr_t[7];  //I2C写8位数据
  311.               sda_dir <= 1'b1;
  312.             end
  313.             7'd1:    scl <= 1'b1;
  314.             7'd3:    scl <= 1'b0;
  315.             7'd4:    sda_out <= data_wr_t[6];
  316.             7'd5:    scl <= 1'b1;
  317.             7'd7:    scl <= 1'b0;
  318.             7'd8:    sda_out <= data_wr_t[5];
  319.             7'd9:    scl <= 1'b1;
  320.             7'd11:   scl <= 1'b0;
  321.             7'd12:   sda_out <= data_wr_t[4];
  322.             7'd13:   scl <= 1'b1;
  323.             7'd15:   scl <= 1'b0;
  324.             7'd16:   sda_out <= data_wr_t[3];
  325.             7'd17:   scl <= 1'b1;
  326.             7'd19:   scl <= 1'b0;
  327.             7'd20:   sda_out <= data_wr_t[2];
  328.             7'd21:   scl <= 1'b1;
  329.             7'd23:   scl <= 1'b0;
  330.             7'd24:   sda_out <= data_wr_t[1];
  331.             7'd25:   scl <= 1'b1;
  332.             7'd27:   scl <= 1'b0;
  333.             7'd28:   sda_out <= data_wr_t[0];
  334.             7'd29:   scl <= 1'b1;
  335.             7'd31:   scl <= 1'b0;
  336.             7'd32: begin
  337.               sda_dir <= 1'b0;
  338.               sda_out <= 1'b1;
  339.             end
  340.             7'd33:   scl <= 1'b1;
  341.             7'd34: begin  //从机应答
  342.               st_done <= 1'b1;
  343.               if (sda_in == 1'b1)  //高电平表示未应答
  344.                 i2c_ack <= 1'b1;  //拉高应答标志位    
  345.             end
  346.             7'd35: begin
  347.               scl <= 1'b0;
  348.               cnt <= 1'b0;
  349.             end
  350.             default: ;
  351.           endcase
  352.         end
  353.         st_addr_rd: begin  //写地址以进行读数据
  354.           case (cnt)
  355.             7'd0: begin
  356.               sda_dir <= 1'b1;
  357.               sda_out <= 1'b1;
  358.             end
  359.             7'd1:    scl <= 1'b1;
  360.             7'd2:    sda_out <= 1'b0;  //重新开始
  361.             7'd3:    scl <= 1'b0;
  362.             7'd4:    sda_out <= SLAVE_ADDR[6];  //传送器件地址
  363.             7'd5:    scl <= 1'b1;
  364.             7'd7:    scl <= 1'b0;
  365.             7'd8:    sda_out <= SLAVE_ADDR[5];
  366.             7'd9:    scl <= 1'b1;
  367.             7'd11:   scl <= 1'b0;
  368.             7'd12:   sda_out <= SLAVE_ADDR[4];
  369.             7'd13:   scl <= 1'b1;
  370.             7'd15:   scl <= 1'b0;
  371.             7'd16:   sda_out <= SLAVE_ADDR[3];
  372.             7'd17:   scl <= 1'b1;
  373.             7'd19:   scl <= 1'b0;
  374.             7'd20:   sda_out <= SLAVE_ADDR[2];
  375.             7'd21:   scl <= 1'b1;
  376.             7'd23:   scl <= 1'b0;
  377.             7'd24:   sda_out <= SLAVE_ADDR[1];
  378.             7'd25:   scl <= 1'b1;
  379.             7'd27:   scl <= 1'b0;
  380.             7'd28:   sda_out <= SLAVE_ADDR[0];
  381.             7'd29:   scl <= 1'b1;
  382.             7'd31:   scl <= 1'b0;
  383.             7'd32:   sda_out <= 1'b1;  //1:读
  384.             7'd33:   scl <= 1'b1;
  385.             7'd35:   scl <= 1'b0;
  386.             7'd36: begin
  387.               sda_dir <= 1'b0;
  388.               sda_out <= 1'b1;
  389.             end
  390.             7'd37:   scl <= 1'b1;
  391.             7'd38: begin  //从机应答
  392.               st_done <= 1'b1;
  393.               if (sda_in == 1'b1)  //高电平表示未应答
  394.                 i2c_ack <= 1'b1;  //拉高应答标志位    
  395.             end
  396.             7'd39: begin
  397.               scl <= 1'b0;
  398.               cnt <= 1'b0;
  399.             end
  400.             default: ;
  401.           endcase
  402.         end
  403.         st_data_rd: begin  //读取数据(8 bit)
  404.           case (cnt)
  405.             7'd0:    sda_dir <= 1'b0;
  406.             7'd1: begin
  407.               data_r[7] <= sda_in;
  408.               scl       <= 1'b1;
  409.             end
  410.             7'd3:    scl <= 1'b0;
  411.             7'd5: begin
  412.               data_r[6] <= sda_in;
  413.               scl       <= 1'b1;
  414.             end
  415.             7'd7:    scl <= 1'b0;
  416.             7'd9: begin
  417.               data_r[5] <= sda_in;
  418.               scl       <= 1'b1;
  419.             end
  420.             7'd11:   scl <= 1'b0;
  421.             7'd13: begin
  422.               data_r[4] <= sda_in;
  423.               scl       <= 1'b1;
  424.             end
  425.             7'd15:   scl <= 1'b0;
  426.             7'd17: begin
  427.               data_r[3] <= sda_in;
  428.               scl       <= 1'b1;
  429.             end
  430.             7'd19:   scl <= 1'b0;
  431.             7'd21: begin
  432.               data_r[2] <= sda_in;
  433.               scl       <= 1'b1;
  434.             end
  435.             7'd23:   scl <= 1'b0;
  436.             7'd25: begin
  437.               data_r[1] <= sda_in;
  438.               scl       <= 1'b1;
  439.             end
  440.             7'd27:   scl <= 1'b0;
  441.             7'd29: begin
  442.               data_r[0] <= sda_in;
  443.               scl       <= 1'b1;
  444.             end
  445.             7'd31:   scl <= 1'b0;
  446.             7'd32: begin
  447.               sda_dir <= 1'b1;
  448.               sda_out <= 1'b1;
  449.             end
  450.             7'd33:   scl <= 1'b1;
  451.             7'd34:   st_done <= 1'b1;  //非应答
  452.             7'd35: begin
  453.               scl <= 1'b0;
  454.               cnt <= 1'b0;
  455.               i2c_data_r <= data_r;
  456.             end
  457.             default: ;
  458.           endcase
  459.         end
  460.         st_stop: begin  //结束I2C操作
  461.           case (cnt)
  462.             7'd0: begin
  463.               sda_dir <= 1'b1;  //结束I2C
  464.               sda_out <= 1'b0;
  465.             end
  466.             7'd1:    scl <= 1'b1;
  467.             7'd3:    sda_out <= 1'b1;
  468.             7'd15:   st_done <= 1'b1;
  469.             7'd16: begin
  470.               cnt      <= 1'b0;
  471.               i2c_done <= 1'b1;  //向上层模块传递I2C结束信号
  472.             end
  473.             default: ;
  474.           endcase
  475.         end
  476.       endcase
  477.     end
  478.   end
  479.  
  480. endmodule

3.4 摄像头数据采集模块

  1. `timescale 1ns / 1ps
  2. //摄像头数据采集模块
  3.  
  4. module cmos_capture_data (
  5.     input         rst_n,             //复位信号    
  6.     //摄像头接口                           
  7.     input         cam_pclk,          //cmos 数据像素时钟
  8.     input         cam_vsync,         //cmos 场同步信号
  9.     input         cam_href,          //cmos 行同步信号
  10.     input  [ 7:0] cam_data,
  11.     //用户接口                              
  12.     output        cmos_frame_vsync,  //帧有效信号    
  13.     output        cmos_frame_href,   //行有效信号
  14.     output        cmos_frame_valid,  //数据有效使能信号
  15.     output [15:0] cmos_frame_data    //有效数据        
  16. );
  17.  
  18.   //寄存器全部配置完成后，先等待10帧数据
  19.   //待寄存器配置生效后再开始采集图像
  20.   parameter WAIT_FRAME = 4'd10;  //寄存器数据稳定等待的帧个数            
  22.   //reg define                     
  23.   reg         cam_vsync_d0;
  24.   reg         cam_vsync_d1;
  25.   reg         cam_href_d0;
  26.   reg         cam_href_d1;
  27.   reg  [ 3:0] cmos_ps_cnt;  //等待帧数稳定计数器
  28.   reg  [ 7:0] cam_data_d0;
  29.   reg  [15:0] cmos_data_t;  //用于8位转16位的临时寄存器
  30.   reg         byte_flag;  //16位RGB数据转换完成的标志信号
  31.   reg         byte_flag_d0;
  32.   reg         frame_val_flag;  //帧有效的标志 
  34.   wire        pos_vsync;  //采输入场同步信号的上升沿
  36.   //*****************************************************
  37.   //**                    main code
  38.   //*****************************************************
  40.   //采输入场同步信号的上升沿
  41.   assign pos_vsync = (~cam_vsync_d1) & cam_vsync_d0;
  43.   //输出帧有效信号
  44.   assign cmos_frame_vsync = frame_val_flag ? cam_vsync_d1 : 1'b0;
  45.  
  46.   //输出行有效信号
  47.   assign cmos_frame_href = frame_val_flag ? cam_href_d1 : 1'b0;
  49.   //输出数据使能有效信号
  50.   assign cmos_frame_valid = frame_val_flag ? byte_flag_d0 : 1'b0;
  51.  
  52.   //输出数据
  53.   assign cmos_frame_data = frame_val_flag ? cmos_data_t : 1'b0;
  55.   always @(posedge cam_pclk or negedge rst_n) begin
  56.     if (!rst_n) begin
  57.       cam_vsync_d0 <= 1'b0;
  58.       cam_vsync_d1 <= 1'b0;
  59.       cam_href_d0  <= 1'b0;
  60.       cam_href_d1  <= 1'b0;
  61.     end else begin
  62.       cam_vsync_d0 <= cam_vsync;
  63.       cam_vsync_d1 <= cam_vsync_d0;
  64.       cam_href_d0  <= cam_href;
  65.       cam_href_d1  <= cam_href_d0;
  66.     end
  67.   end
  69.   //对帧数进行计数
  70.   always @(posedge cam_pclk or negedge rst_n) begin
  71.     if (!rst_n) cmos_ps_cnt <= 4'd0;
  72.     else if (pos_vsync && (cmos_ps_cnt < WAIT_FRAME)) cmos_ps_cnt <= cmos_ps_cnt + 4'd1;
  73.   end
  75.   //帧有效标志
  76.   always @(posedge cam_pclk or negedge rst_n) begin
  77.     if (!rst_n) frame_val_flag <= 1'b0;
  78.     else if ((cmos_ps_cnt == WAIT_FRAME) && pos_vsync) frame_val_flag <= 1'b1;
  79.     else;
  80.   end
  82.   //8位数据转16位RGB565数据        
  83.   always @(posedge cam_pclk or negedge rst_n) begin
  84.     if (!rst_n) begin
  85.       cmos_data_t <= 16'd0;
  86.       cam_data_d0 <= 8'd0;
  87.       byte_flag   <= 1'b0;
  88.     end else if (cam_href) begin
  89.       byte_flag   <= ~byte_flag;
  90.       cam_data_d0 <= cam_data;
  91.       if (byte_flag) cmos_data_t <= {cam_data_d0, cam_data};
  92.       else;
  93.     end else begin
  94.       byte_flag   <= 1'b0;
  95.       cam_data_d0 <= 8'b0;
  96.     end
  97.   end
  98.  
  99.   //产生输出数据有效信号(cmos_frame_valid)
  100.   always @(posedge cam_pclk or negedge rst_n) begin
  101.     if (!rst_n) byte_flag_d0 <= 1'b0;
  102.     else byte_flag_d0 <= byte_flag;
  103.   end
  105. endmodule

3.5 图像开始传输控制模块

  1. `timescale 1ns / 1ps
  2. //图像开始传输控制模块
  3.  
  4.  
  5. module start_transfer_ctrl (
  6.     input             clk,               //时钟信号
  7.     input             rst_n,             //复位信号，低电平有效
  8.     input             udp_rec_pkt_done,  //GMII接收时钟 
  9.     input             udp_rec_en,        //UDP单包数据接收完成信号
  10.     input      [31:0] udp_rec_data,      //UDP接收的数据使能信号 
  11.     input      [15:0] udp_rec_byte_num,  //UDP接收的数据
  12.                                          //UDP接收到的字节数
  13.     output reg        transfer_flag      //图像开始传输标志,0:开始传输 1:停止传输
  14. );
  15.  
  16.   //parameter define
  17.   parameter START = "1";  //开始命令
  18.   parameter STOP = "0";  //停止命令
  19.  
  20.   //*****************************************************
  21.   //**                    main code
  22.   //*****************************************************
  23.  
  24.   //解析接收到的数据
  25.   always @(posedge clk or negedge rst_n) begin
  26.     if (!rst_n) transfer_flag <= 1'b0;
  27.     else if (udp_rec_pkt_done && udp_rec_byte_num == 1'b1) begin
  28.       if (udp_rec_data[31:24] == START)  //开始传输
  29.         transfer_flag <= 1'b1;
  30.       else if (udp_rec_data[31:24] == STOP)  //停止传输
  31.         transfer_flag <= 1'b0;
  32.     end
  33.   end
  34.  
  35. endmodule

3.6 图像封装模块

  1. `timescale 1ns / 1ps
  2. //图像封装模块(添加帧头)    
  3.  
  4.  
  5. module img_data_pkt (
  6.     input        rst_n,        //复位信号，低电平有效
  7.     //图像相关信号
  8.     input        cam_pclk,     //像素时钟
  9.     input        img_vsync,    //帧同步信号
  10.     input        img_data_en,  //数据有效使能信号
  11.     input [15:0] img_data,     //有效数据 
  12.  
  13.     input             transfer_flag,    //图像开始传输标志,0:开始传输 1:停止传输
  14.     //以太网相关信号 
  15.     input             eth_tx_clk,       //以太网发送时钟
  16.     input             udp_tx_req,       //udp发送数据请求信号
  17.     input             udp_tx_done,      //udp发送数据完成信号                               
  18.     output reg        udp_tx_start_en,  //udp开始发送信号
  19.     output     [31:0] udp_tx_data,      //udp发送的数据
  20.     output reg [15:0] udp_tx_byte_num   //udp单包发送的有效字节数
  21. );
  22.  
  23.   //parameter define
  24.   parameter CMOS_H_PIXEL = 16'd640;  //图像水平方向分辨率
  25.   parameter CMOS_V_PIXEL = 16'd480;  //图像垂直方向分辨率
  26.   //图像帧头,用于标志一帧数据的开始
  27.   parameter IMG_FRAME_HEAD = {32'hf0_5a_a5_0f};
  29.   reg         img_vsync_d0;  //帧有效信号打拍
  30.   reg         img_vsync_d1;  //帧有效信号打拍
  31.   reg         neg_vsync_d0;  //帧有效信号下降沿打拍
  33.   reg         wr_sw;  //用于位拼接的标志
  34.   reg  [15:0] img_data_d0;  //有效图像数据打拍
  35.   reg         wr_fifo_en;  //写fifo使能
  36.   reg  [31:0] wr_fifo_data;  //写fifo数据
  38.   reg         img_vsync_txc_d0;  //以太网发送时钟域下,帧有效信号打拍
  39.   reg         img_vsync_txc_d1;  //以太网发送时钟域下,帧有效信号打拍
  40.   reg         tx_busy_flag;  //发送忙信号标志
  42.   //wire define                   
  43.   wire        pos_vsync;  //帧有效信号上升沿
  44.   wire        neg_vsync;  //帧有效信号下降沿
  45.   wire        neg_vsynt_txc;  //以太网发送时钟域下,帧有效信号下降沿
  46.   wire [ 9:0] fifo_rdusedw;  //当前FIFO缓存的个数
  48.   //*****************************************************
  49.   //**                    main code
  50.   //*****************************************************
  52.   //信号采沿
  53.   assign neg_vsync = img_vsync_d1 & (~img_vsync_d0);
  54.   assign pos_vsync = ~img_vsync_d1 & img_vsync_d0;
  55.   assign neg_vsynt_txc = ~img_vsync_txc_d1 & img_vsync_txc_d0;
  57.   //对img_vsync信号延时两个时钟周期,用于采沿
  58.   always @(posedge cam_pclk or negedge rst_n) begin
  59.     if (!rst_n) begin
  60.       img_vsync_d0 <= 1'b0;
  61.       img_vsync_d1 <= 1'b0;
  62.     end else begin
  63.       img_vsync_d0 <= img_vsync;
  64.       img_vsync_d1 <= img_vsync_d0;
  65.     end
  66.   end
  68.   //寄存neg_vsync信号
  69.   always @(posedge cam_pclk or negedge rst_n) begin
  70.     if (!rst_n) neg_vsync_d0 <= 1'b0;
  71.     else neg_vsync_d0 <= neg_vsync;
  72.   end
  73.  
  74.   //对wr_sw和img_data_d0信号赋值,用于位拼接
  75.   always @(posedge cam_pclk or negedge rst_n) begin
  76.     if (!rst_n) begin
  77.       wr_sw <= 1'b0;
  78.       img_data_d0 <= 1'b0;
  79.     end else if (neg_vsync) wr_sw <= 1'b0;
  80.     else if (img_data_en) begin
  81.       wr_sw <= ~wr_sw;
  82.       img_data_d0 <= img_data;
  83.     end
  84.   end
  86.   //将帧头和图像数据写入FIFO
  87.   always @(posedge cam_pclk or negedge rst_n) begin
  88.     if (!rst_n) begin
  89.       wr_fifo_en   <= 1'b0;
  90.       wr_fifo_data <= 1'b0;
  91.     end else begin
  92.       if (neg_vsync) begin
  93.         wr_fifo_en   <= 1'b1;
  94.         wr_fifo_data <= IMG_FRAME_HEAD;  //帧头
  95.       end else if (neg_vsync_d0) begin
  96.         wr_fifo_en   <= 1'b1;
  97.         wr_fifo_data <= {CMOS_H_PIXEL, CMOS_V_PIXEL};  //水平和垂直方向分辨率
  98.       end else if (img_data_en && wr_sw) begin
  99.         wr_fifo_en   <= 1'b1;
  100.         wr_fifo_data <= {img_data_d0, img_data};  //图像数据位拼接,16位转32位
  101.       end else begin
  102.         wr_fifo_en   <= 1'b0;
  103.         wr_fifo_data <= 1'b0;
  104.       end
  105.     end
  106.   end
  107.  
  108.   //以太网发送时钟域下,对img_vsync信号延时两个时钟周期,用于采沿
  109.   always @(posedge eth_tx_clk or negedge rst_n) begin
  110.     if (!rst_n) begin
  111.       img_vsync_txc_d0 <= 1'b0;
  112.       img_vsync_txc_d1 <= 1'b0;
  113.     end else begin
  114.       img_vsync_txc_d0 <= img_vsync;
  115.       img_vsync_txc_d1 <= img_vsync_txc_d0;
  116.     end
  117.   end
  118.  
  119.   //控制以太网发送的字节数
  120.   always @(posedge eth_tx_clk or negedge rst_n) begin
  121.     if (!rst_n) udp_tx_byte_num <= 1'b0;
  122.     else if (neg_vsynt_txc) udp_tx_byte_num <= {CMOS_H_PIXEL, 1'b0} + 16'd8;
  123.     else if (udp_tx_done) udp_tx_byte_num <= {CMOS_H_PIXEL, 1'b0};
  124.   end
  125.  
  126.   //控制以太网发送开始信号
  127.   always @(posedge eth_tx_clk or negedge rst_n) begin
  128.     if (!rst_n) begin
  129.       udp_tx_start_en <= 1'b0;
  130.       tx_busy_flag <= 1'b0;
  131.     end  //上位机未发送"开始"命令时,以太网不发送图像数据
  132.     else if (transfer_flag == 1'b0) begin
  133.       udp_tx_start_en <= 1'b0;
  134.       tx_busy_flag <= 1'b0;
  135.     end else begin
  136.       udp_tx_start_en <= 1'b0;
  137.       //当FIFO中的个数满足需要发送的字节数时
  138.       if (tx_busy_flag == 1'b0 && fifo_rdusedw >= udp_tx_byte_num[15:2]) begin
  139.         udp_tx_start_en <= 1'b1;  //开始控制发送一包数据
  140.         tx_busy_flag    <= 1'b1;
  141.       end else if (udp_tx_done || neg_vsynt_txc) tx_busy_flag <= 1'b0;
  142.     end
  143.   end
  144.  
  145.   //异步FIFO
  146.   async_fifo_1024x32b async_fifo_1024x32b_inst (
  147.       .rst          (pos_vsync | (~transfer_flag)),  // input wire rst
  148.       .wr_clk       (cam_pclk),                      // input wire wr_clk
  149.       .rd_clk       (eth_tx_clk),                    // input wire rd_clk
  150.       .din          (wr_fifo_data),                  // input wire [31 : 0] din
  151.       .wr_en        (wr_fifo_en),                    // input wire wr_en
  152.       .rd_en        (udp_tx_req),                    // input wire rd_en
  153.       .dout         (udp_tx_data),                   // output wire [31 : 0] dout
  154.       .full         (),                              // output wire full
  155.       .empty        (),                              // output wire empty
  156.       .rd_data_count(fifo_rdusedw),                  // output wire [9 : 0] rd_data_count
  157.       .wr_rst_busy  (),                              // output wire wr_rst_busy
  158.       .rd_rst_busy  ()                               // output wire rd_rst_busy
  159.   );
  160.  
  161.  
  162.  
  163.  
  164.  
  165. endmodule

 

3.7 以太网通信UDP通信顶层模块

  1. `timescale 1ns / 1ps
  2. //以太网通信UDP通信顶层模块
  3.  
  4.  
  5. module eth_top (
  6.     input        sys_rst_n,   //系统复位信号，低电平有效 
  7.     //以太网RGMII接口            
  8.     input        eth_rxc,     //RGMII接收数据时钟
  9.     input        eth_rx_ctl,  //RGMII输入数据有效信号
  10.     input  [3:0] eth_rxd,     //RGMII输入数据
  11.     output       eth_txc,     //RGMII发送数据时钟    
  12.     output       eth_tx_ctl,  //RGMII输出数据有效信号
  13.     output [3:0] eth_txd,     //RGMII输出数据          
  14.  
  15.     input         gmii_tx_clk,      //GMII发送时钟
  16.     input         udp_tx_start_en,  //以太网开始发送信号   
  17.     input  [31:0] tx_data,          //以太网待发送数据     
  18.     input  [15:0] tx_byte_num,      //以太网发送的有效字节数 单位:byte 
  19.     output        udp_tx_done,      //UDP发送完成信号  
  20.     output        tx_req,           //读数据请求信号    
  21.  
  22.     output        gmii_rx_clk,   //GMII接收时钟 
  23.     output        rec_pkt_done,  //UDP单包数据接收完成信号 
  24.     output        rec_en,        //UDP接收的数据使能信号          
  25.     output [31:0] rec_data,      //UDP接收的数据
  26.     output [15:0] rec_byte_num   //UDP接收到的字节数
  27. );
  28.  
  29.   //parameter define
  30.   //开发板MAC地址 00-11-22-33-44-55
  31.   parameter BOARD_MAC = 48'h00_11_22_33_44_55;
  32.   //开发板IP地址 192.168.1.10
  33.   parameter BOARD_IP = {8'd192, 8'd168, 8'd1, 8'd10};
  34.   //目的MAC地址 ff_ff_ff_ff_ff_ff
  35.   parameter DES_MAC = 48'hff_ff_ff_ff_ff_ff;
  36.   //目的IP地址 192.168.1.102     
  37.   parameter DES_IP = {8'd192, 8'd168, 8'd1, 8'd102};
  38.  
  39.   //wire define          
  40.   wire        gmii_rx_dv;  //GMII接收数据有效信号
  41.   wire [ 7:0] gmii_rxd;  //GMII接收数据
  42.   wire        gmii_tx_en;  //GMII发送数据使能信号
  43.   wire [ 7:0] gmii_txd;  //GMII发送数据     
  44.   wire        arp_gmii_tx_en;  //ARP GMII输出数据有效信号 
  45.   wire [ 7:0] arp_gmii_txd;  //ARP GMII输出数据
  46.   wire        arp_rx_done;  //ARP接收完成信号
  47.   wire        arp_rx_type;  //ARP接收类型 0:请求  1:应答
  48.   wire [47:0] src_mac;  //接收到目的MAC地址
  49.   wire [31:0] src_ip;  //接收到目的IP地址    
  50.   wire        arp_tx_en;  //ARP发送使能信号
  51.   wire        arp_tx_type;  //ARP发送类型 0:请求  1:应答
  52.   wire [47:0] des_mac;  //发送的目标MAC地址
  53.   wire [31:0] des_ip;  //发送的目标IP地址   
  54.   wire        arp_tx_done;  //ARP发送完成信号
  55.   wire        udp_gmii_tx_en;  //UDP GMII输出数据有效信号 
  56.   wire [ 7:0] udp_gmii_txd;  //UDP GMII输出数据
  57.  
  58.   //*****************************************************
  59.   //**                    main code
  60.   //*****************************************************
  61.  
  62.   assign des_mac = src_mac;
  63.   assign des_ip  = src_ip;
  64.   assign eth_txc = clk_125m_deg;
  65.  
  66.   clk_wiz u_clk_wiz (
  67.       // Clock out ports
  68.       .clk_out1(clk_125m_deg),  // output clk_out1
  69.       // Status and control signals
  70.       .reset   (~sys_rst_n),    // input reset
  71.       .locked  (locked),        // output locked
  72.       // Clock in ports
  73.       .clk_in1 (rgmii_txc)      // input clk_in1
  74.   );
  75.  
  76.   //GMII接口转RGMII接口
  77.   gmii_to_rgmii u_gmii_to_rgmii (
  78.       .gmii_rx_clk(gmii_rx_clk),
  79.       .gmii_rx_dv (gmii_rx_dv),
  80.       .gmii_rxd   (gmii_rxd),
  81.       .gmii_tx_clk(gmii_tx_clk),
  82.       .gmii_tx_en (gmii_tx_en),
  83.       .gmii_txd   (gmii_txd),
  84.  
  85.       .rgmii_rxc   (eth_rxc),
  86.       .rgmii_rx_ctl(eth_rx_ctl),
  87.       .rgmii_rxd   (eth_rxd),
  88.       .rgmii_txc   (rgmii_txc),
  89.       .rgmii_tx_ctl(eth_tx_ctl),
  90.       .rgmii_txd   (eth_txd)
  91.   );
  92.  
  93.   //ARP通信
  94.   arp #(
  95.       .BOARD_MAC(BOARD_MAC),  //参数例化
  96.       .BOARD_IP (BOARD_IP),
  97.       .DES_MAC  (DES_MAC),
  98.       .DES_IP   (DES_IP)
  99.   ) u_arp (
  100.       .rst_n(sys_rst_n),
  101.  
  102.       .gmii_rx_clk(gmii_rx_clk),
  103.       .gmii_rx_dv (gmii_rx_dv),
  104.       .gmii_rxd   (gmii_rxd),
  105.       .gmii_tx_clk(gmii_tx_clk),
  106.       .gmii_tx_en (arp_gmii_tx_en),
  107.       .gmii_txd   (arp_gmii_txd),
  108.  
  109.       .arp_rx_done(arp_rx_done),
  110.       .arp_rx_type(arp_rx_type),
  111.       .src_mac    (src_mac),
  112.       .src_ip     (src_ip),
  113.       .arp_tx_en  (arp_tx_en),
  114.       .arp_tx_type(arp_tx_type),
  115.       .des_mac    (des_mac),
  116.       .des_ip     (des_ip),
  117.       .tx_done    (arp_tx_done)
  118.   );
  119.  
  120.   //UDP通信
  121.   udp #(
  122.       .BOARD_MAC(BOARD_MAC),  //参数例化
  123.       .BOARD_IP (BOARD_IP),
  124.       .DES_MAC  (DES_MAC),
  125.       .DES_IP   (DES_IP)
  126.   ) u_udp (
  127.       .rst_n(sys_rst_n),
  128.  
  129.       .gmii_rx_clk(gmii_rx_clk),
  130.       .gmii_rx_dv (gmii_rx_dv),
  131.       .gmii_rxd   (gmii_rxd),
  132.       .gmii_tx_clk(gmii_tx_clk),
  133.       .gmii_tx_en (udp_gmii_tx_en),
  134.       .gmii_txd   (udp_gmii_txd),
  135.  
  136.       .rec_pkt_done(rec_pkt_done),
  137.       .rec_en      (rec_en),
  138.       .rec_data    (rec_data),
  139.       .rec_byte_num(rec_byte_num),
  140.       .tx_start_en (udp_tx_start_en),
  141.       .tx_data     (tx_data),
  142.       .tx_byte_num (tx_byte_num),
  143.       .des_mac     (des_mac),
  144.       .des_ip      (des_ip),
  145.       .tx_done     (udp_tx_done),
  146.       .tx_req      (tx_req)
  147.   );
  148.  
  149.   //以太网控制模块
  150.   eth_ctrl u_eth_ctrl (
  151.       .clk  (gmii_rx_clk),
  152.       .rst_n(sys_rst_n),
  153.  
  154.       .arp_rx_done   (arp_rx_done),
  155.       .arp_rx_type   (arp_rx_type),
  156.       .arp_tx_en     (arp_tx_en),
  157.       .arp_tx_type   (arp_tx_type),
  158.       .arp_tx_done   (arp_tx_done),
  159.       .arp_gmii_tx_en(arp_gmii_tx_en),
  160.       .arp_gmii_txd  (arp_gmii_txd),
  161.  
  162.       .udp_gmii_tx_en(udp_gmii_tx_en),
  163.       .udp_gmii_txd  (udp_gmii_txd),
  164.  
  165.       .gmii_tx_en(gmii_tx_en),
  166.       .gmii_txd  (gmii_txd)
  167.   );
  168.  
  169. endmodule

 

3.8 GMII接口转RGMII接口模块

  1. `timescale 1ns / 1ps
  2. //GMII接口转RGMII接口模块
  3.  
  4.  
  5. module gmii_to_rgmii (
  6.     //以太网GMII接口
  7.     output       gmii_rx_clk,   //GMII接收时钟
  8.     output       gmii_rx_dv,    //GMII接收数据有效信号
  9.     output [7:0] gmii_rxd,      //GMII接收数据
  10.     input        gmii_tx_clk,   //GMII发送时钟
  11.     input        gmii_tx_en,    //GMII发送数据使能信号
  12.     input  [7:0] gmii_txd,      //GMII发送数据            
  13.     //以太网RGMII接口   
  14.     input        rgmii_rxc,     //RGMII接收时钟
  15.     input        rgmii_rx_ctl,  //RGMII接收数据控制信号
  16.     input  [3:0] rgmii_rxd,     //RGMII接收数据
  17.     output       rgmii_txc,     //RGMII发送时钟    
  18.     output       rgmii_tx_ctl,  //RGMII发送数据控制信号
  19.     output [3:0] rgmii_txd      //RGMII发送数据          
  20. );
  21.  
  22.   //*****************************************************
  23.   //**                    main code
  24.   //*****************************************************
  25.  
  26.   assign gmii_tx_clk = gmii_rx_clk;
  27.  
  28.   //RGMII接收
  29.   rgmii_rx u_rgmii_rx (
  30.       .gmii_rx_clk (gmii_rx_clk),
  31.       .rgmii_rxc   (rgmii_rxc),
  32.       .rgmii_rx_ctl(rgmii_rx_ctl),
  33.       .rgmii_rxd   (rgmii_rxd),
  34.  
  35.       .gmii_rx_dv(gmii_rx_dv),
  36.       .gmii_rxd  (gmii_rxd)
  37.   );
  38.  
  39.   //RGMII发送
  40.   rgmii_tx u_rgmii_tx (
  41.       .gmii_tx_clk(gmii_tx_clk),
  42.       .gmii_tx_en (gmii_tx_en),
  43.       .gmii_txd   (gmii_txd),
  44.  
  45.       .rgmii_txc   (rgmii_txc),
  46.       .rgmii_tx_ctl(rgmii_tx_ctl),
  47.       .rgmii_txd   (rgmii_txd)
  48.   );
  49.  
  50. endmodule

3.8.1 RGMII接收模块

  1. `timescale 1ns / 1ps
  2. //RGMII接收模块
  3.  
  4.  
  5. module rgmii_rx (
  6.     //以太网RGMII接口
  7.     input       rgmii_rxc,     //RGMII接收时钟
  8.     input       rgmii_rx_ctl,  //RGMII接收数据控制信号
  9.     input [3:0] rgmii_rxd,     //RGMII接收数据    
  10.  
  11.     //以太网GMII接口
  12.     output       gmii_rx_clk,  //GMII接收时钟
  13.     output       gmii_rx_dv,   //GMII接收数据有效信号
  14.     output [7:0] gmii_rxd      //GMII接收数据   
  15. );
  16.  
  17.   //wire define
  18.   wire       rgmii_rxc_bufg;  //全局时钟缓存
  19.   wire       rgmii_rxc_bufio;  //全局时钟IO缓存
  20.   wire [1:0] gmii_rxdv_t;  //两位GMII接收有效信号 
  21.  
  22.   //*****************************************************
  23.   //**                    main code
  24.   //*****************************************************
  25.  
  26.   assign gmii_rx_clk = rgmii_rxc_bufg;
  27.   assign gmii_rx_dv  = gmii_rxdv_t[0] & gmii_rxdv_t[1];
  28.  
  29.   //全局时钟缓存
  30.   BUFG BUFG_inst (
  31.       .I(rgmii_rxc),      // 1-bit input: Clock input
  32.       .O(rgmii_rxc_bufg)  // 1-bit output: Clock output
  33.   );
  34.  
  35.   //全局时钟IO缓存
  36.   BUFIO BUFIO_inst (
  37.       .I(rgmii_rxc),       // 1-bit input: Clock input
  38.       .O(rgmii_rxc_bufio)  // 1-bit output: Clock output
  39.   );
  40.  
  41.   //将输入的上下边沿DDR信号，转换成两位单边沿SDR信号
  42.   IDDRE1 #(
  43.       .DDR_CLK_EDGE     ("SAME_EDGE_PIPELINED"),// IDDRE1 mode (OPPOSITE_EDGE, SAME_EDGE, SAME_EDGE_PIPELINED)
  44.       .IS_CB_INVERTED(1'b0),  // Optional inversion for CB
  45.       .IS_C_INVERTED(1'b0)  // Optional inversion for C
  46.   ) IDDRE1_inst (
  47.       .Q1(gmii_rxdv_t[0]),    // 1-bit output: Registered parallel output 1
  48.       .Q2(gmii_rxdv_t[1]),    // 1-bit output: Registered parallel output 2
  49.       .C (rgmii_rxc_bufio),   // 1-bit input: High-speed clock
  50.       .CB(~rgmii_rxc_bufio),  // 1-bit input: Inversion of High-speed clock C
  51.       .D (rgmii_rx_ctl),      // 1-bit input: Serial Data Input
  52.       .R (1'b0)               // 1-bit input: Active High Async Reset
  53.   );
  55.   genvar i;
  56.   generate
  57.     for (i = 0; i < 4; i = i + 1) begin : rxdata_bus
  58.       IDDRE1 #(
  59.           .DDR_CLK_EDGE      ("SAME_EDGE_PIPELINED"),  // IDDRE1 mode (OPPOSITE_EDGE, SAME_EDGE, SAME_EDGE_PIPELINED)
  60.           .IS_CB_INVERTED(1'b0),  // Optional inversion for CB
  61.           .IS_C_INVERTED(1'b0)  // Optional inversion for C
  62.       ) IDDRE1_inst (
  63.           .Q1(gmii_rxd[i]),       // 1-bit output: Registered parallel output 1
  64.           .Q2(gmii_rxd[4+i]),     // 1-bit output: Registered parallel output 2
  65.           .C (rgmii_rxc_bufio),   // 1-bit input: High-speed clock
  66.           .CB(~rgmii_rxc_bufio),  // 1-bit input: Inversion of High-speed clock C
  67.           .D (rgmii_rxd[i]),      // 1-bit input: Serial Data Input
  68.           .R (1'b0)               // 1-bit input: Active High Async Reset
  69.       );
  70.     end
  71.   endgenerate
  72.  
  73. endmodule

3.8.2 RGMII发送模块

  1. `timescale 1ns / 1ps
  2. //RGMII发送模块
  3.  
  4.  
  5. module rgmii_tx (
  6.     //GMII发送端口
  7.     input       gmii_tx_clk,  //GMII发送时钟    
  8.     input       gmii_tx_en,   //GMII输出数据有效信号
  9.     input [7:0] gmii_txd,     //GMII输出数据        
  10.  
  11.     //RGMII发送端口
  12.     output       rgmii_txc,     //RGMII发送数据时钟    
  13.     output       rgmii_tx_ctl,  //RGMII输出数据有效信号
  14.     output [3:0] rgmii_txd      //RGMII输出数据     
  15. );
  16.  
  17.   //*****************************************************
  18.   //**                    main code
  19.   //*****************************************************
  20.  
  21.   assign rgmii_txc = gmii_tx_clk;
  22.  
  23.   //输出双沿采样寄存器 (rgmii_tx_ctl)
  24.   ODDRE1 #(
  25.       .IS_C_INVERTED(1'b0),  // Optional inversion for C
  26.       .IS_D1_INVERTED(1'b0),  // Unsupported, do not use
  27.       .IS_D2_INVERTED(1'b0),  // Unsupported, do not use
  28.       .SIM_DEVICE        ("ULTRASCALE"),    // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,ULTRASCALE_PLUS_ES2)
  29.       .SRVAL(1'b0)  // Initializes the ODDRE1 Flip-Flops to the specified value (1'b0, 1'b1)
  30.   ) ODDRE1_tx_ctl (
  31.       .Q (rgmii_tx_ctl),  // 1-bit output: Data output to IOB
  32.       .C (gmii_tx_clk),   // 1-bit input: High-speed clock input
  33.       .D1(gmii_tx_en),    // 1-bit input: Parallel data input 1
  34.       .D2(gmii_tx_en),    // 1-bit input: Parallel data input 2
  35.       .SR(1'b0)           // 1-bit input: Active High Async Reset
  36.   );
  38.   genvar i;
  39.   generate
  40.     for (i = 0; i < 4; i = i + 1) begin : txdata_bus
  41.       ODDRE1 #(
  42.           .IS_C_INVERTED(1'b0),  // Optional inversion for C
  43.           .IS_D1_INVERTED(1'b0),  // Unsupported, do not use
  44.           .IS_D2_INVERTED(1'b0),  // Unsupported, do not use
  45.           .SIM_DEVICE("ULTRASCALE"), // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,ULTRASCALE_PLUS_ES2)
  46.           .SRVAL(1'b0)  // Initializes the ODDRE1 Flip-Flops to the specified value (1'b0, 1'b1)
  47.       ) ODDRE1_inst (
  48.           .Q (rgmii_txd[i]),   // 1-bit output: Data output to IOB
  49.           .C (gmii_tx_clk),    // 1-bit input: High-speed clock input
  50.           .D1(gmii_txd[i]),    // 1-bit input: Parallel data input 1
  51.           .D2(gmii_txd[4+i]),  // 1-bit input: Parallel data input 2
  52.           .SR(1'b0)            // 1-bit input: Active High Async Reset
  53.       );
  54.     end
  55.   endgenerate
  56.  
  57. endmodule

3.9 arp模块

  1. `timescale 1ns / 1ps
  2. //arp模块
  3.  
  4.  
  5. module arp (
  6.     input        rst_n,        //复位信号，低电平有效
  7.     //GMII接口
  8.     input        gmii_rx_clk,  //GMII接收数据时钟
  9.     input        gmii_rx_dv,   //GMII输入数据有效信号
  10.     input  [7:0] gmii_rxd,     //GMII输入数据
  11.     input        gmii_tx_clk,  //GMII发送数据时钟
  12.     output       gmii_tx_en,   //GMII输出数据有效信号
  13.     output [7:0] gmii_txd,     //GMII输出数据          
  14.  
  15.     //用户接口
  16.     output        arp_rx_done,  //ARP接收完成信号
  17.     output        arp_rx_type,  //ARP接收类型 0:请求  1:应答
  18.     output [47:0] src_mac,      //接收到目的MAC地址
  19.     output [31:0] src_ip,       //接收到目的IP地址    
  20.     input         arp_tx_en,    //ARP发送使能信号
  21.     input         arp_tx_type,  //ARP发送类型 0:请求  1:应答
  22.     input  [47:0] des_mac,      //发送的目标MAC地址
  23.     input  [31:0] des_ip,       //发送的目标IP地址
  24.     output        tx_done       //以太网发送完成信号    
  25. );
  26.  
  27.   //parameter define
  28.   //开发板MAC地址 00-11-22-33-44-55
  29.   parameter BOARD_MAC = 48'h00_11_22_33_44_55;
  30.   //开发板IP地址 192.168.1.10 
  31.   parameter BOARD_IP = {8'd192, 8'd168, 8'd1, 8'd10};
  32.   //目的MAC地址 ff_ff_ff_ff_ff_ff
  33.   parameter DES_MAC = 48'hff_ff_ff_ff_ff_ff;
  34.   //目的IP地址 192.168.1.102     
  35.   parameter DES_IP = {8'd192, 8'd168, 8'd1, 8'd102};
  36.  
  37.   //wire define
  38.   wire        crc_en;  //CRC开始校验使能
  39.   wire        crc_clr;  //CRC数据复位信号 
  40.   wire [ 7:0] crc_d8;  //输入待校验8位数据
  41.   wire [31:0] crc_data;  //CRC校验数据
  42.   wire [31:0] crc_next;  //CRC下次校验完成数据
  43.  
  44.   //*****************************************************
  45.   //**                    main code
  46.   //*****************************************************
  47.  
  48.   assign crc_d8 = gmii_txd;
  49.  
  50.   //ARP接收模块    
  51.   arp_rx #(
  52.       .BOARD_MAC(BOARD_MAC),  //参数例化
  53.       .BOARD_IP (BOARD_IP)
  54.   ) u_arp_rx (
  55.       .clk  (gmii_rx_clk),
  56.       .rst_n(rst_n),
  57.  
  58.       .gmii_rx_dv (gmii_rx_dv),
  59.       .gmii_rxd   (gmii_rxd),
  60.       .arp_rx_done(arp_rx_done),
  61.       .arp_rx_type(arp_rx_type),
  62.       .src_mac    (src_mac),
  63.       .src_ip     (src_ip)
  64.   );
  65.  
  66.   //ARP发送模块
  67.   arp_tx #(
  68.       .BOARD_MAC(BOARD_MAC),  //参数例化
  69.       .BOARD_IP (BOARD_IP),
  70.       .DES_MAC  (DES_MAC),
  71.       .DES_IP   (DES_IP)
  72.   ) u_arp_tx (
  73.       .clk  (gmii_tx_clk),
  74.       .rst_n(rst_n),
  75.  
  76.       .arp_tx_en  (arp_tx_en),
  77.       .arp_tx_type(arp_tx_type),
  78.       .des_mac    (des_mac),
  79.       .des_ip     (des_ip),
  80.       .crc_data   (crc_data),
  81.       .crc_next   (crc_next[31:24]),
  82.       .tx_done    (tx_done),
  83.       .gmii_tx_en (gmii_tx_en),
  84.       .gmii_txd   (gmii_txd),
  85.       .crc_en     (crc_en),
  86.       .crc_clr    (crc_clr)
  87.   );
  88.  
  89.   //以太网发送CRC校验模块
  90.   crc32_d8 u_crc32_d8 (
  91.       .clk     (gmii_tx_clk),
  92.       .rst_n   (rst_n),
  93.       .data    (crc_d8),
  94.       .crc_en  (crc_en),
  95.       .crc_clr (crc_clr),
  96.       .crc_data(crc_data),
  97.       .crc_next(crc_next)
  98.   );
  99.  
  100. endmodule

3.9.1 arp接收模块

  1. `timescale 1ns / 1ps
  2. //arp接收模块
  3.  
  4.  
  5. module arp_rx #(
  6.     //开发板MAC地址 00-11-22-33-44-55
  7.     parameter BOARD_MAC = 48'h00_11_22_33_44_55,
  8.     //开发板IP地址 192.168.1.10   
  9.     parameter BOARD_IP  = {8'd192, 8'd168, 8'd1, 8'd10}
  10. ) (
  11.     input clk,   //时钟信号
  12.     input rst_n, //复位信号，低电平有效
  14.     input             gmii_rx_dv,   //GMII输入数据有效信号
  15.     input      [ 7:0] gmii_rxd,     //GMII输入数据
  16.     output reg        arp_rx_done,  //ARP接收完成信号
  17.     output reg        arp_rx_type,  //ARP接收类型 0:请求  1:应答
  18.     output reg [47:0] src_mac,      //接收到的源MAC地址
  19.     output reg [31:0] src_ip        //接收到的源IP地址
  20. );
  22.   //parameter define
  23.   localparam st_idle = 5'b0_0001;  //初始状态，等待接收前导码
  24.   localparam st_preamble = 5'b0_0010;  //接收前导码状态 
  25.   localparam st_eth_head = 5'b0_0100;  //接收以太网帧头
  26.   localparam st_arp_data = 5'b0_1000;  //接收ARP数据
  27.   localparam st_rx_end = 5'b1_0000;  //接收结束
  28.  
  29.   localparam ETH_TPYE = 16'h0806;  //以太网帧类型 ARP
  31.   //reg define
  32.   reg [ 4:0] cur_state;
  33.   reg [ 4:0] next_state;
  35.   reg        skip_en;  //控制状态跳转使能信号
  36.   reg        error_en;  //解析错误使能信号
  37.   reg [ 4:0] cnt;  //解析数据计数器
  38.   reg [47:0] des_mac_t;  //接收到的目的MAC地址
  39.   reg [31:0] des_ip_t;  //接收到的目的IP地址
  40.   reg [47:0] src_mac_t;  //接收到的源MAC地址
  41.   reg [31:0] src_ip_t;  //接收到的源IP地址
  42.   reg [15:0] eth_type;  //以太网类型
  43.   reg [15:0] op_data;  //操作码
  45.   //*****************************************************
  46.   //**                    main code
  47.   //*****************************************************
  49.   //(三段式状态机)同步时序描述状态转移
  50.   always @(posedge clk or negedge rst_n) begin
  51.     if (!rst_n) cur_state <= st_idle;
  52.     else cur_state <= next_state;
  53.   end
  55.   //组合逻辑判断状态转移条件
  56.   always @(*) begin
  57.     next_state = st_idle;
  58.     case (cur_state)
  59.       st_idle: begin  //等待接收前导码
  60.         if (skip_en) next_state = st_preamble;
  61.         else next_state = st_idle;
  62.       end
  63.       st_preamble: begin  //接收前导码
  64.         if (skip_en) next_state = st_eth_head;
  65.         else if (error_en) next_state = st_rx_end;
  66.         else next_state = st_preamble;
  67.       end
  68.       st_eth_head: begin  //接收以太网帧头
  69.         if (skip_en) next_state = st_arp_data;
  70.         else if (error_en) next_state = st_rx_end;
  71.         else next_state = st_eth_head;
  72.       end
  73.       st_arp_data: begin  //接收ARP数据
  74.         if (skip_en) next_state = st_rx_end;
  75.         else if (error_en) next_state = st_rx_end;
  76.         else next_state = st_arp_data;
  77.       end
  78.       st_rx_end: begin  //接收结束
  79.         if (skip_en) next_state = st_idle;
  80.         else next_state = st_rx_end;
  81.       end
  82.       default: next_state = st_idle;
  83.     endcase
  84.   end
  86.   //时序电路描述状态输出,解析以太网数据
  87.   always @(posedge clk or negedge rst_n) begin
  88.     if (!rst_n) begin
  89.       skip_en <= 1'b0;
  90.       error_en <= 1'b0;
  91.       cnt <= 5'd0;
  92.       des_mac_t <= 48'd0;
  93.       des_ip_t <= 32'd0;
  94.       src_mac_t <= 48'd0;
  95.       src_ip_t <= 32'd0;
  96.       eth_type <= 16'd0;
  97.       op_data <= 16'd0;
  98.       arp_rx_done <= 1'b0;
  99.       arp_rx_type <= 1'b0;
  100.       src_mac <= 48'd0;
  101.       src_ip <= 32'd0;
  102.     end else begin
  103.       skip_en <= 1'b0;
  104.       error_en <= 1'b0;
  105.       arp_rx_done <= 1'b0;
  106.       case (next_state)
  107.         st_idle: begin  //检测到第一个8'h55
  108.           if ((gmii_rx_dv == 1'b1) && (gmii_rxd == 8'h55)) skip_en <= 1'b1;
  109.         end
  110.         st_preamble: begin
  111.           if (gmii_rx_dv) begin  //解析前导码
  112.             cnt <= cnt + 5'd1;
  113.             if ((cnt < 5'd6) && (gmii_rxd != 8'h55))  //7个8'h55  
  114.               error_en <= 1'b1;
  115.             else if (cnt == 5'd6) begin
  116.               cnt <= 5'd0;
  117.               if (gmii_rxd == 8'hd5)  //1个8'hd5
  118.                 skip_en <= 1'b1;
  119.               else error_en <= 1'b1;
  120.             end
  121.           end
  122.         end
  123.         st_eth_head: begin
  124.           if (gmii_rx_dv) begin
  125.             cnt <= cnt + 5'b1;
  126.             if (cnt < 5'd6) des_mac_t <= {des_mac_t[39:0], gmii_rxd};
  127.             else if (cnt == 5'd6) begin
  128.               //判断MAC地址是否为开发板MAC地址或者公共地址
  129.               if ((des_mac_t != BOARD_MAC) && (des_mac_t != 48'hff_ff_ff_ff_ff_ff))
  130.                 error_en <= 1'b1;
  131.             end else if (cnt == 5'd12) eth_type[15:8] <= gmii_rxd;  //以太网协议类型
  132.             else if (cnt == 5'd13) begin
  133.               eth_type[7:0] <= gmii_rxd;
  134.               cnt <= 5'd0;
  135.               if (eth_type[15:8] == ETH_TPYE[15:8]  //判断是否为ARP协议
  136.                   && gmii_rxd == ETH_TPYE[7:0])
  137.                 skip_en <= 1'b1;
  138.               else error_en <= 1'b1;
  139.             end
  140.           end
  141.         end
  142.         st_arp_data: begin
  143.           if (gmii_rx_dv) begin
  144.             cnt <= cnt + 5'd1;
  145.             if (cnt == 5'd6) op_data[15:8] <= gmii_rxd;  //操作码       
  146.             else if (cnt == 5'd7) op_data[7:0] <= gmii_rxd;
  147.             else if (cnt >= 5'd8 && cnt < 5'd14)  //源MAC地址
  148.               src_mac_t <= {src_mac_t[39:0], gmii_rxd};
  149.             else if (cnt >= 5'd14 && cnt < 5'd18)  //源IP地址
  150.               src_ip_t <= {src_ip_t[23:0], gmii_rxd};
  151.             else if (cnt >= 5'd24 && cnt < 5'd28)  //目标IP地址
  152.               des_ip_t <= {des_ip_t[23:0], gmii_rxd};
  153.             else if (cnt == 5'd28) begin
  154.               cnt <= 5'd0;
  155.               if (des_ip_t == BOARD_IP) begin  //判断目的IP地址和操作码
  156.                 if ((op_data == 16'd1) || (op_data == 16'd2)) begin
  157.                   skip_en <= 1'b1;
  158.                   arp_rx_done <= 1'b1;
  159.                   src_mac <= src_mac_t;
  160.                   src_ip <= src_ip_t;
  161.                   src_mac_t <= 48'd0;
  162.                   src_ip_t <= 32'd0;
  163.                   des_mac_t <= 48'd0;
  164.                   des_ip_t <= 32'd0;
  165.                   if (op_data == 16'd1) arp_rx_type <= 1'b0;  //ARP请求
  166.                   else arp_rx_type <= 1'b1;  //ARP应答
  167.                 end else error_en <= 1'b1;
  168.               end else error_en <= 1'b1;
  169.             end
  170.           end
  171.         end
  172.         st_rx_end: begin
  173.           cnt <= 5'd0;
  174.           //单包数据接收完成   
  175.           if (gmii_rx_dv == 1'b0 && skip_en == 1'b0) skip_en <= 1'b1;
  176.         end
  177.         default: ;
  178.       endcase
  179.     end
  180.   end
  181.  
  182. endmodule

3.9.2 arp发送模块

  1. `timescale 1ns / 1ps
  2. //arp发送模块
  3.  
  4.  
  5. module arp_tx (
  6.     input clk,   //时钟信号
  7.     input rst_n, //复位信号，低电平有效
  8.  
  9.     input             arp_tx_en,    //ARP发送使能信号
  10.     input             arp_tx_type,  //ARP发送类型 0:请求  1:应答
  11.     input      [47:0] des_mac,      //发送的目标MAC地址
  12.     input      [31:0] des_ip,       //发送的目标IP地址
  13.     input      [31:0] crc_data,     //CRC校验数据
  14.     input      [ 7:0] crc_next,     //CRC下次校验完成数据
  15.     output reg        tx_done,      //以太网发送完成信号
  16.     output reg        gmii_tx_en,   //GMII输出数据有效信号
  17.     output reg [ 7:0] gmii_txd,     //GMII输出数据
  18.     output reg        crc_en,       //CRC开始校验使能
  19.     output reg        crc_clr       //CRC数据复位信号 
  20. );
  21.  
  22.   //parameter define
  23.   //开发板MAC地址 00-11-22-33-44-55
  24.   parameter BOARD_MAC = 48'h00_11_22_33_44_55;
  25.   //开发板IP地址 192.168.1.10
  26.   parameter BOARD_IP = {8'd192, 8'd168, 8'd1, 8'd10};
  27.   //目的MAC地址 ff_ff_ff_ff_ff_ff
  28.   parameter DES_MAC = 48'hff_ff_ff_ff_ff_ff;
  29.   //目的IP地址 192.168.1.102     
  30.   parameter DES_IP = {8'd192, 8'd168, 8'd1, 8'd102};
  31.  
  32.   localparam st_idle = 5'b0_0001;  //初始状态，等待开始发送信号
  33.   localparam st_preamble = 5'b0_0010;  //发送前导码+帧起始界定符
  34.   localparam st_eth_head = 5'b0_0100;  //发送以太网帧头
  35.   localparam st_arp_data = 5'b0_1000;  //
  36.   localparam st_crc = 5'b1_0000;  //发送CRC校验值
  38.   localparam ETH_TYPE = 16'h0806;  //以太网帧类型 ARP协议
  39.   localparam HD_TYPE = 16'h0001;  //硬件类型 以太网
  40.   localparam PROTOCOL_TYPE = 16'h0800;  //上层协议为IP协议
  41.   //以太网数据最小为46个字节,不足部分填充数据
  42.   localparam MIN_DATA_NUM = 16'd46;
  44.   //reg define
  45.   reg  [4:0] cur_state;
  46.   reg  [4:0] next_state;
  48.   reg  [7:0] preamble                                  [ 7:0];  //前导码+SFD
  49.   reg  [7:0] eth_head                                  [13:0];  //以太网首部
  50.   reg  [7:0] arp_data                                  [27:0];  //ARP数据
  52.   reg        tx_en_d0;  //arp_tx_en信号延时
  53.   reg        tx_en_d1;
  54.   reg        skip_en;  //控制状态跳转使能信号
  55.   reg  [5:0] cnt;
  56.   reg  [4:0] data_cnt;  //发送数据个数计数器
  57.   reg        tx_done_t;
  59.   //wire define                   
  60.   wire       pos_tx_en;  //arp_tx_en信号上升沿
  62.   //*****************************************************
  63.   //**                    main code
  64.   //*****************************************************
  66.   assign pos_tx_en = (~tx_en_d1) & tx_en_d0;
  68.   //对arp_tx_en信号延时打拍两次,用于采arp_tx_en的上升沿
  69.   always @(posedge clk or negedge rst_n) begin
  70.     if (!rst_n) begin
  71.       tx_en_d0 <= 1'b0;
  72.       tx_en_d1 <= 1'b0;
  73.     end else begin
  74.       tx_en_d0 <= arp_tx_en;
  75.       tx_en_d1 <= tx_en_d0;
  76.     end
  77.   end
  79.   //(三段式状态机)同步时序描述状态转移
  80.   always @(posedge clk or negedge rst_n) begin
  81.     if (!rst_n) cur_state <= st_idle;
  82.     else cur_state <= next_state;
  83.   end
  85.   //组合逻辑判断状态转移条件
  86.   always @(*) begin
  87.     next_state = st_idle;
  88.     case (cur_state)
  89.       st_idle: begin  //空闲状态
  90.         if (skip_en) next_state = st_preamble;
  91.         else next_state = st_idle;
  92.       end
  93.       st_preamble: begin  //发送前导码+帧起始界定符
  94.         if (skip_en) next_state = st_eth_head;
  95.         else next_state = st_preamble;
  96.       end
  97.       st_eth_head: begin  //发送以太网首部
  98.         if (skip_en) next_state = st_arp_data;
  99.         else next_state = st_eth_head;
  100.       end
  101.       st_arp_data: begin  //发送ARP数据                      
  102.         if (skip_en) next_state = st_crc;
  103.         else next_state = st_arp_data;
  104.       end
  105.       st_crc: begin  //发送CRC校验值
  106.         if (skip_en) next_state = st_idle;
  107.         else next_state = st_crc;
  108.       end
  109.       default: next_state = st_idle;
  110.     endcase
  111.   end
  113.   //时序电路描述状态输出，发送以太网数据
  114.   always @(posedge clk or negedge rst_n) begin
  115.     if (!rst_n) begin
  116.       skip_en      <= 1'b0;
  117.       cnt          <= 6'd0;
  118.       data_cnt     <= 5'd0;
  119.       crc_en       <= 1'b0;
  120.       gmii_tx_en   <= 1'b0;
  121.       gmii_txd     <= 8'd0;
  122.       tx_done_t    <= 1'b0;
  123.  
  124.       //初始化数组    
  125.       //前导码 7个8'h55 + 1个8'hd5 
  126.       preamble[0]  <= 8'h55;
  127.       preamble[1]  <= 8'h55;
  128.       preamble[2]  <= 8'h55;
  129.       preamble[3]  <= 8'h55;
  130.       preamble[4]  <= 8'h55;
  131.       preamble[5]  <= 8'h55;
  132.       preamble[6]  <= 8'h55;
  133.       preamble[7]  <= 8'hd5;
  134.       //以太网帧头 
  135.       eth_head[0]  <= DES_MAC[47:40];  //目的MAC地址
  136.       eth_head[1]  <= DES_MAC[39:32];
  137.       eth_head[2]  <= DES_MAC[31:24];
  138.       eth_head[3]  <= DES_MAC[23:16];
  139.       eth_head[4]  <= DES_MAC[15:8];
  140.       eth_head[5]  <= DES_MAC[7:0];
  141.       eth_head[6]  <= BOARD_MAC[47:40];  //源MAC地址
  142.       eth_head[7]  <= BOARD_MAC[39:32];
  143.       eth_head[8]  <= BOARD_MAC[31:24];
  144.       eth_head[9]  <= BOARD_MAC[23:16];
  145.       eth_head[10] <= BOARD_MAC[15:8];
  146.       eth_head[11] <= BOARD_MAC[7:0];
  147.       eth_head[12] <= ETH_TYPE[15:8];  //以太网帧类型
  148.       eth_head[13] <= ETH_TYPE[7:0];
  149.       //ARP数据                           
  150.       arp_data[0]  <= HD_TYPE[15:8];  //硬件类型
  151.       arp_data[1]  <= HD_TYPE[7:0];
  152.       arp_data[2]  <= PROTOCOL_TYPE[15:8];  //上层协议类型
  153.       arp_data[3]  <= PROTOCOL_TYPE[7:0];
  154.       arp_data[4]  <= 8'h06;  //硬件地址长度,6
  155.       arp_data[5]  <= 8'h04;  //协议地址长度,4
  156.       arp_data[6]  <= 8'h00;  //OP,操作码 8'h01：ARP请求 8'h02:ARP应答
  157.       arp_data[7]  <= 8'h01;
  158.       arp_data[8]  <= BOARD_MAC[47:40];  //发送端(源)MAC地址
  159.       arp_data[9]  <= BOARD_MAC[39:32];
  160.       arp_data[10] <= BOARD_MAC[31:24];
  161.       arp_data[11] <= BOARD_MAC[23:16];
  162.       arp_data[12] <= BOARD_MAC[15:8];
  163.       arp_data[13] <= BOARD_MAC[7:0];
  164.       arp_data[14] <= BOARD_IP[31:24];  //发送端(源)IP地址
  165.       arp_data[15] <= BOARD_IP[23:16];
  166.       arp_data[16] <= BOARD_IP[15:8];
  167.       arp_data[17] <= BOARD_IP[7:0];
  168.       arp_data[18] <= DES_MAC[47:40];  //接收端(目的)MAC地址
  169.       arp_data[19] <= DES_MAC[39:32];
  170.       arp_data[20] <= DES_MAC[31:24];
  171.       arp_data[21] <= DES_MAC[23:16];
  172.       arp_data[22] <= DES_MAC[15:8];
  173.       arp_data[23] <= DES_MAC[7:0];
  174.       arp_data[24] <= DES_IP[31:24];  //接收端(目的)IP地址
  175.       arp_data[25] <= DES_IP[23:16];
  176.       arp_data[26] <= DES_IP[15:8];
  177.       arp_data[27] <= DES_IP[7:0];
  178.     end else begin
  179.       skip_en <= 1'b0;
  180.       crc_en <= 1'b0;
  181.       gmii_tx_en <= 1'b0;
  182.       tx_done_t <= 1'b0;
  183.       case (next_state)
  184.         st_idle: begin
  185.           if (pos_tx_en) begin
  186.             skip_en <= 1'b1;
  187.             //如果目标MAC地址和IP地址已经更新,则发送正确的地址
  188.             if ((des_mac != 48'b0) || (des_ip != 32'd0)) begin
  189.               eth_head[0]  <= des_mac[47:40];
  190.               eth_head[1]  <= des_mac[39:32];
  191.               eth_head[2]  <= des_mac[31:24];
  192.               eth_head[3]  <= des_mac[23:16];
  193.               eth_head[4]  <= des_mac[15:8];
  194.               eth_head[5]  <= des_mac[7:0];
  195.               arp_data[18] <= des_mac[47:40];
  196.               arp_data[19] <= des_mac[39:32];
  197.               arp_data[20] <= des_mac[31:24];
  198.               arp_data[21] <= des_mac[23:16];
  199.               arp_data[22] <= des_mac[15:8];
  200.               arp_data[23] <= des_mac[7:0];
  201.               arp_data[24] <= des_ip[31:24];
  202.               arp_data[25] <= des_ip[23:16];
  203.               arp_data[26] <= des_ip[15:8];
  204.               arp_data[27] <= des_ip[7:0];
  205.             end
  206.             if (arp_tx_type == 1'b0) arp_data[7] <= 8'h01;  //ARP请求 
  207.             else arp_data[7] <= 8'h02;  //ARP应答
  208.           end
  209.         end
  210.         st_preamble: begin  //发送前导码+帧起始界定符
  211.           gmii_tx_en <= 1'b1;
  212.           gmii_txd   <= preamble[cnt];
  213.           if (cnt == 6'd7) begin
  214.             skip_en <= 1'b1;
  215.             cnt <= 1'b0;
  216.           end else cnt <= cnt + 1'b1;
  217.         end
  218.         st_eth_head: begin  //发送以太网首部
  219.           gmii_tx_en <= 1'b1;
  220.           crc_en <= 1'b1;
  221.           gmii_txd <= eth_head[cnt];
  222.           if (cnt == 6'd13) begin
  223.             skip_en <= 1'b1;
  224.             cnt <= 1'b0;
  225.           end else cnt <= cnt + 1'b1;
  226.         end
  227.         st_arp_data: begin  //发送ARP数据  
  228.           crc_en <= 1'b1;
  229.           gmii_tx_en <= 1'b1;
  230.           //至少发送46个字节
  231.           if (cnt == MIN_DATA_NUM - 1'b1) begin
  232.             skip_en <= 1'b1;
  233.             cnt <= 1'b0;
  234.             data_cnt <= 1'b0;
  235.           end else cnt <= cnt + 1'b1;
  236.           if (data_cnt <= 6'd27) begin
  237.             data_cnt <= data_cnt + 1'b1;
  238.             gmii_txd <= arp_data[data_cnt];
  239.           end else gmii_txd <= 8'd0;  //Padding,填充0
  240.         end
  241.         st_crc: begin  //发送CRC校验值
  242.           gmii_tx_en <= 1'b1;
  243.           cnt <= cnt + 1'b1;
  244.           if (cnt == 6'd0)
  245.             gmii_txd <= {
  246.               ~crc_next[0],
  247.               ~crc_next[1],
  248.               ~crc_next[2],
  249.               ~crc_next[3],
  250.               ~crc_next[4],
  251.               ~crc_next[5],
  252.               ~crc_next[6],
  253.               ~crc_next[7]
  254.             };
  255.           else if (cnt == 6'd1)
  256.             gmii_txd <= {
  257.               ~crc_data[16],
  258.               ~crc_data[17],
  259.               ~crc_data[18],
  260.               ~crc_data[19],
  261.               ~crc_data[20],
  262.               ~crc_data[21],
  263.               ~crc_data[22],
  264.               ~crc_data[23]
  265.             };
  266.           else if (cnt == 6'd2) begin
  267.             gmii_txd <= {
  268.               ~crc_data[8],
  269.               ~crc_data[9],
  270.               ~crc_data[10],
  271.               ~crc_data[11],
  272.               ~crc_data[12],
  273.               ~crc_data[13],
  274.               ~crc_data[14],
  275.               ~crc_data[15]
  276.             };
  277.           end else if (cnt == 6'd3) begin
  278.             gmii_txd <= {
  279.               ~crc_data[0],
  280.               ~crc_data[1],
  281.               ~crc_data[2],
  282.               ~crc_data[3],
  283.               ~crc_data[4],
  284.               ~crc_data[5],
  285.               ~crc_data[6],
  286.               ~crc_data[7]
  287.             };
  288.             tx_done_t <= 1'b1;
  289.             skip_en <= 1'b1;
  290.             cnt <= 1'b0;
  291.           end
  292.         end
  293.         default: ;
  294.       endcase
  295.     end
  296.   end
  297.  
  298.   //发送完成信号及crc值复位信号
  299.   always @(posedge clk or negedge rst_n) begin
  300.     if (!rst_n) begin
  301.       tx_done <= 1'b0;
  302.       crc_clr <= 1'b0;
  303.     end else begin
  304.       tx_done <= tx_done_t;
  305.       crc_clr <= tx_done_t;
  306.     end
  307.   end
  308.  
  309. endmodule

3.9.3 CRC32校验模块

  1. `timescale 1ns / 1ps
  2. //CRC32校验模块
  3.  
  4.  
  5. module crc32_d8 (
  6.     input             clk,       //时钟信号
  7.     input             rst_n,     //复位信号，低电平有效
  8.     input      [ 7:0] data,      //输入待校验8位数据
  9.     input             crc_en,    //crc使能，开始校验标志
  10.     input             crc_clr,   //crc数据复位信号            
  11.     output reg [31:0] crc_data,  //CRC校验数据
  12.     output     [31:0] crc_next   //CRC下次校验完成数据
  13. );
  14.  
  15.   //*****************************************************
  16.   //**                    main code
  17.   //*****************************************************
  18.  
  19.   //输入待校验8位数据,需要先将高低位互换
  20.   wire [7:0] data_t;
  21.  
  22.   assign data_t = {data[0], data[1], data[2], data[3], data[4], data[5], data[6], data[7]};
  23.  
  24.   //CRC32的生成多项式为：G(x)= x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 
  25.   //+ x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
  26.  
  27.   assign crc_next[0] = crc_data[24] ^ crc_data[30] ^ data_t[0] ^ data_t[6];
  28.   assign crc_next[1] = crc_data[24] ^ crc_data[25] ^ crc_data[30] ^ crc_data[31] 
  29.                      ^ data_t[0] ^ data_t[1] ^ data_t[6] ^ data_t[7];
  30.   assign crc_next[2] = crc_data[24] ^ crc_data[25] ^ crc_data[26] ^ crc_data[30] 
  31.                      ^ crc_data[31] ^ data_t[0] ^ data_t[1] ^ data_t[2] ^ data_t[6] 
  32.                      ^ data_t[7];
  33.   assign crc_next[3] = crc_data[25] ^ crc_data[26] ^ crc_data[27] ^ crc_data[31] 
  34.                      ^ data_t[1] ^ data_t[2] ^ data_t[3] ^ data_t[7];
  35.   assign crc_next[4] = crc_data[24] ^ crc_data[26] ^ crc_data[27] ^ crc_data[28] 
  36.                      ^ crc_data[30] ^ data_t[0] ^ data_t[2] ^ data_t[3] ^ data_t[4] 
  37.                      ^ data_t[6];
  38.   assign crc_next[5] = crc_data[24] ^ crc_data[25] ^ crc_data[27] ^ crc_data[28] 
  39.                      ^ crc_data[29] ^ crc_data[30] ^ crc_data[31] ^ data_t[0] 
  40.                      ^ data_t[1] ^ data_t[3] ^ data_t[4] ^ data_t[5] ^ data_t[6] 
  41.                      ^ data_t[7];
  42.   assign crc_next[6] = crc_data[25] ^ crc_data[26] ^ crc_data[28] ^ crc_data[29] 
  43.                      ^ crc_data[30] ^ crc_data[31] ^ data_t[1] ^ data_t[2] ^ data_t[4] 
  44.                      ^ data_t[5] ^ data_t[6] ^ data_t[7];
  45.   assign crc_next[7] = crc_data[24] ^ crc_data[26] ^ crc_data[27] ^ crc_data[29] 
  46.                      ^ crc_data[31] ^ data_t[0] ^ data_t[2] ^ data_t[3] ^ data_t[5] 
  47.                      ^ data_t[7];
  48.   assign crc_next[8] = crc_data[0] ^ crc_data[24] ^ crc_data[25] ^ crc_data[27] 
  49.                      ^ crc_data[28] ^ data_t[0] ^ data_t[1] ^ data_t[3] ^ data_t[4];
  50.   assign crc_next[9] = crc_data[1] ^ crc_data[25] ^ crc_data[26] ^ crc_data[28] 
  51.                      ^ crc_data[29] ^ data_t[1] ^ data_t[2] ^ data_t[4] ^ data_t[5];
  52.   assign crc_next[10] = crc_data[2] ^ crc_data[24] ^ crc_data[26] ^ crc_data[27] 
  53.                      ^ crc_data[29] ^ data_t[0] ^ data_t[2] ^ data_t[3] ^ data_t[5];
  54.   assign crc_next[11] = crc_data[3] ^ crc_data[24] ^ crc_data[25] ^ crc_data[27] 
  55.                      ^ crc_data[28] ^ data_t[0] ^ data_t[1] ^ data_t[3] ^ data_t[4];
  56.   assign crc_next[12] = crc_data[4] ^ crc_data[24] ^ crc_data[25] ^ crc_data[26] 
  57.                      ^ crc_data[28] ^ crc_data[29] ^ crc_data[30] ^ data_t[0] 
  58.                      ^ data_t[1] ^ data_t[2] ^ data_t[4] ^ data_t[5] ^ data_t[6];
  59.   assign crc_next[13] = crc_data[5] ^ crc_data[25] ^ crc_data[26] ^ crc_data[27] 
  60.                      ^ crc_data[29] ^ crc_data[30] ^ crc_data[31] ^ data_t[1] 
  61.                      ^ data_t[2] ^ data_t[3] ^ data_t[5] ^ data_t[6] ^ data_t[7];
  62.   assign crc_next[14] = crc_data[6] ^ crc_data[26] ^ crc_data[27] ^ crc_data[28] 
  63.                      ^ crc_data[30] ^ crc_data[31] ^ data_t[2] ^ data_t[3] ^ data_t[4]
  64.                      ^ data_t[6] ^ data_t[7];
  65.   assign crc_next[15] =  crc_data[7] ^ crc_data[27] ^ crc_data[28] ^ crc_data[29]
  66.                      ^ crc_data[31] ^ data_t[3] ^ data_t[4] ^ data_t[5] ^ data_t[7];
  67.   assign crc_next[16] = crc_data[8] ^ crc_data[24] ^ crc_data[28] ^ crc_data[29] 
  68.                      ^ data_t[0] ^ data_t[4] ^ data_t[5];
  69.   assign crc_next[17] = crc_data[9] ^ crc_data[25] ^ crc_data[29] ^ crc_data[30] 
  70.                      ^ data_t[1] ^ data_t[5] ^ data_t[6];
  71.   assign crc_next[18] = crc_data[10] ^ crc_data[26] ^ crc_data[30] ^ crc_data[31] 
  72.                      ^ data_t[2] ^ data_t[6] ^ data_t[7];
  73.   assign crc_next[19] = crc_data[11] ^ crc_data[27] ^ crc_data[31] ^ data_t[3] ^ data_t[7];
  74.   assign crc_next[20] = crc_data[12] ^ crc_data[28] ^ data_t[4];
  75.   assign crc_next[21] = crc_data[13] ^ crc_data[29] ^ data_t[5];
  76.   assign crc_next[22] = crc_data[14] ^ crc_data[24] ^ data_t[0];
  77.   assign crc_next[23] = crc_data[15] ^ crc_data[24] ^ crc_data[25] ^ crc_data[30] 
  78.                       ^ data_t[0] ^ data_t[1] ^ data_t[6];
  79.   assign crc_next[24] = crc_data[16] ^ crc_data[25] ^ crc_data[26] ^ crc_data[31] 
  80.                       ^ data_t[1] ^ data_t[2] ^ data_t[7];
  81.   assign crc_next[25] = crc_data[17] ^ crc_data[26] ^ crc_data[27] ^ data_t[2] ^ data_t[3];
  82.   assign crc_next[26] = crc_data[18] ^ crc_data[24] ^ crc_data[27] ^ crc_data[28] 
  83.                       ^ crc_data[30] ^ data_t[0] ^ data_t[3] ^ data_t[4] ^ data_t[6];
  84.   assign crc_next[27] = crc_data[19] ^ crc_data[25] ^ crc_data[28] ^ crc_data[29] 
  85.                       ^ crc_data[31] ^ data_t[1] ^ data_t[4] ^ data_t[5] ^ data_t[7];
  86.   assign crc_next[28] = crc_data[20] ^ crc_data[26] ^ crc_data[29] ^ crc_data[30] 
  87.                       ^ data_t[2] ^ data_t[5] ^ data_t[6];
  88.   assign crc_next[29] = crc_data[21] ^ crc_data[27] ^ crc_data[30] ^ crc_data[31] 
  89.                       ^ data_t[3] ^ data_t[6] ^ data_t[7];
  90.   assign crc_next[30] = crc_data[22] ^ crc_data[28] ^ crc_data[31] ^ data_t[4] ^ data_t[7];
  91.   assign crc_next[31] = crc_data[23] ^ crc_data[29] ^ data_t[5];
  92.  
  93.   always @(posedge clk or negedge rst_n) begin
  94.     if (!rst_n) crc_data <= 32'hff_ff_ff_ff;
  95.     else if (crc_clr)  //CRC校验值复位
  96.       crc_data <= 32'hff_ff_ff_ff;
  97.     else if (crc_en) crc_data <= crc_next;
  98.   end
  99.  
  100. endmodule

3.10 udp模块

  1. `timescale 1ns / 1ps
  2. //udp模块
  3.  
  4.  
  5. module udp (
  6.     input         rst_n,         //复位信号，低电平有效
  7.     //GMII接口
  8.     input         gmii_rx_clk,   //GMII接收数据时钟
  9.     input         gmii_rx_dv,    //GMII输入数据有效信号
  10.     input  [ 7:0] gmii_rxd,      //GMII输入数据
  11.     input         gmii_tx_clk,   //GMII发送数据时钟    
  12.     output        gmii_tx_en,    //GMII输出数据有效信号
  13.     output [ 7:0] gmii_txd,      //GMII输出数据 
  14.     //用户接口
  15.     output        rec_pkt_done,  //以太网单包数据接收完成信号
  16.     output        rec_en,        //以太网接收的数据使能信号
  17.     output [31:0] rec_data,      //以太网接收的数据
  18.     output [15:0] rec_byte_num,  //以太网接收的有效字节数 单位:byte     
  19.     input         tx_start_en,   //以太网开始发送信号
  20.     input  [31:0] tx_data,       //以太网待发送数据  
  21.     input  [15:0] tx_byte_num,   //以太网发送的有效字节数 单位:byte  
  22.     input  [47:0] des_mac,       //发送的目标MAC地址
  23.     input  [31:0] des_ip,        //发送的目标IP地址    
  24.     output        tx_done,       //以太网发送完成信号
  25.     output        tx_req         //读数据请求信号    
  26. );
  27.  
  28.   //parameter define
  29.   //开发板MAC地址 00-11-22-33-44-55
  30.   parameter BOARD_MAC = 48'h00_11_22_33_44_55;
  31.   //开发板IP地址 192.168.1.10     
  32.   parameter BOARD_IP = {8'd192, 8'd168, 8'd1, 8'd10};
  33.   //目的MAC地址 ff_ff_ff_ff_ff_ff
  34.   parameter DES_MAC = 48'hff_ff_ff_ff_ff_ff;
  35.   //目的IP地址 192.168.1.102     
  36.   parameter DES_IP = {8'd192, 8'd168, 8'd1, 8'd102};
  37.  
  38.   //wire define
  39.   wire        crc_en;  //CRC开始校验使能
  40.   wire        crc_clr;  //CRC数据复位信号 
  41.   wire [ 7:0] crc_d8;  //输入待校验8位数据
  42.  
  43.   wire [31:0] crc_data;  //CRC校验数据
  44.   wire [31:0] crc_next;  //CRC下次校验完成数据
  45.  
  46.   //*****************************************************
  47.   //**                    main code
  48.   //*****************************************************
  49.  
  50.   assign crc_d8 = gmii_txd;
  51.  
  52.   //以太网接收模块    
  53.   udp_rx #(
  54.       .BOARD_MAC(BOARD_MAC),  //参数例化
  55.       .BOARD_IP (BOARD_IP)
  56.   ) u_udp_rx (
  57.       .clk         (gmii_rx_clk),
  58.       .rst_n       (rst_n),
  59.       .gmii_rx_dv  (gmii_rx_dv),
  60.       .gmii_rxd    (gmii_rxd),
  61.       .rec_pkt_done(rec_pkt_done),
  62.       .rec_en      (rec_en),
  63.       .rec_data    (rec_data),
  64.       .rec_byte_num(rec_byte_num)
  65.   );
  66.  
  67.   //以太网发送模块
  68.   udp_tx #(
  69.       .BOARD_MAC(BOARD_MAC),  //参数例化
  70.       .BOARD_IP (BOARD_IP),
  71.       .DES_MAC  (DES_MAC),
  72.       .DES_IP   (DES_IP)
  73.   ) u_udp_tx (
  74.       .clk        (gmii_tx_clk),
  75.       .rst_n      (rst_n),
  76.       .tx_start_en(tx_start_en),
  77.       .tx_data    (tx_data),
  78.       .tx_byte_num(tx_byte_num),
  79.       .des_mac    (des_mac),
  80.       .des_ip     (des_ip),
  81.       .crc_data   (crc_data),
  82.       .crc_next   (crc_next[31:24]),
  83.       .tx_done    (tx_done),
  84.       .tx_req     (tx_req),
  85.       .gmii_tx_en (gmii_tx_en),
  86.       .gmii_txd   (gmii_txd),
  87.       .crc_en     (crc_en),
  88.       .crc_clr    (crc_clr)
  89.   );
  90.  
  91.   //以太网发送CRC校验模块
  92.   crc32_d8 u_crc32_d8 (
  93.       .clk     (gmii_tx_clk),
  94.       .rst_n   (rst_n),
  95.       .data    (crc_d8),
  96.       .crc_en  (crc_en),
  97.       .crc_clr (crc_clr),
  98.       .crc_data(crc_data),
  99.       .crc_next(crc_next)
  100.   );
  101.  
  102. endmodule

3.10.1 以太网数据接收模块

  1. `timescale 1ns / 1ps
  2. //以太网数据接收模块
  3.  
  4.  
  5. module udp_rx (
  6.     input clk,   //时钟信号
  7.     input rst_n, //复位信号，低电平有效
  8.  
  9.     input             gmii_rx_dv,    //GMII输入数据有效信号
  10.     input      [ 7:0] gmii_rxd,      //GMII输入数据
  11.     output reg        rec_pkt_done,  //以太网单包数据接收完成信号
  12.     output reg        rec_en,        //以太网接收的数据使能信号
  13.     output reg [31:0] rec_data,      //以太网接收的数据
  14.     output reg [15:0] rec_byte_num   //以太网接收的有效字数 单位:byte     
  15. );
  16.  
  17.   //parameter define
  18.   //开发板MAC地址 00-11-22-33-44-55
  19.   parameter BOARD_MAC = 48'h00_11_22_33_44_55;
  20.   //开发板IP地址 192.168.1.10 
  21.   parameter BOARD_IP = {8'd192, 8'd168, 8'd1, 8'd10};
  23.   localparam st_idle = 7'b000_0001;  //初始状态，等待接收前导码
  24.   localparam st_preamble = 7'b000_0010;  //接收前导码状态 
  25.   localparam st_eth_head = 7'b000_0100;  //接收以太网帧头
  26.   localparam st_ip_head = 7'b000_1000;  //接收IP首部
  27.   localparam st_udp_head = 7'b001_0000;  //接收UDP首部
  28.   localparam st_rx_data = 7'b010_0000;  //接收有效数据
  29.   localparam st_rx_end = 7'b100_0000;  //接收结束
  30.  
  31.   localparam ETH_TYPE = 16'h0800;  //以太网协议类型 IP协议
  33.   //reg define
  34.   reg [ 6:0] cur_state;
  35.   reg [ 6:0] next_state;
  37.   reg        skip_en;  //控制状态跳转使能信号
  38.   reg        error_en;  //解析错误使能信号
  39.   reg [ 4:0] cnt;  //解析数据计数器
  40.   reg [47:0] des_mac;  //目的MAC地址
  41.   reg [15:0] eth_type;  //以太网类型
  42.   reg [31:0] des_ip;  //目的IP地址
  43.   reg [ 5:0] ip_head_byte_num;  //IP首部长度
  44.   reg [15:0] udp_byte_num;  //UDP长度
  45.   reg [15:0] data_byte_num;  //数据长度
  46.   reg [15:0] data_cnt;  //有效数据计数    
  47.   reg [ 1:0] rec_en_cnt;  //8bit转32bit计数器
  49.   //*****************************************************
  50.   //**                    main code
  51.   //*****************************************************
  53.   //(三段式状态机)同步时序描述状态转移
  54.   always @(posedge clk or negedge rst_n) begin
  55.     if (!rst_n) cur_state <= st_idle;
  56.     else cur_state <= next_state;
  57.   end
  59.   //组合逻辑判断状态转移条件
  60.   always @(*) begin
  61.     next_state = st_idle;
  62.     case (cur_state)
  63.       st_idle: begin  //等待接收前导码
  64.         if (skip_en) next_state = st_preamble;
  65.         else next_state = st_idle;
  66.       end
  67.       st_preamble: begin  //接收前导码
  68.         if (skip_en) next_state = st_eth_head;
  69.         else if (error_en) next_state = st_rx_end;
  70.         else next_state = st_preamble;
  71.       end
  72.       st_eth_head: begin  //接收以太网帧头
  73.         if (skip_en) next_state = st_ip_head;
  74.         else if (error_en) next_state = st_rx_end;
  75.         else next_state = st_eth_head;
  76.       end
  77.       st_ip_head: begin  //接收IP首部
  78.         if (skip_en) next_state = st_udp_head;
  79.         else if (error_en) next_state = st_rx_end;
  80.         else next_state = st_ip_head;
  81.       end
  82.       st_udp_head: begin  //接收UDP首部
  83.         if (skip_en) next_state = st_rx_data;
  84.         else next_state = st_udp_head;
  85.       end
  86.       st_rx_data: begin  //接收有效数据
  87.         if (skip_en) next_state = st_rx_end;
  88.         else next_state = st_rx_data;
  89.       end
  90.       st_rx_end: begin  //接收结束
  91.         if (skip_en) next_state = st_idle;
  92.         else next_state = st_rx_end;
  93.       end
  94.       default: next_state = st_idle;
  95.     endcase
  96.   end
  98.   //时序电路描述状态输出,解析以太网数据
  99.   always @(posedge clk or negedge rst_n) begin
  100.     if (!rst_n) begin
  101.       skip_en <= 1'b0;
  102.       error_en <= 1'b0;
  103.       cnt <= 5'd0;
  104.       des_mac <= 48'd0;
  105.       eth_type <= 16'd0;
  106.       des_ip <= 32'd0;
  107.       ip_head_byte_num <= 6'd0;
  108.       udp_byte_num <= 16'd0;
  109.       data_byte_num <= 16'd0;
  110.       data_cnt <= 16'd0;
  111.       rec_en_cnt <= 2'd0;
  112.       rec_en <= 1'b0;
  113.       rec_data <= 32'd0;
  114.       rec_pkt_done <= 1'b0;
  115.       rec_byte_num <= 16'd0;
  116.     end else begin
  117.       skip_en <= 1'b0;
  118.       error_en <= 1'b0;
  119.       rec_en <= 1'b0;
  120.       rec_pkt_done <= 1'b0;
  121.       case (next_state)
  122.         st_idle: begin
  123.           if ((gmii_rx_dv == 1'b1) && (gmii_rxd == 8'h55)) skip_en <= 1'b1;
  124.         end
  125.         st_preamble: begin
  126.           if (gmii_rx_dv) begin  //解析前导码
  127.             cnt <= cnt + 5'd1;
  128.             if ((cnt < 5'd6) && (gmii_rxd != 8'h55))  //7个8'h55  
  129.               error_en <= 1'b1;
  130.             else if (cnt == 5'd6) begin
  131.               cnt <= 5'd0;
  132.               if (gmii_rxd == 8'hd5)  //1个8'hd5
  133.                 skip_en <= 1'b1;
  134.               else error_en <= 1'b1;
  135.             end
  136.           end
  137.         end
  138.         st_eth_head: begin
  139.           if (gmii_rx_dv) begin
  140.             cnt <= cnt + 5'b1;
  141.             if (cnt < 5'd6) des_mac <= {des_mac[39:0], gmii_rxd};  //目的MAC地址
  142.             else if (cnt == 5'd12) eth_type[15:8] <= gmii_rxd;  //以太网协议类型
  143.             else if (cnt == 5'd13) begin
  144.               eth_type[7:0] <= gmii_rxd;
  145.               cnt <= 5'd0;
  146.               //判断MAC地址是否为开发板MAC地址或者公共地址
  147.               if(((des_mac == BOARD_MAC) ||(des_mac == 48'hff_ff_ff_ff_ff_ff))
  148.                        && eth_type[15:8] == ETH_TYPE[15:8] && gmii_rxd == ETH_TYPE[7:0])
  149.                 skip_en <= 1'b1;
  150.               else error_en <= 1'b1;
  151.             end
  152.           end
  153.         end
  154.         st_ip_head: begin
  155.           if (gmii_rx_dv) begin
  156.             cnt <= cnt + 5'd1;
  157.             if (cnt == 5'd0) ip_head_byte_num <= {gmii_rxd[3:0], 2'd0};
  158.             else if ((cnt >= 5'd16) && (cnt <= 5'd18))
  159.               des_ip <= {des_ip[23:0], gmii_rxd};  //目的IP地址
  160.             else if (cnt == 5'd19) begin
  161.               des_ip <= {des_ip[23:0], gmii_rxd};
  162.               //判断IP地址是否为开发板IP地址
  163.               if ((des_ip[23:0] == BOARD_IP[31:8]) && (gmii_rxd == BOARD_IP[7:0])) begin
  164.                 if (cnt == ip_head_byte_num - 1'b1) begin
  165.                   skip_en <= 1'b1;
  166.                   cnt <= 5'd0;
  167.                 end
  168.               end else begin
  169.                 //IP错误，停止解析数据                        
  170.                 error_en <= 1'b1;
  171.                 cnt <= 5'd0;
  172.               end
  173.             end else if (cnt == ip_head_byte_num - 1'b1) begin
  174.               skip_en <= 1'b1;  //IP首部解析完成
  175.               cnt     <= 5'd0;
  176.             end
  177.           end
  178.         end
  179.         st_udp_head: begin
  180.           if (gmii_rx_dv) begin
  181.             cnt <= cnt + 5'd1;
  182.             if (cnt == 5'd4) udp_byte_num[15:8] <= gmii_rxd;  //解析UDP字节长度 
  183.             else if (cnt == 5'd5) udp_byte_num[7:0] <= gmii_rxd;
  184.             else if (cnt == 5'd7) begin
  185.               //有效数据字节长度，（UDP首部8个字节，所以减去8）
  186.               data_byte_num <= udp_byte_num - 16'd8;
  187.               skip_en <= 1'b1;
  188.               cnt <= 5'd0;
  189.             end
  190.           end
  191.         end
  192.         st_rx_data: begin
  193.           //接收数据，转换成32bit            
  194.           if (gmii_rx_dv) begin
  195.             data_cnt   <= data_cnt + 16'd1;
  196.             rec_en_cnt <= rec_en_cnt + 2'd1;
  197.             if (data_cnt == data_byte_num - 16'd1) begin
  198.               skip_en      <= 1'b1;  //有效数据接收完成
  199.               data_cnt     <= 16'd0;
  200.               rec_en_cnt   <= 2'd0;
  201.               rec_pkt_done <= 1'b1;
  202.               rec_en       <= 1'b1;
  203.               rec_byte_num <= data_byte_num;
  204.             end
  205.             //先收到的数据放在了rec_data的高位,所以当数据不是4的倍数时,
  206.             //低位数据为无效数据，可根据有效字节数来判断(rec_byte_num)
  207.             if (rec_en_cnt == 2'd0) rec_data[31:24] <= gmii_rxd;
  208.             else if (rec_en_cnt == 2'd1) rec_data[23:16] <= gmii_rxd;
  209.             else if (rec_en_cnt == 2'd2) rec_data[15:8] <= gmii_rxd;
  210.             else if (rec_en_cnt == 2'd3) begin
  211.               rec_en <= 1'b1;
  212.               rec_data[7:0] <= gmii_rxd;
  213.             end
  214.           end
  215.         end
  216.         st_rx_end: begin  //单包数据接收完成   
  217.           if (gmii_rx_dv == 1'b0 && skip_en == 1'b0) skip_en <= 1'b1;
  218.         end
  219.         default: ;
  220.       endcase
  221.     end
  222.   end
  224. endmodule

3.10.2 以太网数据发送模块

  1. `timescale 1ns / 1ps
  2. //以太网数据发送模块
  3.  
  4.  
  5. module udp_tx (
  6.     input clk,   //时钟信号
  7.     input rst_n, //复位信号，低电平有效
  8.  
  9.     input             tx_start_en,  //以太网开始发送信号
  10.     input      [31:0] tx_data,      //以太网待发送数据  
  11.     input      [15:0] tx_byte_num,  //以太网发送的有效字节数
  12.     input      [47:0] des_mac,      //发送的目标MAC地址
  13.     input      [31:0] des_ip,       //发送的目标IP地址    
  14.     input      [31:0] crc_data,     //CRC校验数据
  15.     input      [ 7:0] crc_next,     //CRC下次校验完成数据
  16.     output reg        tx_done,      //以太网发送完成信号
  17.     output reg        tx_req,       //读数据请求信号
  18.     output reg        gmii_tx_en,   //GMII输出数据有效信号
  19.     output reg [ 7:0] gmii_txd,     //GMII输出数据
  20.     output reg        crc_en,       //CRC开始校验使能
  21.     output reg        crc_clr       //CRC数据复位信号 
  22. );
  23.  
  24.   //parameter define
  25.   //开发板MAC地址 00-11-22-33-44-55
  26.   parameter BOARD_MAC = 48'h00_11_22_33_44_55;
  27.   //开发板IP地址 192.168.1.123     
  28.   parameter BOARD_IP = {8'd192, 8'd168, 8'd1, 8'd123};
  29.   //目的MAC地址 ff_ff_ff_ff_ff_ff
  30.   parameter DES_MAC = 48'hff_ff_ff_ff_ff_ff;
  31.   //目的IP地址 192.168.1.102     
  32.   parameter DES_IP = {8'd192, 8'd168, 8'd1, 8'd102};
  33.  
  34.   localparam st_idle = 7'b000_0001;  //初始状态，等待开始发送信号
  35.   localparam st_check_sum = 7'b000_0010;  //IP首部校验和
  36.   localparam st_preamble = 7'b000_0100;  //发送前导码+帧起始界定符
  37.   localparam st_eth_head = 7'b000_1000;  //发送以太网帧头
  38.   localparam st_ip_head = 7'b001_0000;  //发送IP首部+UDP首部
  39.   localparam st_tx_data = 7'b010_0000;  //发送数据
  40.   localparam st_crc = 7'b100_0000;  //发送CRC校验值
  42.   localparam ETH_TYPE = 16'h0800;  //以太网协议类型 IP协议
  43.   //以太网数据最小46个字节，IP首部20个字节+UDP首部8个字节
  44.   //所以数据至少46-20-8=18个字节
  45.   localparam MIN_DATA_NUM = 16'd18;
  47.   //reg define
  48.   reg [6:0] cur_state;
  49.   reg [6:0] next_state;
  51.   reg [7:0] preamble[7:0];  //前导码
  52.   reg [7:0] eth_head[13:0];  //以太网首部
  53.   reg [31:0] ip_head[6:0];  //IP首部 + UDP首部
  55.   reg start_en_d0;
  56.   reg start_en_d1;
  57.   reg [15:0] tx_data_num;  //发送的有效数据字节个数
  58.   reg [15:0] total_num;  //总字节数
  59.   reg trig_tx_en;
  60.   reg [15:0] udp_num;  //UDP字节数
  61.   reg skip_en;  //控制状态跳转使能信号
  62.   reg [4:0] cnt;
  63.   reg [31:0] check_buffer;  //首部校验和
  64.   reg [1:0] tx_bit_sel;
  65.   reg [15:0] data_cnt;  //发送数据个数计数器
  66.   reg tx_done_t;
  67.   reg [4:0] real_add_cnt;  //以太网数据实际多发的字节数
  69.   //wire define                       
  70.   wire pos_start_en;  //开始发送数据上升沿
  71.   wire [15:0] real_tx_data_num;  //实际发送的字节数(以太网最少字节要求)
  72.   //*****************************************************
  73.   //**                    main code
  74.   //*****************************************************
  76.   assign pos_start_en = (~start_en_d1) & start_en_d0;
  77.   assign real_tx_data_num = (tx_data_num >= MIN_DATA_NUM) ? tx_data_num : MIN_DATA_NUM;
  79.   //采tx_start_en的上升沿
  80.   always @(posedge clk or negedge rst_n) begin
  81.     if (!rst_n) begin
  82.       start_en_d0 <= 1'b0;
  83.       start_en_d1 <= 1'b0;
  84.     end else begin
  85.       start_en_d0 <= tx_start_en;
  86.       start_en_d1 <= start_en_d0;
  87.     end
  88.   end
  90.   //寄存数据有效字节
  91.   always @(posedge clk or negedge rst_n) begin
  92.     if (!rst_n) begin
  93.       tx_data_num <= 16'd0;
  94.       total_num <= 16'd0;
  95.       udp_num <= 16'd0;
  96.     end else begin
  97.       if (pos_start_en && cur_state == st_idle) begin
  98.         //数据长度
  99.         tx_data_num <= tx_byte_num;
  100.         //IP长度：有效数据+IP首部长度            
  101.         total_num <= tx_byte_num + 16'd28;
  102.         //UDP长度：有效数据+UDP首部长度            
  103.         udp_num <= tx_byte_num + 16'd8;
  104.       end
  105.     end
  106.   end
  107.  
  108.   //触发发送信号
  109.   always @(posedge clk or negedge rst_n) begin
  110.     if (!rst_n) trig_tx_en <= 1'b0;
  111.     else trig_tx_en <= pos_start_en;
  113.   end
  115.   always @(posedge clk or negedge rst_n) begin
  116.     if (!rst_n) cur_state <= st_idle;
  117.     else cur_state <= next_state;
  118.   end
  120.   always @(*) begin
  121.     next_state = st_idle;
  122.     case (cur_state)
  123.       st_idle: begin  //等待发送数据
  124.         if (skip_en) next_state = st_check_sum;
  125.         else next_state = st_idle;
  126.       end
  127.       st_check_sum: begin  //IP首部校验
  128.         if (skip_en) next_state = st_preamble;
  129.         else next_state = st_check_sum;
  130.       end
  131.       st_preamble: begin  //发送前导码+帧起始界定符
  132.         if (skip_en) next_state = st_eth_head;
  133.         else next_state = st_preamble;
  134.       end
  135.       st_eth_head: begin  //发送以太网首部
  136.         if (skip_en) next_state = st_ip_head;
  137.         else next_state = st_eth_head;
  138.       end
  139.       st_ip_head: begin  //发送IP首部+UDP首部               
  140.         if (skip_en) next_state = st_tx_data;
  141.         else next_state = st_ip_head;
  142.       end
  143.       st_tx_data: begin  //发送数据                  
  144.         if (skip_en) next_state = st_crc;
  145.         else next_state = st_tx_data;
  146.       end
  147.       st_crc: begin  //发送CRC校验值
  148.         if (skip_en) next_state = st_idle;
  149.         else next_state = st_crc;
  150.       end
  151.       default: next_state = st_idle;
  152.     endcase
  153.   end
  155.   //发送数据
  156.   always @(posedge clk or negedge rst_n) begin
  157.     if (!rst_n) begin
  158.       skip_en <= 1'b0;
  159.       cnt <= 5'd0;
  160.       check_buffer <= 32'd0;
  161.       ip_head[1][31:16] <= 16'd0;
  162.       tx_bit_sel <= 2'b0;
  163.       crc_en <= 1'b0;
  164.       gmii_tx_en <= 1'b0;
  165.       gmii_txd <= 8'd0;
  166.       tx_req <= 1'b0;
  167.       tx_done_t <= 1'b0;
  168.       data_cnt <= 16'd0;
  169.       real_add_cnt <= 5'd0;
  170.       //初始化数组    
  171.       //前导码 7个8'h55 + 1个8'hd5
  172.       preamble[0] <= 8'h55;
  173.       preamble[1] <= 8'h55;
  174.       preamble[2] <= 8'h55;
  175.       preamble[3] <= 8'h55;
  176.       preamble[4] <= 8'h55;
  177.       preamble[5] <= 8'h55;
  178.       preamble[6] <= 8'h55;
  179.       preamble[7] <= 8'hd5;
  180.       //目的MAC地址
  181.       eth_head[0] <= DES_MAC[47:40];
  182.       eth_head[1] <= DES_MAC[39:32];
  183.       eth_head[2] <= DES_MAC[31:24];
  184.       eth_head[3] <= DES_MAC[23:16];
  185.       eth_head[4] <= DES_MAC[15:8];
  186.       eth_head[5] <= DES_MAC[7:0];
  187.       //源MAC地址
  188.       eth_head[6] <= BOARD_MAC[47:40];
  189.       eth_head[7] <= BOARD_MAC[39:32];
  190.       eth_head[8] <= BOARD_MAC[31:24];
  191.       eth_head[9] <= BOARD_MAC[23:16];
  192.       eth_head[10] <= BOARD_MAC[15:8];
  193.       eth_head[11] <= BOARD_MAC[7:0];
  194.       //以太网类型
  195.       eth_head[12] <= ETH_TYPE[15:8];
  196.       eth_head[13] <= ETH_TYPE[7:0];
  197.     end else begin
  198.       skip_en <= 1'b0;
  199.       tx_req <= 1'b0;
  200.       crc_en <= 1'b0;
  201.       gmii_tx_en <= 1'b0;
  202.       tx_done_t <= 1'b0;
  203.       case (next_state)
  204.         st_idle: begin
  205.           if (trig_tx_en) begin
  206.             skip_en <= 1'b1;
  207.             //版本号：4 首部长度：5(单位:32bit,20byte/4=5)
  208.             ip_head[0] <= {8'h45, 8'h00, total_num};
  209.             //16位标识，每次发送累加1      
  210.             ip_head[1][31:16] <= ip_head[1][31:16] + 1'b1;
  211.             //bit[15:13]: 010表示不分片
  212.             ip_head[1][15:0] <= 16'h4000;
  213.             //协议：17(udp)                  
  214.             ip_head[2] <= {8'h40, 8'd17, 16'h0};
  215.             //源IP地址               
  216.             ip_head[3] <= BOARD_IP;
  217.             //目的IP地址    
  218.             if (des_ip != 32'd0) ip_head[4] <= des_ip;
  219.             else ip_head[4] <= DES_IP;
  220.             //16位源端口号：1234  16位目的端口号：1234                      
  221.             ip_head[5] <= {16'd1234, 16'd1234};
  222.             //16位udp长度，16位udp校验和              
  223.             ip_head[6] <= {udp_num, 16'h0000};
  224.             //更新MAC地址
  225.             if (des_mac != 48'b0) begin
  226.               //目的MAC地址
  227.               eth_head[0] <= des_mac[47:40];
  228.               eth_head[1] <= des_mac[39:32];
  229.               eth_head[2] <= des_mac[31:24];
  230.               eth_head[3] <= des_mac[23:16];
  231.               eth_head[4] <= des_mac[15:8];
  232.               eth_head[5] <= des_mac[7:0];
  233.             end
  234.           end
  235.         end
  236.         st_check_sum: begin  //IP首部校验
  237.           cnt <= cnt + 5'd1;
  238.           if (cnt == 5'd0) begin
  239.             check_buffer <= ip_head[0][31:16] + ip_head[0][15:0]
  240.                                     + ip_head[1][31:16] + ip_head[1][15:0]
  241.                                     + ip_head[2][31:16] + ip_head[2][15:0]
  242.                                     + ip_head[3][31:16] + ip_head[3][15:0]
  243.                                     + ip_head[4][31:16] + ip_head[4][15:0];
  244.           end else if (cnt == 5'd1)  //可能出现进位,累加一次
  245.             check_buffer <= check_buffer[31:16] + check_buffer[15:0];
  246.           else if (cnt == 5'd2) begin  //可能再次出现进位,累加一次
  247.             check_buffer <= check_buffer[31:16] + check_buffer[15:0];
  248.           end else if (cnt == 5'd3) begin  //按位取反 
  249.             skip_en <= 1'b1;
  250.             cnt <= 5'd0;
  251.             ip_head[2][15:0] <= ~check_buffer[15:0];
  252.           end
  253.         end
  254.         st_preamble: begin  //发送前导码+帧起始界定符
  255.           gmii_tx_en <= 1'b1;
  256.           gmii_txd   <= preamble[cnt];
  257.           if (cnt == 5'd7) begin
  258.             skip_en <= 1'b1;
  259.             cnt <= 5'd0;
  260.           end else cnt <= cnt + 5'd1;
  261.         end
  262.         st_eth_head: begin  //发送以太网首部
  263.           gmii_tx_en <= 1'b1;
  264.           crc_en <= 1'b1;
  265.           gmii_txd <= eth_head[cnt];
  266.           if (cnt == 5'd13) begin
  267.             skip_en <= 1'b1;
  268.             cnt <= 5'd0;
  269.           end else cnt <= cnt + 5'd1;
  270.         end
  271.         st_ip_head: begin  //发送IP首部 + UDP首部
  272.           crc_en <= 1'b1;
  273.           gmii_tx_en <= 1'b1;
  274.           tx_bit_sel <= tx_bit_sel + 2'd1;
  275.           if (tx_bit_sel == 3'd0) gmii_txd <= ip_head[cnt][31:24];
  276.           else if (tx_bit_sel == 3'd1) gmii_txd <= ip_head[cnt][23:16];
  277.           else if (tx_bit_sel == 3'd2) begin
  278.             gmii_txd <= ip_head[cnt][15:8];
  279.             if (cnt == 5'd6) begin
  280.               //提前读请求数据，等待数据有效时发送
  281.               tx_req <= 1'b1;
  282.             end
  283.           end else if (tx_bit_sel == 3'd3) begin
  284.             gmii_txd <= ip_head[cnt][7:0];
  285.             if (cnt == 5'd6) begin
  286.               skip_en <= 1'b1;
  287.               cnt <= 5'd0;
  288.             end else cnt <= cnt + 5'd1;
  289.           end
  290.         end
  291.         st_tx_data: begin  //发送数据
  292.           crc_en <= 1'b1;
  293.           gmii_tx_en <= 1'b1;
  294.           tx_bit_sel <= tx_bit_sel + 3'd1;
  295.           if (data_cnt < tx_data_num - 16'd1) data_cnt <= data_cnt + 16'd1;
  296.           else if (data_cnt == tx_data_num - 16'd1) begin
  297.             //如果发送的有效数据少于18个字节，在后面填补充位
  298.             //补充的值为最后一次发送的有效数据
  299.             gmii_txd <= 8'd0;
  300.             if (data_cnt + real_add_cnt < real_tx_data_num - 16'd1)
  301.               real_add_cnt <= real_add_cnt + 5'd1;
  302.             else begin
  303.               skip_en <= 1'b1;
  304.               data_cnt <= 16'd0;
  305.               real_add_cnt <= 5'd0;
  306.               tx_bit_sel <= 3'd0;
  307.             end
  308.           end
  309.           if (tx_bit_sel == 1'b0) gmii_txd <= tx_data[31:24];
  310.           else if (tx_bit_sel == 3'd1) gmii_txd <= tx_data[23:16];
  311.           else if (tx_bit_sel == 3'd2) begin
  312.             gmii_txd <= tx_data[15:8];
  313.             if (data_cnt != tx_data_num - 16'd1) tx_req <= 1'b1;
  314.           end else if (tx_bit_sel == 3'd3) gmii_txd <= tx_data[7:0];
  315.         end
  316.         st_crc: begin  //发送CRC校验值
  317.           gmii_tx_en <= 1'b1;
  318.           tx_bit_sel <= tx_bit_sel + 3'd1;
  319.           if (tx_bit_sel == 3'd0)
  320.             gmii_txd <= {
  321.               ~crc_next[0],
  322.               ~crc_next[1],
  323.               ~crc_next[2],
  324.               ~crc_next[3],
  325.               ~crc_next[4],
  326.               ~crc_next[5],
  327.               ~crc_next[6],
  328.               ~crc_next[7]
  329.             };
  330.           else if (tx_bit_sel == 3'd1)
  331.             gmii_txd <= {
  332.               ~crc_data[16],
  333.               ~crc_data[17],
  334.               ~crc_data[18],
  335.               ~crc_data[19],
  336.               ~crc_data[20],
  337.               ~crc_data[21],
  338.               ~crc_data[22],
  339.               ~crc_data[23]
  340.             };
  341.           else if (tx_bit_sel == 3'd2) begin
  342.             gmii_txd <= {
  343.               ~crc_data[8],
  344.               ~crc_data[9],
  345.               ~crc_data[10],
  346.               ~crc_data[11],
  347.               ~crc_data[12],
  348.               ~crc_data[13],
  349.               ~crc_data[14],
  350.               ~crc_data[15]
  351.             };
  352.           end else if (tx_bit_sel == 3'd3) begin
  353.             gmii_txd <= {
  354.               ~crc_data[0],
  355.               ~crc_data[1],
  356.               ~crc_data[2],
  357.               ~crc_data[3],
  358.               ~crc_data[4],
  359.               ~crc_data[5],
  360.               ~crc_data[6],
  361.               ~crc_data[7]
  362.             };
  363.             tx_done_t <= 1'b1;
  364.             skip_en <= 1'b1;
  365.           end
  366.         end
  367.         default: ;
  368.       endcase
  369.     end
  370.   end
  372.   //发送完成信号及crc值复位信号
  373.   always @(posedge clk or negedge rst_n) begin
  374.     if (!rst_n) begin
  375.       tx_done <= 1'b0;
  376.       crc_clr <= 1'b0;
  377.     end else begin
  378.       tx_done <= tx_done_t;
  379.       crc_clr <= tx_done_t;
  380.     end
  381.   end
  383. endmodule

3.10.3 CRC32校验模块

  1. `timescale 1ns / 1ps
  2. //CRC32校验模块
  3.  
  4.  
  5. module crc32_d8 (
  6.     input             clk,       //时钟信号
  7.     input             rst_n,     //复位信号，低电平有效
  8.     input      [ 7:0] data,      //输入待校验8位数据
  9.     input             crc_en,    //crc使能，开始校验标志
  10.     input             crc_clr,   //crc数据复位信号            
  11.     output reg [31:0] crc_data,  //CRC校验数据
  12.     output     [31:0] crc_next   //CRC下次校验完成数据
  13. );
  14.  
  15.   //*****************************************************
  16.   //**                    main code
  17.   //*****************************************************
  18.  
  19.   //输入待校验8位数据,需要先将高低位互换
  20.   wire [7:0] data_t;
  21.  
  22.   assign data_t = {data[0], data[1], data[2], data[3], data[4], data[5], data[6], data[7]};
  23.  
  24.   //CRC32的生成多项式为：G(x)= x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 
  25.   //+ x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
  26.  
  27.   assign crc_next[0] = crc_data[24] ^ crc_data[30] ^ data_t[0] ^ data_t[6];
  28.   assign crc_next[1] = crc_data[24] ^ crc_data[25] ^ crc_data[30] ^ crc_data[31] 
  29.                      ^ data_t[0] ^ data_t[1] ^ data_t[6] ^ data_t[7];
  30.   assign crc_next[2] = crc_data[24] ^ crc_data[25] ^ crc_data[26] ^ crc_data[30] 
  31.                      ^ crc_data[31] ^ data_t[0] ^ data_t[1] ^ data_t[2] ^ data_t[6] 
  32.                      ^ data_t[7];
  33.   assign crc_next[3] = crc_data[25] ^ crc_data[26] ^ crc_data[27] ^ crc_data[31] 
  34.                      ^ data_t[1] ^ data_t[2] ^ data_t[3] ^ data_t[7];
  35.   assign crc_next[4] = crc_data[24] ^ crc_data[26] ^ crc_data[27] ^ crc_data[28] 
  36.                      ^ crc_data[30] ^ data_t[0] ^ data_t[2] ^ data_t[3] ^ data_t[4] 
  37.                      ^ data_t[6];
  38.   assign crc_next[5] = crc_data[24] ^ crc_data[25] ^ crc_data[27] ^ crc_data[28] 
  39.                      ^ crc_data[29] ^ crc_data[30] ^ crc_data[31] ^ data_t[0] 
  40.                      ^ data_t[1] ^ data_t[3] ^ data_t[4] ^ data_t[5] ^ data_t[6] 
  41.                      ^ data_t[7];
  42.   assign crc_next[6] = crc_data[25] ^ crc_data[26] ^ crc_data[28] ^ crc_data[29] 
  43.                      ^ crc_data[30] ^ crc_data[31] ^ data_t[1] ^ data_t[2] ^ data_t[4] 
  44.                      ^ data_t[5] ^ data_t[6] ^ data_t[7];
  45.   assign crc_next[7] = crc_data[24] ^ crc_data[26] ^ crc_data[27] ^ crc_data[29] 
  46.                      ^ crc_data[31] ^ data_t[0] ^ data_t[2] ^ data_t[3] ^ data_t[5] 
  47.                      ^ data_t[7];
  48.   assign crc_next[8] = crc_data[0] ^ crc_data[24] ^ crc_data[25] ^ crc_data[27] 
  49.                      ^ crc_data[28] ^ data_t[0] ^ data_t[1] ^ data_t[3] ^ data_t[4];
  50.   assign crc_next[9] = crc_data[1] ^ crc_data[25] ^ crc_data[26] ^ crc_data[28] 
  51.                      ^ crc_data[29] ^ data_t[1] ^ data_t[2] ^ data_t[4] ^ data_t[5];
  52.   assign crc_next[10] = crc_data[2] ^ crc_data[24] ^ crc_data[26] ^ crc_data[27] 
  53.                      ^ crc_data[29] ^ data_t[0] ^ data_t[2] ^ data_t[3] ^ data_t[5];
  54.   assign crc_next[11] = crc_data[3] ^ crc_data[24] ^ crc_data[25] ^ crc_data[27] 
  55.                      ^ crc_data[28] ^ data_t[0] ^ data_t[1] ^ data_t[3] ^ data_t[4];
  56.   assign crc_next[12] = crc_data[4] ^ crc_data[24] ^ crc_data[25] ^ crc_data[26] 
  57.                      ^ crc_data[28] ^ crc_data[29] ^ crc_data[30] ^ data_t[0] 
  58.                      ^ data_t[1] ^ data_t[2] ^ data_t[4] ^ data_t[5] ^ data_t[6];
  59.   assign crc_next[13] = crc_data[5] ^ crc_data[25] ^ crc_data[26] ^ crc_data[27] 
  60.                      ^ crc_data[29] ^ crc_data[30] ^ crc_data[31] ^ data_t[1] 
  61.                      ^ data_t[2] ^ data_t[3] ^ data_t[5] ^ data_t[6] ^ data_t[7];
  62.   assign crc_next[14] = crc_data[6] ^ crc_data[26] ^ crc_data[27] ^ crc_data[28] 
  63.                      ^ crc_data[30] ^ crc_data[31] ^ data_t[2] ^ data_t[3] ^ data_t[4]
  64.                      ^ data_t[6] ^ data_t[7];
  65.   assign crc_next[15] =  crc_data[7] ^ crc_data[27] ^ crc_data[28] ^ crc_data[29]
  66.                      ^ crc_data[31] ^ data_t[3] ^ data_t[4] ^ data_t[5] ^ data_t[7];
  67.   assign crc_next[16] = crc_data[8] ^ crc_data[24] ^ crc_data[28] ^ crc_data[29] 
  68.                      ^ data_t[0] ^ data_t[4] ^ data_t[5];
  69.   assign crc_next[17] = crc_data[9] ^ crc_data[25] ^ crc_data[29] ^ crc_data[30] 
  70.                      ^ data_t[1] ^ data_t[5] ^ data_t[6];
  71.   assign crc_next[18] = crc_data[10] ^ crc_data[26] ^ crc_data[30] ^ crc_data[31] 
  72.                      ^ data_t[2] ^ data_t[6] ^ data_t[7];
  73.   assign crc_next[19] = crc_data[11] ^ crc_data[27] ^ crc_data[31] ^ data_t[3] ^ data_t[7];
  74.   assign crc_next[20] = crc_data[12] ^ crc_data[28] ^ data_t[4];
  75.   assign crc_next[21] = crc_data[13] ^ crc_data[29] ^ data_t[5];
  76.   assign crc_next[22] = crc_data[14] ^ crc_data[24] ^ data_t[0];
  77.   assign crc_next[23] = crc_data[15] ^ crc_data[24] ^ crc_data[25] ^ crc_data[30] 
  78.                       ^ data_t[0] ^ data_t[1] ^ data_t[6];
  79.   assign crc_next[24] = crc_data[16] ^ crc_data[25] ^ crc_data[26] ^ crc_data[31] 
  80.                       ^ data_t[1] ^ data_t[2] ^ data_t[7];
  81.   assign crc_next[25] = crc_data[17] ^ crc_data[26] ^ crc_data[27] ^ data_t[2] ^ data_t[3];
  82.   assign crc_next[26] = crc_data[18] ^ crc_data[24] ^ crc_data[27] ^ crc_data[28] 
  83.                       ^ crc_data[30] ^ data_t[0] ^ data_t[3] ^ data_t[4] ^ data_t[6];
  84.   assign crc_next[27] = crc_data[19] ^ crc_data[25] ^ crc_data[28] ^ crc_data[29] 
  85.                       ^ crc_data[31] ^ data_t[1] ^ data_t[4] ^ data_t[5] ^ data_t[7];
  86.   assign crc_next[28] = crc_data[20] ^ crc_data[26] ^ crc_data[29] ^ crc_data[30] 
  87.                       ^ data_t[2] ^ data_t[5] ^ data_t[6];
  88.   assign crc_next[29] = crc_data[21] ^ crc_data[27] ^ crc_data[30] ^ crc_data[31] 
  89.                       ^ data_t[3] ^ data_t[6] ^ data_t[7];
  90.   assign crc_next[30] = crc_data[22] ^ crc_data[28] ^ crc_data[31] ^ data_t[4] ^ data_t[7];
  91.   assign crc_next[31] = crc_data[23] ^ crc_data[29] ^ data_t[5];
  92.  
  93.   always @(posedge clk or negedge rst_n) begin
  94.     if (!rst_n) crc_data <= 32'hff_ff_ff_ff;
  95.     else if (crc_clr)  //CRC校验值复位
  96.       crc_data <= 32'hff_ff_ff_ff;
  97.     else if (crc_en) crc_data <= crc_next;
  98.   end
  99.  
  100. endmodule

3.11 以太网控制模块

  1. `timescale 1ns / 1ps
  2. //以太网控制模块
  3.  
  4.  
  5. module eth_ctrl (
  6.     input        clk,             //系统时钟
  7.     input        rst_n,           //系统复位信号，低电平有效 
  8.     //ARP相关端口信号                                  
  9.     input        arp_rx_done,     //ARP接收完成信号
  10.     input        arp_rx_type,     //ARP接收类型 0:请求  1:应答
  11.     output       arp_tx_en,       //ARP发送使能信号
  12.     output       arp_tx_type,     //ARP发送类型 0:请求  1:应答
  13.     input        arp_tx_done,     //ARP发送完成信号
  14.     input        arp_gmii_tx_en,  //ARP GMII输出数据有效信号 
  15.     input  [7:0] arp_gmii_txd,    //ARP GMII输出数据
  16.     //UDP相关端口信号
  17.     input        udp_gmii_tx_en,  //UDP GMII输出数据有效信号  
  18.     input  [7:0] udp_gmii_txd,    //UDP GMII输出数据   
  19.     //GMII发送引脚
  20.     output       gmii_tx_en,      //GMII输出数据有效信号 
  21.     output [7:0] gmii_txd         //UDP GMII输出数据 
  22. );
  23.  
  24.   //reg define
  25.   reg protocol_sw;  //协议切换信号
  26.  
  27.   //*****************************************************
  28.   //**                    main code
  29.   //*****************************************************
  30.  
  31.   assign arp_tx_en = arp_rx_done && (arp_rx_type == 1'b0);
  32.   assign arp_tx_type = 1'b1;  //ARP发送类型固定为ARP应答                                   
  33.   assign gmii_tx_en = protocol_sw ? udp_gmii_tx_en : arp_gmii_tx_en;
  34.   assign gmii_txd = protocol_sw ? udp_gmii_txd : arp_gmii_txd;
  35.  
  36.   //根据ARP发送使能/完成信号,切换GMII引脚
  37.   always @(posedge clk or negedge rst_n) begin
  38.     if (!rst_n) protocol_sw <= 1'b1;
  39.     else if (arp_tx_en) protocol_sw <= 1'b0;
  40.     else if (arp_tx_done) protocol_sw <= 1'b1;
  41.   end
  43. endmodule

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