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基于FPGA的updata大综合设计_flash擦除仿真结果

作者：weixin_40725706 | 2024-06-05 12:29:32

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flash擦除仿真结果

1.原理图，这次的协议是7*55/d5/aa（擦出flash）55（在flash中写入数据）。因此frame的控制模块至关重要。

2.仿真结果

   这是仿真的frame控制模过滤协议之后产生的擦除地址与标志位，图中可以看出能够产生。

    这是flash的擦除模块，这是flash模块中的扇区自动加一，这次擦除了8个扇区。

     这是擦除完成的标志位，回传55表示擦除完成。

        这是仿真在协议模块中过滤协议之后，产生写的地址、写地址标志位、写数据以及写数据的标志位。

          通过观察flash的写控制模块可以发现flash可以写入相应的数据。

    通过观察uart的tx模块端，结束标志位产生后，可以回传aa（16进制）

3.这次大综合需要用到的模块uart的rx模块和tx模块、flash的擦除模块和写入模块、按键消抖和icapIP核模块以及利用top模块将所有模块综合。

  1. module rx_crtl(
  2.  
  3. 		input wire sclk,
  4. 		input wire rst_n,
  5. 		input wire rx_in,
  6. 		
  7. 		output reg stop_flag,   //新增数据监测停止位
  8. 		output reg flag_o,
  9. 		output reg [7:0] data_o
  10. );
  11.  
  12. reg [12:0] cnt;
  13. reg [3:0]  bit_cnt;
  14. reg rx_in_1,rx_in_2;
  15. reg rx_en;     //使能信号值有问题
  16. reg bit_flag;
  17. reg [7:0]tmp_data;
  18. reg tmp_flag;
  19.  
  20. reg [16:0] cnt_clean;
  21.  
  22. parameter CNT_CLEAN=100000;//28888; 仿真多写1个4
  23. parameter	CNT=5207;
  24. parameter   BIT_CNT=8;
  25. parameter   bit_flag_cnt=2603;  //	产生bit采集标志位
  26. //parameter   clean_flag=2610;
  27.  
  28.  
  29. always@(posedge sclk or negedge rst_n)   //ram输入信号清零计数器
  30. 		if(!rst_n)
  31. 		cnt_clean<=16'd0;
  32. 		else if(flag_o==1'b1)			//  少写了清零条件，导致写地址一直处于清零状态
  33. 				cnt_clean<=16'd0;		
  34. 		else if(cnt_clean==CNT_CLEAN)
  35. 					cnt_clean<=cnt_clean;	// 优先级,当时产生清零标志位没有保持，而是清零导致产生无数个终端位
  36. 		else if(flag_o==1'b0)  		 	//flag_o==1'b1，当时想的就是拉高开始计数，结果发现根本不计数
  37. 			cnt_clean<=cnt_clean+1'b1;	//因为标志位拉高只有一个时钟周期，应该记拉低的时钟周期。
  38. 			
  39.  
  40. always@(posedge sclk or negedge rst_n)  //数据清零位传递给帧协议
  41. 		if(!rst_n)
  42. 		stop_flag<=1'b0;
  43. 		else if (cnt_clean==CNT_CLEAN-1)
  44. 				stop_flag<=1'b1;
  45. 		else 	stop_flag<=1'b0;
  47. always@(posedge sclk or negedge rst_n)
  48. 		if(!rst_n)
  49. 			rx_in_1<=1'b1;
  50. 		else rx_in_1<=rx_in;
  51. always@(posedge sclk or negedge rst_n)  //输入信号延时
  52. 		if(!rst_n)
  53. 			rx_in_2<=1'b1;
  54. 		else rx_in_2<=rx_in_1;
  56. always@(posedge sclk or negedge rst_n)   //产生计数使能信号
  57. 		if(!rst_n)
  58. 			rx_en<=1'b0;
  59. 		else if(rx_in_1==1'b0&&rx_in_2==1'b1)
  60. 			rx_en<=1'b1;
  61. 			else if(bit_cnt==BIT_CNT&&cnt==CNT)
  62. 			 rx_en<=1'b0;
  63. 			 
  64. always@(posedge sclk or negedge rst_n)
  65. 		if(!rst_n)	
  66. 			cnt<=13'd0;
  67. 			else if(rx_en==1'b0)
  68. 				  cnt<=13'd0;
  69. 				  else if(cnt==CNT)
  70. 						cnt<=13'd0;
  71. 				  	else if(rx_en==1'b1)
  72. 				  			cnt<=cnt+1'b1;
  73. 				 
  74. always@(posedge sclk or negedge rst_n)   //位宽计数
  75. 		if(!rst_n)	
  76. 			bit_cnt<=4'd0;
  77. 				else if(rx_en==1'b0)	
  78. 					bit_cnt<=4'd0;
  79. 				else if(bit_cnt==BIT_CNT&&cnt==CNT)	
  80. 					bit_cnt<=4'd0;	
  81. 					else if(cnt==CNT)
  82. 						bit_cnt<=bit_cnt+1'b1;
  84. always@(posedge sclk or negedge rst_n)   //产生bit标志位
  85. 		if(!rst_n)
  86. 			bit_flag<=1'b0;
  87. 			else if(cnt==bit_flag_cnt)	
  88. 				bit_flag<=1'b1;
  89. 				else bit_flag<=1'b0;	
  90.  
  91. always@(posedge sclk or negedge rst_n)   //数据拼接
  92. 		if(!rst_n)	
  93. 			tmp_data<=8'd0;
  94. 		else if(bit_flag==1'b1&&bit_cnt>=4'd1&&bit_cnt<=4'd8)
  95. 				tmp_data<={rx_in_2,tmp_data[7:1]}; 		//少写分号
  96. 														//else if(bit_cnt==BIT_CNT&&cnt==clean_flag)  数据不清零条件
  97. 														//		tmp_data<=8'd0;
  99. always@(posedge sclk or negedge rst_n)   //数据拼接完成标志
  100. 		if(!rst_n)	
  101. 		 tmp_flag<=1'b0;
  102. 		 else if(bit_flag==1'b1&&bit_cnt==BIT_CNT)
  103. 		 	tmp_flag<=1'b1;
  104. 		 	else tmp_flag<=1'b0;
  106. always@(posedge sclk or negedge rst_n)
  107. 		if(!rst_n)	
  108. 			data_o<=8'd0;
  109. 		else if(tmp_flag==1'b1)
  110. 			data_o<=tmp_data;
  112. always@(posedge sclk or negedge rst_n)
  113. 		if(!rst_n)			
  114. 			flag_o<=1'b0;
  115. 			else flag_o<=tmp_flag;	 
  116. endmodule

 

  1. module	w_farme(
  2. 		
  3. 		input wire 			sclk,
  4. 		input wire 			rst_n,
  5. 		input wire 			flag_uart,
  6. 		input wire 	[7:0] 	data_uart,
  7. 		input wire 			stop_flag,		//数据发送完成标志
  8. 		input wire			sen_stop_flag,  //擦除完成标识
  9. 		
  10. 		output reg 			wr_flag,		
  11. 		output reg 	[23:0]	wr_addr,
  12. 		output reg	[7:0]	wr_data,
  13. 		output	reg			wr_flag_dizhi,
  14. 		
  15. 		output	reg	[23:0]	se_addr,
  16. 		output	reg			se_flag,
  17. 		
  18. 		output	reg			tx_flag,
  19. 		output	reg	[7:0]	tx_data		//擦除结束用55标志，发生完成用aa标识
  20.  
  21. );
  22.  
  23. reg [10:0] 	state;
  24. parameter IDLE		=11'b00000_0000_01;
  25. parameter H_1_55	=11'b00000_0000_10;
  26. parameter H_2_55	=11'b00000_0001_00;
  27. parameter H_3_55	=11'b00000_0010_00;
  28. parameter H_4_55	=11'b00000_0100_00;
  29. parameter H_5_55	=11'b00000_1000_00;
  30. parameter H_6_55	=11'b00001_0000_00;
  31. parameter H_7_55	=11'b00010_0000_00;
  32. parameter H_d5		=11'b00100_0000_00;
  33. parameter H_se		=11'b01000_0000_00;
  34. parameter H_wr		=11'b10000_0000_00;
  36. reg		[2:0]		cnt_flag;
  37. reg		[23:0]		tmp_addr;
  39. reg		[2:0]		cnt_flag_wr;
  40. reg		[23:0]		tmp_addr_wr;
  42. reg					flag_uart_dely;
  43. reg					flag_uart_dely1;
  44. always@(posedge sclk or negedge rst_n)
  45. 		if(!rst_n)
  46. 			state<=IDLE;
  47. 		//else if(stop_flag==1'b1)
  48. 		//		state<=idle;
  49. 		 else if(flag_uart==1'b1)
  50. 		 			case(state)
  51. 		 			IDLE  :  if(data_uart==8'h55)
  52. 		 						state<=H_1_55;
  53. 		 						else state<=IDLE;
  54. 		 			H_1_55:	 if(data_uart==8'h55)
  55. 		 						state<=H_2_55;
  56. 		 						else state<=IDLE;
  57. 		 			H_2_55:	 if(data_uart==8'h55)
  58. 		 						state<=H_3_55;
  59. 		 						else state<=IDLE;
  60. 		 			H_3_55:	 if(data_uart==8'h55)
  61. 		 						state<=H_4_55;
  62. 		 						else state<=IDLE;
  63. 		 			H_4_55:	 if(data_uart==8'h55)
  64. 		 						state<=H_5_55;
  65. 		 						else state<=IDLE;
  66. 		 			H_5_55:	 if(data_uart==8'h55)
  67. 		 						state<=H_6_55;
  68. 		 						else state<=IDLE;
  69. 		 			H_6_55:	 if(data_uart==8'h55)
  70. 		 						state<=H_7_55;
  71. 		 						else state<=IDLE;
  72. 		 			H_7_55:	 if(data_uart==8'hd5)
  73. 		 						state<=H_d5;
  74. 		 						else state<=IDLE;
  75. 		 			H_d5:	 if(data_uart==8'haa)
  76. 		 						state<=H_se;
  77. 		 					 else if(data_uart==8'h55)
  78. 		 						state<=H_wr;
  79. 		 					 else state<=IDLE;
  80. 		 			H_se:	 if(sen_stop_flag==1)
  81. 		 						state<=IDLE;
  82. 		 					 else state<=state;
  83. 		 			H_wr:	 if(stop_flag==1)
  84. 		 						state<=IDLE;	
  85. 		 					else state<=state;
  86. 					default:;
  87. 					endcase 
  89. always@(posedge sclk or negedge rst_n)
  90. 		if(!rst_n)
  91. 		flag_uart_dely<=0;
  92. 		else 	flag_uart_dely<=flag_uart;
  93. always@(posedge sclk or negedge rst_n)
  94. 		if(!rst_n)
  95. 		flag_uart_dely1<=0;
  96. 		else 	flag_uart_dely1<=flag_uart_dely;
  97. 						
  98. always@(posedge sclk or negedge rst_n)    //产生读计数器，对输入的标志位计数
  99. 	if(!rst_n)
  100. 		cnt_flag<=2'd0;
  101. 	else if(sen_stop_flag==1)
  102. 		cnt_flag<=2'd0;
  103. 	else if(cnt_flag==5)
  104. 		cnt_flag<=cnt_flag;
  105. 	else if(state==H_se&&flag_uart_dely==1)	
  106. 		cnt_flag<=cnt_flag+1;
  108. always@(posedge sclk or negedge rst_n)    //读地址拼接——目前不确定要不要清零
  109. 	if(!rst_n)
  110. 		tmp_addr<=24'd0;
  111. 	else if(state==H_se&&flag_uart==1&&cnt_flag<=3)
  112. 		tmp_addr<={tmp_addr[15:0],data_uart};
  113. 	
  114. always@(posedge sclk or negedge rst_n)    //地址发送
  115. 	if(!rst_n)
  116. 		se_addr<=24'd0;
  117. 	else se_addr<=tmp_addr;
  119. always@(posedge sclk or negedge rst_n)    //清除标志位产生
  120. 	if(!rst_n)
  121. 		se_flag<=0;
  122. 	else if(cnt_flag==4)
  123. 		se_flag<=flag_uart_dely1;
  124. 	else  se_flag<=0;
  125. 						
  126. always@(posedge sclk or negedge rst_n)    //产生写计数器，对输入的标志位计数
  127. 	if(!rst_n)
  128. 		cnt_flag_wr<=2'd0;
  129. 	else if(stop_flag==1)
  130. 		cnt_flag_wr<=2'd0;
  131. 	else if(cnt_flag_wr==5)
  132. 		cnt_flag_wr<=cnt_flag_wr;
  133. 	else if(state==H_wr&&flag_uart_dely==1)	
  134. 		cnt_flag_wr<=cnt_flag_wr+1;
  136. always@(posedge sclk or negedge rst_n)    //写地址拼接——目前不确定要不要清零wr_flag_dizhi
  137. 	if(!rst_n)
  138. 		tmp_addr_wr<=24'd0;
  139. 	else if(state==H_wr&&flag_uart==1&&cnt_flag_wr<=3)
  140. 		tmp_addr_wr<={tmp_addr_wr[15:0],data_uart};
  141.  
  142. always@(posedge sclk or negedge rst_n)    //写地址拼接——目前不确定要不要清零wr_flag_dizhi
  143. 	if(!rst_n)
  144. 		wr_flag_dizhi<=0;
  145. 	else if(cnt_flag_wr==4)
  146. 		wr_flag_dizhi<=flag_uart_dely;
  147. 	else	wr_flag_dizhi<=0;
  148. 	
  149. always@(posedge sclk or negedge rst_n)    //地址发送
  150. 	if(!rst_n)
  151. 		wr_addr<=24'd0;
  152. 	else wr_addr<=tmp_addr_wr;
  154. always@(posedge sclk or negedge rst_n)    //数据发送标志位产生
  155. 	if(!rst_n)
  156. 		wr_flag<=0;
  157. 	else if(cnt_flag_wr>=5)
  158. 		wr_flag<=flag_uart_dely1;
  159. 	else  wr_flag<=0;
  161. always@(posedge sclk or negedge rst_n)    //写的数据打拍
  162. 	if(!rst_n)
  163. 		wr_data<=8'd0;
  164. 	else if(cnt_flag_wr==5)
  165. 		wr_data<=data_uart;
  166. 	else if(stop_flag==1)
  167. 		wr_data<=8'd0;
  168. 	
  169. always@(posedge sclk or negedge rst_n)    //回传数据标志位
  170. 	if(!rst_n)
  171. 		tx_flag<=0;
  172. 	else if(sen_stop_flag==1)
  173. 		tx_flag<=1;
  174. 	else if(stop_flag==1&&state==H_wr)
  175. 		tx_flag<=1;
  176. 	else tx_flag<=0;
  177. 	
  178. always@(posedge sclk or negedge rst_n)    //回传数据
  179. 	if(!rst_n)
  180. 		tx_data<=8'd0;
  181. 	else if(sen_stop_flag==1)
  182. 		tx_data<=8'h55;
  183. 	else if(stop_flag==1)
  184. 		tx_data<=8'haa;
  185. 	else tx_data<=8'd0;	
  187. endmodule

 

  1. /***************************
  2. spi协议控制flash扇区擦除
  3. ****************************/
  4. module flash_ctrl_se(
  5. 		
  6. 		input	wire		sclk,
  7. 		input	wire		rst_n,
  8. 		input	wire		pi_se_flag,
  9. 		input	wire [23:0] se_addr_in,
  10. 		
  11. 		output	reg			led,
  12. 		output	reg			cs_n,
  13. 		output	reg			sck,
  14. 		output	reg			sdi,
  15. 		output	reg			sent_flag_out			//地址清零结束位
  16.  
  17. );
  18.  
  19. reg	[9:0]	state;
  20. parameter	idle		=10'b0000_0000_01;
  21. parameter	WAIT1		=10'b0000_0000_10;
  22. parameter	WRITE		=10'b0000_0001_00;
  23. parameter	WAIT2		=10'b0000_0010_00;
  24. parameter	WAIT3		=10'b0000_0100_00;
  25. parameter	WAIT4		=10'b0000_1000_00;
  26. parameter	SE			=10'b0001_0000_00;
  27. parameter	INIT_ADDR	=10'b0010_0000_00;
  28. parameter	WAIT5		=10'b0100_0000_00;
  29. parameter	WAIT_3S		=10'b1000_0000_00; 	
  30. reg	[4:0]	sclk_cnt;
  31. parameter	SCLK_CNT=31;
  32. reg	[1:0]	cnt_init_addr;
  33. reg	[25:0]	cnt_1s;
  34. parameter	ONE_S=49_9999_99;
  35. reg	[1:0]	cnt_3s;
  36. reg	[1:0]	cnt4;
  37. reg	[2:0]	bit_cnt;
  38. reg	[3:0]	cnt_wait_3s;
  39. reg	[23:0]	init_addr;
  40. parameter	wr_en=8'h06;		//信号差了一个时钟周期
  41. parameter	se_en=8'hd8;
  42. parameter	CNT_wait_3s=7;
  43. reg			cnt_3s_en;
  44.  
  45. always@(posedge	sclk or negedge rst_n)	//循环擦除
  46. 		if(!rst_n)	
  47. 			cnt_wait_3s<=3'd0;
  48. 		else if(cnt_wait_3s==CNT_wait_3s&&cnt_1s==ONE_S&&cnt_3s==2)
  49. 			cnt_wait_3s<=3'd0;
  50. 		else if(state==WAIT_3S&&cnt_1s==ONE_S&&cnt_3s==2)
  51. 			cnt_wait_3s<=cnt_wait_3s+1'b1;
  53. always@(posedge	sclk or negedge rst_n)	//扇区地址变换
  54. 		if(!rst_n)	
  55. 		init_addr<=24'd0;
  56. 		else if(pi_se_flag==1)
  57. 			init_addr<=se_addr_in;
  58. 		else if(state==WAIT_3S&&cnt_1s==ONE_S&&cnt_3s==2)  /
  59. 			init_addr<=init_addr+24'h01_0000;
  60. 		else if(state==idle)
  61. 			init_addr<=24'd0;
  62. 					
  63. always@(posedge	sclk or negedge	rst_n)		//为输出时钟计数
  64. 		if(!rst_n)
  65. 			cnt4<=2'd0;
  66. 		else if(cnt4==3)
  67. 			cnt4<=2'd0;
  68. 		else if(state==WRITE||state==SE||state==INIT_ADDR)
  69. 			 cnt4<=cnt4+1;
  70. always@(posedge	sclk or negedge	rst_n)   //	bit位计数
  71. 		if(!rst_n)
  72. 		bit_cnt<=3'd0;
  73. 		else if(bit_cnt==7&&cnt4==3)
  74. 		bit_cnt<=3'd0;
  75. 		else if(cnt4==3)
  76. 				bit_cnt<=bit_cnt+1;
  77. 				
  78. always@(posedge	sclk or negedge	rst_n)
  79. 		if(!rst_n)
  80. 		cnt_1s<=26'd0;
  81. 		else if(cnt_1s==ONE_S)
  82. 			cnt_1s<=26'd0;
  83. 		else if(cnt_3s_en==1)
  84. 			cnt_1s<=cnt_1s+1;
  85. always@(posedge	sclk or negedge	rst_n)
  86. 		if(!rst_n)
  87. 		cnt_3s<=2'd0;
  88. 		else if(cnt_1s==ONE_S&&cnt_3s==2)
  89. 			cnt_3s<=2'd0;
  90. 		else if(cnt_1s==ONE_S)
  91. 			cnt_3s<=cnt_3s+1;
  92. always@(posedge	sclk or negedge rst_n)	//3秒使能信号
  93. 		if(!rst_n)	
  94. 		cnt_3s_en<=0;
  95. 		else if(cnt_1s==ONE_S&&cnt_3s==2)
  96. 			cnt_3s_en<=0;
  97. 		else if(state==WAIT_3S)
  98. 			cnt_3s_en<=1;
  99. always@(posedge	sclk or negedge rst_n)
  100. 		if(!rst_n)
  101. 			cs_n<=1;
  102. 		else if(pi_se_flag==1)
  103. 			cs_n<=0;
  104. 		else if(state==idle)
  105. 			cs_n<=1;
  106. 		else if(state==WAIT2&&sclk_cnt==SCLK_CNT)		//片选信号没有描述对
  107. 			cs_n<=1;
  108. 		else if(state==WAIT3&&sclk_cnt==SCLK_CNT)
  109. 			cs_n<=0;
  110. 		else if(state==WAIT5&&sclk_cnt==SCLK_CNT)
  111. 			cs_n<=1;
  112. 		else if(state==WAIT_3S&&cnt_1s==ONE_S&&cnt_3s==2)
  113. 			cs_n<=0;
  114. 		//else if(cnt_wait_3s==CNT_wait_3s)
  115. 			//cs_n<=1;		
  116.  
  117. always@(posedge	sclk or negedge rst_n)
  118. 		if(!rst_n)	
  119. 			sclk_cnt<=5'd0;
  120. 		else if	(sclk_cnt==SCLK_CNT&&cnt_wait_3s==CNT_wait_3s)
  121. 			sclk_cnt<=5'd0;
  122. 		else if(sclk_cnt==SCLK_CNT)
  123. 				sclk_cnt<=5'd0;
  124. 		else if(cs_n==0)
  125. 			sclk_cnt<=sclk_cnt+1;
  126. 		else if(state==WAIT3)
  127. 			sclk_cnt<=sclk_cnt+1;				
  128. always@(posedge	sclk or negedge rst_n)   //3位状态计数
  129. 		if(!rst_n)
  130. 		cnt_init_addr<=2'd0;
  131. 		else if(cnt_init_addr==2'd2&&sclk_cnt==SCLK_CNT)
  132. 			cnt_init_addr<=2'd0;
  133. 		else if(sclk_cnt==SCLK_CNT&&state==INIT_ADDR)
  134. 			cnt_init_addr<=cnt_init_addr+1;
  135. 			
  136. always@(posedge	sclk or negedge rst_n)
  137. 		if(!rst_n)
  138. 			state<=idle;
  139. 		else case(state)
  140. 				idle:		if(pi_se_flag==1)
  141. 								state<=WAIT1;
  142. 							else state<=idle;								
  143. 				WAIT1:		if(sclk_cnt==SCLK_CNT)
  144. 								state<=WRITE;
  145. 							else	state<=WAIT1;
  146. 				WRITE:		if(sclk_cnt==SCLK_CNT)
  147. 								state<=WAIT2;
  148. 							else state<=WRITE;
  149. 				WAIT2:		if(sclk_cnt==SCLK_CNT)
  150. 								state<=WAIT3;
  151. 							else 	state<=WAIT2;
  152. 				WAIT3:		if(sclk_cnt==SCLK_CNT)
  153. 								state<=WAIT4;
  154. 							else	state<=WAIT3;
  155. 				WAIT4:		if(sclk_cnt==SCLK_CNT)
  156. 								state<=SE;
  157. 				SE:			if(sclk_cnt==SCLK_CNT)
  158. 								state<=INIT_ADDR;
  159. 							else state<=SE;
  160. 				INIT_ADDR:	if(cnt_init_addr==2'd2&&sclk_cnt==SCLK_CNT)
  161. 								state<=WAIT5;
  162. 								else state<=INIT_ADDR;
  163. 				WAIT5:		if(sclk_cnt==SCLK_CNT)
  164. 								state<=WAIT_3S;
  165. 							else	state<=WAIT5;
  166. 				WAIT_3S:	if(cnt_1s==ONE_S&&cnt_3s==2)
  167. 									state<=WAIT1;
  168. 							else if(cnt_wait_3s==CNT_wait_3s) 
  169. 									state<=idle;
  170. 				default:	state<=idle;
  171. 				endcase
  173. 								
  174. always@(posedge	sclk or negedge rst_n)	//时钟传递
  175. 		if(!rst_n)		
  176. 		  sck<=0;
  177. 		 else if(state==WRITE &&cnt4==1)	
  178. 		 		sck<=1;
  179. 		 else if(state==WRITE&&cnt4==3)
  180. 		 		sck<=0;
  181. 		 else if (state==SE&&cnt4==1)	
  182. 		 		sck<=1;
  183. 		 else if(state==SE&&cnt4==3)
  184. 		 		sck<=0;
  185. 		 else if (state==INIT_ADDR&&cnt4==1)	
  186. 		 		sck<=1;
  187. 		 else if(state==INIT_ADDR&&cnt4==3)
  188. 		 		sck<=0;
  189. 		 		
  190. always@(posedge	sclk or negedge rst_n)	//低电平传输数据 上升沿采集数据
  191. 		if(!rst_n)
  192. 			sdi<=1'b1;
  193. 		else if(state==WRITE)	
  194. 			sdi<=wr_en[7-bit_cnt];
  195. 		else if(state==SE)	
  196. 			sdi<=se_en[7-bit_cnt];
  197. 		else if(state==INIT_ADDR&&cnt_init_addr==0)
  198. 			sdi<=init_addr[23-bit_cnt];
  199. 		else if(state==INIT_ADDR&&cnt_init_addr==1)
  200. 			sdi<=init_addr[15-bit_cnt];
  201. 		else if(state==INIT_ADDR&&cnt_init_addr==2)
  202. 			sdi<=init_addr[7-bit_cnt];
  203. 		else sdi<=1'b1;							//检查发现有问题
  205. always@(posedge	sclk or negedge	rst_n)
  206. 			if(!rst_n)
  207. 				led<=0;
  208. 		else if(cnt_3s_en==1)
  209. 				led<=1;
  210. 		else	led<=0;
  211. 		
  212. always@(posedge	sclk or negedge	rst_n)
  213. 			if(!rst_n)
  214. 			sent_flag_out<=0;
  215. 			else if(cnt_wait_3s==CNT_wait_3s&&cnt_1s==ONE_S&&cnt_3s==2)
  216. 				sent_flag_out<=1;
  217. 			else sent_flag_out<=0;
  218. 			
  219. endmodule

 

  1. /***************************
  2. spi协议控制flash扇区数据输入
  3. ****************************/
  4. module flash_ctrl_wr(
  5. 		
  6. 		input	wire			sclk,
  7. 		input	wire			rst_n,
  8. 		input	wire			pi_flag,
  9. 		input	wire			pi_flag_dizhi,
  10. 		input	wire	[7:0]	data_in,
  11. 		input	wire			stop_flag_rx,		//发送端输入的停止位
  12. 		input	wire	[23:0]	frame_wr_addr,
  13. 		
  14. 		output	reg		cs_n,
  15. 		output	reg		sck,
  16. 		output	reg		sdi
  17. );
  18.  
  19. reg	[9:0]	state;
  20. parameter	idle		=10'b0000_0000_01;
  21. parameter	WAIT1		=10'b0000_0000_10;
  22. parameter	WRITE		=10'b0000_0001_00;
  23. parameter	WAIT2		=10'b0000_0010_00;
  24. parameter	WAIT3		=10'b0000_0100_00;
  25. parameter	WAIT4		=10'b0000_1000_00;
  26. parameter	PP			=10'b0001_0000_00;
  27. parameter	INIT_ADDR	=10'b0010_0000_00;
  28. parameter	DATA_IN		=10'b0100_0000_00;
  29. parameter	WAIT5		=10'b1000_0000_00; 	
  30. reg	[4:0]	sclk_cnt;
  31. parameter	SCLK_CNT=31;
  32. reg	[1:0]	cnt_init_addr;
  33. reg	[1:0]	cnt4;
  34. reg	[2:0]	bit_cnt;
  35. reg			add_addr_flag;
  36. reg	[23:0]	init_addr;
  37. parameter	INIT_ADDR_Location=6'h00_00_00;
  38. parameter	wr_en=8'h06;
  39. parameter	PP_en=8'h02;
  42. always@(posedge sclk or negedge rst_n)
  43. 	if(!rst_n)
  44. 		add_addr_flag<=0;
  45. 	else if(state==WAIT5&&sclk_cnt==SCLK_CNT)
  46. 		add_addr_flag<=1;
  47. 	else add_addr_flag<=0;
  51. always@(posedge	sclk or negedge rst_n)	
  52. 		if(!rst_n)	
  53. 			init_addr<=INIT_ADDR_Location;
  54. 		else if(pi_flag_dizhi==1)
  55. 				init_addr<=frame_wr_addr;
  56. 		else if(add_addr_flag==1)
  57. 			init_addr<=init_addr+24'h0000_01; 	//字节自动加一，加到255后页自动加一
  58. 		//else init_addr<=24'd0;
  59. 					
  60. always@(posedge	sclk or negedge	rst_n)
  61. 		if(!rst_n)
  62. 			cnt4<=2'd0;
  63. 		else if(cnt4==3)
  64. 			cnt4<=2'd0;
  65. 		else if(state==WRITE||state==PP||state==INIT_ADDR||state==DATA_IN)
  66. 			 cnt4<=cnt4+1;
  67. always@(posedge	sclk or negedge	rst_n)
  68. 		if(!rst_n)
  69. 			bit_cnt<=3'd0;
  70. 		else if(bit_cnt==7&&cnt4==3)
  71. 			bit_cnt<=3'd0;
  72. 		else if(cnt4==3)
  73. 				bit_cnt<=bit_cnt+1;
  74. 				
  76. always@(posedge	sclk or negedge rst_n)
  77. 		if(!rst_n)
  78. 			cs_n<=1;
  79. 		else if(pi_flag==1)
  80. 			cs_n<=0;
  81. 		else if(state==WAIT2&&sclk_cnt==SCLK_CNT)
  82. 			cs_n<=1;
  83. 		else if(state==WAIT3&&sclk_cnt==SCLK_CNT)
  84. 			cs_n<=0;
  85. 		else if(sclk_cnt==SCLK_CNT&&state==WAIT5)
  86. 			cs_n<=1;		
  87. always@(posedge	sclk or negedge rst_n)
  88. 		if(!rst_n)	
  89. 			sclk_cnt<=5'd0;
  90. 		else if	(sclk_cnt==SCLK_CNT&&state==WAIT5)
  91. 			sclk_cnt<=5'd0;
  92. 		else if(sclk_cnt==SCLK_CNT)	
  93. 			sclk_cnt<=5'd0;
  94. 		else if(cs_n==0)
  95. 			sclk_cnt<=sclk_cnt+1;
  96. 		else if(state==WAIT3)
  97. 			sclk_cnt<=sclk_cnt+1;
  98.  
  99. always@(posedge	sclk or negedge rst_n)
  100. 		if(!rst_n)
  101. 		cnt_init_addr<=2'd0;
  102. 		else if(cnt_init_addr==2'd2&&sclk_cnt==SCLK_CNT)
  103. 			cnt_init_addr<=2'd0;
  104. 		else if(sclk_cnt==SCLK_CNT&&state==INIT_ADDR)
  105. 			cnt_init_addr<=cnt_init_addr+1;
  106. 			
  107. always@(posedge	sclk or negedge rst_n)
  108. 		if(!rst_n)
  109. 			state<=idle;
  110. 		else case(state)
  111. 				idle:		if(pi_flag==1)
  112. 								state<=WAIT1;
  113. 							else	state<=idle;
  114. 				WAIT1:		if(sclk_cnt==SCLK_CNT)
  115. 								state<=WRITE;
  116. 							else	state<=WAIT1;
  117. 				WRITE:		if(sclk_cnt==SCLK_CNT)
  118. 								state<=WAIT2;
  119. 							else state<=WRITE;
  120. 				WAIT2:		if(sclk_cnt==SCLK_CNT)
  121. 								state<=WAIT3;
  122. 							else 	state<=WAIT2;
  123. 				WAIT3:		if(sclk_cnt==SCLK_CNT)
  124. 								state<=WAIT4;
  125. 							else	state<=WAIT3;
  126. 				WAIT4:		if(sclk_cnt==SCLK_CNT)
  127. 								state<=PP;
  128. 				PP:			if(sclk_cnt==SCLK_CNT)
  129. 								state<=INIT_ADDR;
  130. 							else state<=PP;
  131. 				INIT_ADDR:	if(cnt_init_addr==2'd2&&sclk_cnt==SCLK_CNT)
  132. 								state<=DATA_IN;
  133. 								else state<=INIT_ADDR;
  134. 				DATA_IN:	if(sclk_cnt==SCLK_CNT)
  135. 								state<=WAIT5;
  136. 							else	state<=DATA_IN;
  137. 				WAIT5:		if(stop_flag_rx)
  138. 									state<=idle;
  139. 							else if(sclk_cnt==SCLK_CNT)
  140. 									state<=idle;
  141. 							else state<=WAIT5;
  142. 				default:	state<=idle;
  143. 				endcase
  144. 								
  145. always@(posedge	sclk or negedge rst_n)	//时钟传递
  146. 		if(!rst_n)		
  147. 		  sck<=0;
  148. 		 else if(state==WRITE &&cnt4==1)	
  149. 		 		sck<=1;
  150. 		 else if(state==WRITE&&cnt4==3)
  151. 		 		sck<=0;
  152. 		 else if (state==PP&&cnt4==1)	
  153. 		 		sck<=1;
  154. 		 else if(state==PP&&cnt4==3)
  155. 		 		sck<=0;
  156. 		 else if (state==INIT_ADDR&&cnt4==1)	
  157. 		 		sck<=1;
  158. 		 else if(state==INIT_ADDR&&cnt4==3)
  159. 		 		sck<=0;
  160. 		 else if (state==DATA_IN&&cnt4==1)	
  161. 		 		sck<=1;
  162. 		 else if(state==DATA_IN&&cnt4==3)
  163. 		 		sck<=0;
  164. 		 		
  165. always@(posedge	sclk or negedge rst_n)	
  166. 		if(!rst_n)
  167. 			sdi<=1'b1;
  168. 		else if(state==WRITE)	
  169. 			sdi<=wr_en[7-bit_cnt];
  170. 		else if(state==PP)	
  171. 			sdi<=PP_en[7-bit_cnt];
  172. 		else if(state==INIT_ADDR&&cnt_init_addr==0)
  173. 			sdi<=init_addr[23-bit_cnt];
  174. 		else if(state==INIT_ADDR&&cnt_init_addr==1)
  175. 			sdi<=init_addr[15-bit_cnt];
  176. 		else if(state==INIT_ADDR&&cnt_init_addr==2)
  177. 			sdi<=init_addr[7-bit_cnt];
  178. 		else if(state==DATA_IN)
  179. 			 sdi<=data_in[7-bit_cnt];
  180. 		else sdi<=1'b1;							
  181.  
  182. endmodule
  1. module key_rock(
  2. 		input wire sclk,
  3. 		input wire rst_n,
  4. 		input wire key_in,
  5. 		
  6. 		output reg key_o
  7. );
  8. reg [18:0] cnt;
  9. parameter CNT_MAX=500000-1;
  10. always@(posedge sclk or negedge rst_n)
  11. 		if(!rst_n)
  12. 			cnt<=1'b0;
  13. 			 else if(key_in==1)
  14. 					cnt<=0;
  15. 					else if(cnt==CNT_MAX)
  16. 						 cnt<=cnt;
  17. 					else
  18. 							cnt<=cnt+1'b1;
  19. always@(posedge sclk or negedge rst_n)
  20. 		if(!rst_n)
  21. 			key_o<=1'b0;
  22. 			else if (cnt==CNT_MAX-1)
  23. 			 key_o<=1'b1;
  24. 			 else
  25. 			 key_o<=1'b0;
  26. endmodule
  1. module	icap_ctrl(
  2. 		
  3. 		input	wire			sclk,
  4. 		input	wire			rst_n,
  5. 		input	wire			key_in,
  6. 		input	wire	[23:0]	wr_addr_frame
  7. );
  8.  
  9. reg		[3:0]		cnt;
  10. reg					ce;
  11. reg		[15:0]		tmp_i;
  12. wire	[15:0]		i_data;
  13.  
  14. always@(posedge sclk or negedge rst_n)		//cnt14
  15. 		if(!rst_n)
  16. 			cnt<=4'd0;
  17. 		else if(cnt==14)
  18. 			cnt<=4'd0;
  19. 		else if (ce==0)
  20. 			cnt<=cnt+1'b1;
  21. 	
  22. always@(posedge sclk or negedge rst_n)  //ce
  23. 		if(!rst_n)
  24. 			ce<=1'b1;
  25. 		else if(cnt==14)
  26. 			ce<=1'b1;
  27. 		else if (key_in==1)		//不是很理解
  28. 			ce<=1'b0;
  29.  
  30. always@(posedge sclk or negedge rst_n)
  31. 		if(!rst_n)
  32. 			tmp_i<=16'hffff;
  33. 		else 	case(cnt)
  34. 					0:	tmp_i<=16'hffff;
  35. 					1:	tmp_i<=16'haa99;
  36. 					2:	tmp_i<=16'h5566;
  37. 					3:	tmp_i<=16'h3261;
  38. 					4:	tmp_i<=wr_addr_frame[15:0];	//{data_uart,tmp_addr[7:0]};
  39. 					5:	tmp_i<=16'h3281;
  40. 					6:	tmp_i<={8'h03,wr_addr_frame[23:16]};//
  41. 					7:	tmp_i<=16'h32a1;
  42. 					8:	tmp_i<=16'h0000;	//
  43. 					9:	tmp_i<=16'h32c1;
  44. 				   10:	tmp_i<=16'h0300;	//
  45. 				   11:	tmp_i<=16'h30a1;
  46. 				   12:	tmp_i<=16'h000e;
  47. 				   13:	tmp_i<=16'h2000;
  48. 				   14:	tmp_i<=16'hffff;
  49. 			  default:	tmp_i<=16'hffff;
  50. 			endcase
  51. assign i_data={tmp_i[8],tmp_i[9],tmp_i[10],tmp_i[11],tmp_i[12],tmp_i[13],tmp_i[14],tmp_i[15],
  52. 		   tmp_i[0],tmp_i[1],tmp_i[2],tmp_i[3],tmp_i[4],tmp_i[5],tmp_i[6],tmp_i[7]};
  53.  
  54.  
  55.  
  56. ICAP_SPARTAN6 #(
  57.    .DEVICE_ID(28'h4000093),     // Specifies the pre-programmed Device ID value
  58.    .SIM_CFG_FILE_NAME("NONE")  // Specifies the Raw Bitstream (RBT) file to be parsed by the simulation
  59.                                // model
  60. )
  61. ICAP_SPARTAN6_inst (
  62.    .BUSY(),   // 1-bit output: Busy/Ready output
  63.    .O(),         // 16-bit output: Configuartion data output bus
  64.    .CE(ce),       // 1-bit input: Active-Low ICAP Enable input
  65.    .CLK(sclk),     // 1-bit input: Clock input
  66.    .I(i_data),         // 16-bit input: Configuration data input bus
  67.    .WRITE(1'b0)  // 1-bit input: Read/Write control input
  68. );
  69.  
  70. endmodule
  1. module tx_crtl(
  2.  
  3. 			input wire sclk,
  4. 			input wire rst_n,
  5. 			input wire [7:0] data_in,
  6. 			input wire flag_in,
  7. 			
  8. 			output reg data_o
  9.  
  10. );
  11.  
  12. reg	[12:0]	cnt;
  13. reg	[3:0]   bit_cnt;
  14. reg			tx_en;
  15. parameter  CNT=5207;
  16. parameter  BIT_CNT=8;
  17. reg	[7:0]	data_in_dely;
  18.  
  19. always@(posedge sclk or negedge rst_n)
  20. 		if(!rst_n)
  21. 			data_in_dely<=8'd0;
  22. 		else if(flag_in==1)
  23. 			data_in_dely<=data_in;
  24. 		else if(tx_en==0)
  25. 			data_in_dely<=8'd0;
  26. //tx_en
  27. always@(posedge sclk or negedge rst_n)
  28. 		if(!rst_n)
  29. 			tx_en<=1'b0;
  30. 			else if(flag_in==1'b1)
  31. 				tx_en<=1'b1;
  32. 			else if(bit_cnt==BIT_CNT&&cnt==CNT)
  33. 			tx_en<=1'b0;
  34. //cnt 波特率计数
  35. always@(posedge sclk or negedge rst_n)	
  36. 		if(!rst_n)		
  37. 			cnt<=13'd0;
  38. 		else if(cnt==CNT)	
  39. 			cnt<=13'd0;
  40. 			else if(tx_en==1'b1)	  //条件没写对
  41. 					cnt<=cnt+1'b1;
  42. 				
  43. //bit_cnt 字节统计
  44. always@(posedge sclk or negedge rst_n)	
  45. 		if(!rst_n)	
  46. 			bit_cnt<=4'd0;
  47. 		else if(tx_en==1'b0)
  48. 				bit_cnt<=4'd0;
  49. 		else if(bit_cnt==BIT_CNT&cnt==CNT)
  50. 				bit_cnt<=4'd0;
  51. 			else if(cnt==CNT)
  52. 				bit_cnt<=bit_cnt+1'b1;
  53. 				
  54. //输出数据控制
  55. always@(posedge sclk or negedge rst_n)	
  56. 		if(!rst_n)	
  57. 		data_o<=1'b1;
  58. 		else if(tx_en==1'b0)  //flag_in==1'b1
  59. 			data_o<=1'b1;
  60. 		else if(bit_cnt==10'd0)  //flag_in==1'b1
  61. 			data_o<=1'b0;
  62. 			else if(bit_cnt==10'd1)
  63. 				data_o<=data_in_dely[0];
  64. 			else if (bit_cnt==10'd2)
  65. 				data_o<=data_in_dely[1];
  66. 			else if(bit_cnt==10'd3)
  67. 				data_o<=data_in_dely[2];
  68. 			else if(bit_cnt==10'd4)
  69. 				data_o<=data_in_dely[3];
  70. 			else if(bit_cnt==10'd5)	
  71. 		  		data_o<=data_in_dely[4];
  72. 		  	else if(bit_cnt==10'd6)
  73. 		  		data_o<=data_in_dely[5];
  74. 			else if(bit_cnt==10'd7)
  75. 				data_o<=data_in_dely[6];
  76. 			else if(bit_cnt==10'd8)
  77. 				data_o<=data_in_dely[7];
  78. 			//else if(bit_cnt==BIT_CNT)
  79. 			//		data_o<=1'b1;
  80. 				else data_o<=1'b1;
  81. 					
  82. endmodule
  1. module	top_updata(
  2. 		
  3. 		input	wire 		sclk,
  4. 		input	wire		rst_n,
  5. 		input	wire		rx_uart_data,
  6. 		input	wire		key_in,
  7. 		
  8. 		output	wire		tx_data,
  9. 		output	wire		led,
  10. 		output	wire		cs_n,
  11. 		output	wire		sck,
  12. 		output	wire		sdi
  13. );
  14.  
  15. wire			key_inst_o;
  16. wire			stop_flag_rx; 
  17. wire			flag_o_rx;
  18. wire	[7:0]	data_o_rx;
  19. wire			wr_flag_frame_inst;
  20. wire	[23:0]	wr_addr_frame_inst;  
  21. wire	[7:0]	wr_data_inst;
  22. wire			se_flag_frame;
  23. wire	[23:0]	se_addr_frame;
  24. wire			sent_flag_out_se_inst;
  25. wire			tx_flag_frame;
  26. wire	[7:0]	tx_data_farme;
  27. wire			wr_inst_cs_n;
  28. wire			wr_inst_sck;
  29. wire			wr_inst_sdi;
  30. wire			se_inst_cs_n;
  31. wire			se_inst_sck;
  32. wire			se_inst_sdi;
  33. wire			wr_flag_dizhi;
  34.  
  35. assign		cs_n=(wr_inst_cs_n&&se_inst_cs_n);
  36. assign		sck=(wr_inst_sck||se_inst_sck);
  37. assign		sdi=(wr_inst_sdi&&se_inst_sdi);
  38.  
  39. key_rock	key_rock_inst(
  40. 			.sclk		(sclk),
  41. 			.rst_n		(rst_n),
  42. 			.key_in		(key_in),
  43. 			.key_o      (key_inst_o)
  44. );
  45.  
  46. icap_ctrl	icap_ctrl_inst(
  47. 		
  48. 			.sclk			(sclk),
  49. 			.rst_n			(rst_n),
  50. 			.key_in			(key_inst_o),
  51. 			.wr_addr_frame  (wr_addr_frame_inst)
  52. );
  53.  
  54. rx_crtl		rx_crtl_inst(
  55.  
  56. 		.sclk		(sclk),
  57. 		.rst_n		(rst_n),
  58. 		.rx_in		(rx_uart_data),
  59. 		.stop_flag	(stop_flag_rx), 
  60. 		.flag_o		(flag_o_rx),
  61. 		.data_o     (data_o_rx)
  62. );
  63.  
  64. w_farme	w_farme_inst(
  65. 		
  66. 			.sclk			(sclk),
  67. 			.rst_n			(rst_n),
  68. 			.flag_uart		(flag_o_rx),
  69. 			.data_uart		(data_o_rx),
  70. 			.stop_flag		(stop_flag_rx),		//数据发送完成标志
  71. 			.sen_stop_flag	(sent_flag_out_se_inst),  //擦除完成标识
  72. 			.wr_flag_dizhi	(wr_flag_dizhi),
  73. 			.wr_flag		(wr_flag_frame_inst),		
  74. 			.wr_addr		(wr_addr_frame_inst),
  75. 			.wr_data		(wr_data_inst),
  76. 		
  77. 			.se_addr			(se_addr_frame),
  78. 			.se_flag			(se_flag_frame),
  79. 		
  80. 			.tx_flag	(tx_flag_frame),
  81. 			.tx_data	(tx_data_farme)	//擦除结束用55标志，发生完成用aa标识
  82. );
  83.  
  84. flash_ctrl_wr	flash_ctrl_wr_inst(
  85. 		
  86. 				.sclk			(sclk),
  87. 				.rst_n			(rst_n),
  88. 				.pi_flag		(wr_flag_frame_inst),
  89. 				.data_in		(wr_data_inst),
  90. 				.stop_flag_rx	(stop_flag_rx),		//发送端输入的停止位
  91. 				.frame_wr_addr	(wr_addr_frame_inst),
  92. 				.pi_flag_dizhi	(wr_flag_dizhi),
  93. 				.cs_n			(wr_inst_cs_n),
  94. 				.sck			(wr_inst_sck),
  95. 				.sdi            (wr_inst_sdi)
  96. );
  97.  
  98. flash_ctrl_se	flash_ctrl_se_inst(
  99. 		
  100. 			.sclk			(sclk),
  101. 			.rst_n			(rst_n),
  102. 			.pi_se_flag		(se_flag_frame),
  103. 			.se_addr_in		(se_addr_frame),
  104. 		
  105. 					.led			(led),
  106. 					.cs_n			(se_inst_cs_n),
  107. 					.sck			(se_inst_sck),
  108. 					.sdi			(se_inst_sdi),
  109. 					.sent_flag_out	(sent_flag_out_se_inst)		//地址清零结束位
  110.  
  111. );
  112.  
  113. tx_crtl	tx_crtl_inst(
  114.  
  115. 			.sclk		(sclk),
  116. 			.rst_n		(rst_n),
  117. 			.data_in	(tx_data_farme),
  118. 			.flag_in	(tx_flag_frame),
  119. 			
  120. 			.data_o    (tx_data)
  121.  
  122. );
  123.  
  124. endmodule
  1. `timescale	1ns/1ns    
  2. module	tb_update;
  3.         reg		sclk;
  4.         reg		rst_n;
  5.         reg		rx;
  6.         
  7.  
  8.         
  9.         reg[7:0] a_mem[18:0];	//当前为测试flash写模块 擦出数据为55 55 55 55 55 55 55 d5 aa 10 00 00
  10.         
  11.         initial   $readmemh("./data.txt", a_mem);	//测试flash写入数据为55 55 55 55 55 55 55 d5 55 10 00 00 01 02 03 04 05 aa 55 
  12.         initial
  13.         	begin
  14.         		sclk	=	1'b1;
  15.         		rst_n	<=	1'b0;
  16.         		#300
  17.         		rst_n	<=	1'b1;
  18.         	end
  19.         
  20.         always	#10	sclk	=	~sclk;
  21.         
  22.         initial
  23.         	begin
  24.         		rx	<=	1'b1;
  25.         		#2000
  26.         		rx_byte();
  27.         	end
  28.         
  29.         task	rx_byte();
  30.     
  31.         	integer	j;//定义一个整型变量
  32.         	for(j=0;j<19;j=j+1)//for循环   测试的时候，数据加到原来的256应该是86
  33.         		rx_bit(a_mem[j]);//a_mem[j]是data.txt文件里面第j个8比特数据
  34.         				//j每次取一个值，就调用一次rx_bit();
  35.         				//一共调用256次
  36. 	endtask
  37.         
  38.         task	rx_bit(input  [7:0]	data);//data是a_mem[j]的值。
  39.         	integer	i;
  40.         	for(i=0;i<10;i=i+1)
  41.         		begin
  42.         			case(i)
  43.         			0:	rx	<=	1'b0;//起始位
  44.         			1:	rx	<=	data[0];
  45.         			2:	rx	<=	data[1];
  46.         			3:	rx	<=	data[2];
  47.         			4:	rx	<=	data[3];
  48.         			5:	rx	<=	data[4];
  49.         			6:	rx	<=	data[5];
  50.         			7:	rx	<=	data[6];
  51.         			8:	rx	<=	data[7];
  52.         			//上面8个发送的是数据位
  53.         			9:	rx	<=	1'b1;//停止位
  54.         			endcase
  55.         			#104140;//一个波特时间=sclk周期*波特计数器	
  56.         		end
  57. 	endtask
  58. 	
  59. defparam 	top_updata_inst.flash_ctrl_se_inst.ONE_S=500;
  60. //defparam 	top_updata_inst.rx_crtl_inst.CNT=9;
  61. //defparam 	top_updata_inst.rx_crtl_inst.bit_flag_cnt=4;
  62. //defparam 	top_updata_inst.tx_crtl_inst.CNT=10;
  63. 	
  64. top_updata	top_updata_inst(
  65. 		
  66. 			.sclk			(sclk),
  67. 			.rst_n			(rst_n),
  68. 			.rx_uart_data	(rx),
  69. 			.key_in          ()
  70. );
  71. 		
  72. endmodule

4.这次比较难调试的frame_ctrl模块，多次仿真最终达到目的

5.如果仿真通过，下载只办卡却没有达到应有效果，就需要利用ise的chipscope对内部信号进行抓取。

6.擦除调试如图：

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