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在 imx6q 上适配 YT8531S

作者：一键难忘520 | 2024-08-12 01:16:01

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yt8531s

一、环境介绍

我适配的设备使用的是 RJ45 网口，phy 和 soc 之间的接口为 RGMII；

linux 版本：4.1.15

soc：imx6q 

二、硬件检查

1. 检查电源；

VDDL = DVDDL = AVDDL = 1.1V；由 32 脚 LX 输出；
AVDD33 检查是否为 3.3V 供电；
DVDD_RGMII 电压是否符合下表，由 36、37 脚来选择电压；

2. 检查时钟；

检查晶振能否正常输出 25Mhz 的信号；

3. 检查接线；

MDI、RGMII、MDIO、MDC 等是否正确连接；

4. 检查 phy 地址；

28、17 脚没有外部上拉的情况下，默认使用的是内部下拉，即值为 0；

 三、软件调试

1. phy id

phy 匹配过程大致如下，可以在 get_phy_device 函数里面判断是否正确读取 phy id；

  1. fec_probe
  2.   fec_enet_mii_init
  3.     of_mdiobus_register  Loop over the child nodes and register a phy_device for each one
  4. 	  of_mdiobus_register_phy
  5. 		get_phy_device ---get_phy_id（phy_device_create匹配phy_driver_register）   ---- phy_device_create
  6. 			              phy_reg = mdiobus_read(bus, addr, MII_PHYSID2);

可以在 u-boot 处，进入命令行模式，用 mii info 命令来查看是否正确获取 phy id，如果没有获取，多半是 phy 硬件有问题；

正常情况下，在 u-boot 时候，可以获取两个 phy id，一个广播地址 00，一个 phy 地址；
对于 YT8531S 来说，操作广播地址与操作 phy 地址没差别；

硬件复位后，需要延时 100 ms，才能进行 MDIO 读写；

 在 drivers/net/ethernet/freescale/fec_main.c 的 fec_reset_phy 函数尾部加一个 100ms 延时；

  1. static void fec_reset_phy(struct platform_device *pdev)
  2. {
  3.         int err, phy_reset;
  4.         int msec = 1;
  5.         struct device_node *np = pdev->dev.of_node;
  6.  
  7.         if (!np)
  8.                 return;
  9.  
  10.         err = of_property_read_u32(np, "phy-reset-duration", &msec);
  11.         /* A sane reset duration should not be longer than 1s */
  12.         if (!err && msec > 1000)
  13.                 msec = 1;
  14.  
  15.         phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
  16.         if (!gpio_is_valid(phy_reset))
  17.                 return;
  18.  
  19.         err = devm_gpio_request_one(&pdev->dev, phy_reset,
  20.                                     GPIOF_OUT_INIT_LOW, "phy-reset");
  21.         if (err) {
  22.                 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
  23.                 return;
  24.         }
  25.         msleep(msec);
  26.         gpio_set_value(phy_reset, 1);
  27.         msleep(100);
  28. }

2. ENET_TX_CLK

对于 imx6q，使用 RGMII 的时候，还需要一个 125M 的时钟；
将 phy 的外部寄存器 0xA012 改为 0x50 即可；

3. dts 和 driver

fec 节点如下：

  1. &fec {
  2. 	pinctrl-names = "default";
  3. 	pinctrl-0 = <&pinctrl_enet>;
  4. 	phy-mode = "rgmii";
  5. 	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
  6. 	phy-reset-duration = <2>;
  7. 	fsl,magic-packet;
  8. 	status = "okay";
  9. };
  10.  
  11. pinctrl_enet: enetgrp {
  12. 	fsl,pins = <
  13. 		MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
  14. 		MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
  15. 		MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
  16. 		MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
  17. 		MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
  18. 		MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
  19. 		MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
  20. 		MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
  21. 		MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
  22. 		MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
  23. 		MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
  24. 		MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
  25. 		MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
  26. 		MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
  27. 		MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
  28.  
  29. 		/* Phy reset */
  30. 		MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25		0x000b0
  31. 	>;

 motorcomm.c 修改如下：

  1. /*
  2.  * drivers/net/phy/motorcomm.c
  3.  *
  4.  * Driver for Motorcomm PHYs
  5.  *
  6.  * Author: Leilei Zhao <leilei.zhao@motorcomm.com>
  7.  *
  8.  * Copyright (c) 2019 Motorcomm, Inc.
  9.  *
  10.  * This program is free software; you can redistribute  it and/or modify it
  11.  * under  the terms of  the GNU General  Public License as published by the
  12.  * Free Software Foundation;  either version 2 of the  License, or (at your
  13.  * option) any later version.
  14.  *
  15.  * Support : Motorcomm Phys:
  16.  *      Giga phys: yt8511, yt8521
  17.  *      100/10 Phys : yt8512, yt8512b, yt8510
  18.  *      Automotive 100Mb Phys : yt8010
  19.  *      Automotive 100/10 hyper range Phys: yt8510
  20.  */
  21.  
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/phy.h>
  25. #include <linux/motorcomm_phy.h>
  26. #include <linux/of.h>
  27. #include <linux/clk.h>
  28. #ifndef LINUX_VERSION_CODE
  29. #include <linux/version.h>
  30. #else
  31. #define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
  32. #endif
  33. /*for wol, 20210604*/
  34. #include <linux/netdevice.h>
  35.  
  36. #include "yt8614-phy.h"
  37.  
  38. /**** configuration section begin ***********/
  39.  
  40. /* if system depends on ethernet packet to restore from sleep, please define this macro to 1
  41.  * otherwise, define it to 0.
  42.  */
  43. #define SYS_WAKEUP_BASED_ON_ETH_PKT     0
  44.  
  45. /* to enable system WOL of phy, please define this macro to 1
  46.  * otherwise, define it to 0.
  47.  * NOTE: this macro will need macro SYS_WAKEUP_BASED_ON_ETH_PKT to set to 1
  48.  */
  49. #define YTPHY_ENABLE_WOL        0
  50.  
  51. /* some GMAC need clock input from PHY, for eg., 125M, please enable this macro
  52.  * by degault, it is set to 0
  53.  */
  54. #define GMAC_CLOCK_INPUT_NEEDED 0
  55.  
  56.  
  57. #define YT8521_PHY_MODE_FIBER   1 //fiber mode only
  58. #define YT8521_PHY_MODE_UTP     2 //utp mode only
  59. #define YT8521_PHY_MODE_POLL    3 //fiber and utp, poll mode
  60.  
  61. /* please make choice according to system design
  62.  * for Fiber only system, please define YT8521_PHY_MODE_CURR 1
  63.  * for UTP only system, please define YT8521_PHY_MODE_CURR 2
  64.  * for combo system, please define YT8521_PHY_MODE_CURR 3 
  65.  */
  66. #define YT8521_PHY_MODE_CURR    2
  67.  
  68. /**** configuration section end ***********/
  69.  
  70.  
  71. /* no need to change below */
  72.  
  73. #if (YTPHY_ENABLE_WOL)
  74. #undef SYS_WAKEUP_BASED_ON_ETH_PKT
  75. #define SYS_WAKEUP_BASED_ON_ETH_PKT     1
  76. #endif
  77.  
  78. /* workaround for 8521 fiber 100m mode */
  79. static int link_mode_8521 = 0; //0: no link; 1: utp; 32: fiber. traced that 1000m fiber uses 32.
  80. static int link_mode_8614[4] = {0}; //0: no link; 1: utp; 32: fiber. traced that 1000m fiber uses 32.
  81.  
  82. /* for multiple port phy, base phy address */
  83. static unsigned int yt_mport_base_phy_addr = 0xff; //0xff: invalid;
  84. static unsigned int yt_mport_base_phy_addr_8614 = 0xff; //0xff: invalid;
  85.  
  86.  
  87. static int ytphy_read_ext(struct phy_device *phydev, u32 regnum)
  88. {
  89.     int ret;
  90.     int val;
  91.  
  92.     ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
  93.     if (ret < 0)
  94.         return ret;
  95.  
  96.     val = phy_read(phydev, REG_DEBUG_DATA);
  97.  
  98.     return val;
  99. }
  100.  
  101. static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val)
  102. {
  103.     int ret;
  104.  
  105.     ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
  106.     if (ret < 0)
  107.         return ret;
  108.  
  109.     ret = phy_write(phydev, REG_DEBUG_DATA, val);
  110.  
  111.     return ret;
  112. }
  113.  
  114.  
  115. int yt8521_soft_reset(struct phy_device *phydev)
  116. {
  117.     int ret;
  118.     int val;
  119.  
  120.     ytphy_write_ext(phydev, 0xa000, 0);
  121.     ret = genphy_soft_reset(phydev);
  122.     if (ret < 0)
  123.         return ret;
  124.  
  125.     ytphy_write_ext(phydev, 0xa000, 2);
  126.     ret = genphy_soft_reset(phydev);
  127.     if (ret < 0) {
  128.         ytphy_write_ext(phydev, 0xa000, 0);
  129.         return ret;
  130.     }
  131.  
  132.     ret = ytphy_write_ext(phydev, 0xA012, 0x50);
  133.     if (ret < 0)
  134.         return ret;
  135.  
  136.     return 0;
  137. }
  138.  
  139. #if (YTPHY_ENABLE_WOL)
  140. static int ytphy_switch_reg_space(struct phy_device *phydev, int space)
  141. {
  142.     int ret;
  143.  
  144.     if (space == YTPHY_REG_SPACE_UTP) {
  145.         ret = ytphy_write_ext(phydev, 0xa000, 0);
  146.     } else {
  147.         ret = ytphy_write_ext(phydev, 0xa000, 2);
  148.     }
  149.  
  150.     return ret;
  151. }
  152.  
  153. static int ytphy_wol_en_cfg(struct phy_device *phydev, ytphy_wol_cfg_t wol_cfg)
  154. {
  155.     int ret = 0;
  156.     int val = 0;
  157.  
  158.     val = ytphy_read_ext(phydev, YTPHY_WOL_CFG_REG);
  159.     if (val < 0)
  160.         return val;
  161.  
  162.     if (wol_cfg.enable) {
  163.         val |= YTPHY_WOL_CFG_EN;
  164.  
  165.         if (wol_cfg.type == YTPHY_WOL_TYPE_LEVEL) {
  166.             val &= ~YTPHY_WOL_CFG_TYPE;
  167.             val &= ~YTPHY_WOL_CFG_INTR_SEL;
  168.         } else if (wol_cfg.type == YTPHY_WOL_TYPE_PULSE) {
  169.             val |= YTPHY_WOL_CFG_TYPE;
  170.             val |= YTPHY_WOL_CFG_INTR_SEL;
  171.  
  172.             if (wol_cfg.width == YTPHY_WOL_WIDTH_84MS) {
  173.                 val &= ~YTPHY_WOL_CFG_WIDTH1;
  174.                 val &= ~YTPHY_WOL_CFG_WIDTH2;
  175.             } else if (wol_cfg.width == YTPHY_WOL_WIDTH_168MS) {
  176.                 val |= YTPHY_WOL_CFG_WIDTH1;
  177.                 val &= ~YTPHY_WOL_CFG_WIDTH2;
  178.             } else if (wol_cfg.width == YTPHY_WOL_WIDTH_336MS) {
  179.                 val &= ~YTPHY_WOL_CFG_WIDTH1;
  180.                 val |= YTPHY_WOL_CFG_WIDTH2;
  181.             } else if (wol_cfg.width == YTPHY_WOL_WIDTH_672MS) {
  182.                 val |= YTPHY_WOL_CFG_WIDTH1;
  183.                 val |= YTPHY_WOL_CFG_WIDTH2;
  184.             }
  185.         }
  186.     } else {
  187.         val &= ~YTPHY_WOL_CFG_EN;
  188.         val &= ~YTPHY_WOL_CFG_INTR_SEL;
  189.     }
  190.  
  191.     ret = ytphy_write_ext(phydev, YTPHY_WOL_CFG_REG, val);
  192.     if (ret < 0)
  193.         return ret;
  194.  
  195.     return 0;
  196. }
  197.  
  198. static void ytphy_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
  199. {
  200.     int val = 0;
  201.  
  202.     wol->supported = WAKE_MAGIC;
  203.     wol->wolopts = 0;
  204.  
  205.     val = ytphy_read_ext(phydev, YTPHY_WOL_CFG_REG);
  206.     if (val < 0)
  207.         return;
  208.  
  209.     if (val & YTPHY_WOL_CFG_EN)
  210.         wol->wolopts |= WAKE_MAGIC;
  211.  
  212.     return;
  213. }
  214.  
  215. static int ytphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
  216. {
  217.     int ret, pre_page, val;
  218.     ytphy_wol_cfg_t wol_cfg;
  219.     struct net_device *p_attached_dev = phydev->attached_dev;
  220.  
  221.     memset(&wol_cfg, 0, sizeof(ytphy_wol_cfg_t));
  222.     pre_page = ytphy_read_ext(phydev, 0xa000);
  223.     if (pre_page < 0)
  224.         return pre_page;
  225.  
  226.     /* Switch to phy UTP page */
  227.     ret = ytphy_switch_reg_space(phydev, YTPHY_REG_SPACE_UTP);
  228.     if (ret < 0)
  229.         return ret;
  230.  
  231.     if (wol->wolopts & WAKE_MAGIC) {
  232.         
  233.         /* Enable the WOL interrupt */
  234.         val = phy_read(phydev, YTPHY_UTP_INTR_REG);
  235.         val |= YTPHY_WOL_INTR;
  236.         ret = phy_write(phydev, YTPHY_UTP_INTR_REG, val);
  237.         if (ret < 0)
  238.             return ret;
  239.  
  240.         /* Set the WOL config */
  241.         wol_cfg.enable = 1; //enable
  242.         wol_cfg.type = YTPHY_WOL_TYPE_PULSE;
  243.         wol_cfg.width = YTPHY_WOL_WIDTH_672MS;
  244.         ret = ytphy_wol_en_cfg(phydev, wol_cfg);
  245.         if (ret < 0)
  246.             return ret;
  247.  
  248.         /* Store the device address for the magic packet */
  249.         ret = ytphy_write_ext(phydev, YTPHY_MAGIC_PACKET_MAC_ADDR2,
  250.                 ((p_attached_dev->dev_addr[0] << 8) |
  251.                  p_attached_dev->dev_addr[1]));
  252.         if (ret < 0)
  253.             return ret;
  254.         ret = ytphy_write_ext(phydev, YTPHY_MAGIC_PACKET_MAC_ADDR1,
  255.                 ((p_attached_dev->dev_addr[2] << 8) |
  256.                  p_attached_dev->dev_addr[3]));
  257.         if (ret < 0)
  258.             return ret;
  259.         ret = ytphy_write_ext(phydev, YTPHY_MAGIC_PACKET_MAC_ADDR0,
  260.                 ((p_attached_dev->dev_addr[4] << 8) |
  261.                  p_attached_dev->dev_addr[5]));
  262.         if (ret < 0)
  263.             return ret;
  264.     } else {
  265.         wol_cfg.enable = 0; //disable
  266.         wol_cfg.type = YTPHY_WOL_TYPE_MAX;
  267.         wol_cfg.width = YTPHY_WOL_WIDTH_MAX;
  268.         ret = ytphy_wol_en_cfg(phydev, wol_cfg);
  269.         if (ret < 0)
  270.             return ret;
  271.     }
  272.  
  273.     /* Recover to previous register space page */
  274.     ret = ytphy_switch_reg_space(phydev, pre_page);
  275.     if (ret < 0)
  276.         return ret;
  277.  
  278.     return 0;
  279. }
  280. #endif /*(YTPHY_ENABLE_WOL)*/
  281.  
  282. static int yt8521_config_init(struct phy_device *phydev)
  283. {
  284.     int ret;
  285.     int val;
  286.  
  287.     phydev->irq = PHY_POLL;
  288.  
  289.     ytphy_write_ext(phydev, 0xa000, 0);
  290.     ret = genphy_config_init(phydev);
  291.     if (ret < 0)
  292.         return ret;
  293.  
  294.     /* disable auto sleep */
  295.     val = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1);
  296.     if (val < 0)
  297.         return val;
  298.  
  299.     val &= (~BIT(YT8521_EN_SLEEP_SW_BIT));
  300.  
  301.     ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, val);
  302.     if (ret < 0)
  303.         return ret;
  304.  
  305.     /* enable RXC clock when no wire plug */
  306.     ret = ytphy_write_ext(phydev, 0xa000, 0);
  307.     if (ret < 0)
  308.         return ret;
  309.  
  310.     val = ytphy_read_ext(phydev, 0xc);
  311.     if (val < 0)
  312.         return val;
  313.     val &= ~(1 << 12);
  314.     ret = ytphy_write_ext(phydev, 0xc, val);
  315.     if (ret < 0)
  316.         return ret;
  317.  
  318.     //printk("8521 init call out...\n");
  319.     return ret;
  320. }
  321.  
  322. static int yt8521_adjust_status(struct phy_device *phydev, int val, int is_utp)
  323. {
  324.     int speed_mode, duplex;
  325.     int speed = SPEED_UNKNOWN;
  326.  
  327.     //printk("8521 status adjust call in...\n");
  328.     duplex = (val & YT8512_DUPLEX) >> YT8521_DUPLEX_BIT;
  329.     speed_mode = (val & YT8521_SPEED_MODE) >> YT8521_SPEED_MODE_BIT;
  330.     switch (speed_mode) {
  331.     case 0:
  332.         if (is_utp)
  333.             speed = SPEED_10;
  334.         break;
  335.     case 1:
  336.         speed = SPEED_100;
  337.         break;
  338.     case 2:
  339.         speed = SPEED_1000;
  340.         break;
  341.     case 3:
  342.         break;
  343.     default:
  344.         speed = SPEED_UNKNOWN;
  345.  
  346.         break;
  347.     }
  348.  
  349.     phydev->speed = speed;
  350.     phydev->duplex = duplex;
  351.  
  352.     //printk("8521 status adjust call out,regval=0x%04x,mode=%s,speed=%dm...\n", val,is_utp?"utp":"fiber", phydev->speed);
  353.     return 0;
  354. }
  355.  
  356. int yt8521_aneg_done (struct phy_device *phydev)
  357. {
  358.     //printk("phy..YT8521 AN_done callin,speed=%dm,linkmoded=%d\n", phydev->speed,link_mode_8521);
  359.  
  360.     if ((32 == link_mode_8521) && (SPEED_100 == phydev->speed))
  361.     {
  362.         return 1/*link_mode_8521*/;
  363.     }
  364.  
  365.     return genphy_aneg_done(phydev);
  366. }
  367.  
  368. static int yt8521_read_status(struct phy_device *phydev)
  369. {
  370.     int ret;
  371.     volatile int val;
  372.     volatile int link;
  373.     int link_utp = 0;
  374.  
  375.     /* reading UTP */
  376.     ret = ytphy_write_ext(phydev, 0xa000, 0);
  377.     if (ret < 0)
  378.         return ret;
  379.  
  380.     val = phy_read(phydev, REG_PHY_SPEC_STATUS);
  381.     if (val < 0)
  382.         return val;
  383.  
  384.     link = val & (BIT(YT8521_LINK_STATUS_BIT));
  385.     if (link) {
  386.         link_utp = 1;
  387.         link_mode_8521 = 1;
  388.         yt8521_adjust_status(phydev, val, 1);
  389.     } else {
  390.         link_utp = 0;
  391.     }
  392.  
  393.     if (link_utp) {
  394.         phydev->link = 1;
  395.     } else {
  396.         phydev->link = 0;
  397.         link_mode_8521 = 0;
  398.     }
  399.  
  400.     if (link_utp) {
  401.         ytphy_write_ext(phydev, 0xa000, 0);
  402.     }
  403.  
  404.     //printk("8521 read status call out, link=%d, linkmode=%d\n", phydev->link, link_mode_8521 );
  405.  
  406.     return 0;
  407. }
  408.  
  409. int yt8521_suspend(struct phy_device *phydev)
  410. {
  411. #if !(SYS_WAKEUP_BASED_ON_ETH_PKT)              
  412.     int value;
  413.  
  414. #if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
  415.     mutex_lock(&phydev->lock);
  416. #else
  417.     /* no need lock in 4.19 */
  418. #endif
  419.  
  420.     ytphy_write_ext(phydev, 0xa000, 0);
  421.     value = phy_read(phydev, MII_BMCR);
  422.     phy_write(phydev, MII_BMCR, value | BMCR_PDOWN);
  423.  
  424.     ytphy_write_ext(phydev, 0xa000, 2);
  425.     value = phy_read(phydev, MII_BMCR);
  426.     phy_write(phydev, MII_BMCR, value | BMCR_PDOWN);
  427.  
  428.     ytphy_write_ext(phydev, 0xa000, 0);
  429.  
  430. #if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
  431.     mutex_unlock(&phydev->lock);
  432. #else
  433.     /* no need lock/unlock in 4.19 */
  434. #endif
  435. #endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/               
  436.  
  437.     return 0;
  438. }
  439.  
  440. int yt8521_resume(struct phy_device *phydev)
  441. {
  442. #if !(SYS_WAKEUP_BASED_ON_ETH_PKT)              
  443.     int value;
  444.  
  445. #if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
  446.     mutex_lock(&phydev->lock);
  447. #else
  448.     /* no need lock/unlock in 4.19 */
  449. #endif
  450.  
  451.     ytphy_write_ext(phydev, 0xa000, 0);
  452.     value = phy_read(phydev, MII_BMCR);
  453.     phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
  454.  
  455.     ytphy_write_ext(phydev, 0xa000, 2);
  456.     value = phy_read(phydev, MII_BMCR);
  457.     phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
  458.  
  459.     ytphy_write_ext(phydev, 0xa000, 0);
  460.  
  461. #if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
  462.     mutex_unlock(&phydev->lock);
  463. #else
  464.     /* no need lock/unlock in 4.19 */
  465. #endif
  466. #endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/               
  467.  
  468.     return 0;
  469. }
  470.  
  471. static struct phy_driver ytphy_drvs[] = {
  472.     {
  473.         /* same as 8521 */
  474.         .phy_id         = PHY_ID_YT8531S,
  475.         .name           = "YT8531S Ethernet",
  476.         .phy_id_mask    = MOTORCOMM_PHY_ID_MASK,
  477.         .features       = PHY_BASIC_FEATURES | PHY_GBIT_FEATURES,
  478.         .flags          = PHY_POLL,
  479.         .soft_reset     = yt8521_soft_reset,
  480.         .config_aneg    = genphy_config_aneg,
  481.         .aneg_done      = yt8521_aneg_done,
  482.         .config_init    = yt8521_config_init,
  483.         .read_status    = yt8521_read_status,
  484.         .suspend        = yt8521_suspend,
  485.         .resume         = yt8521_resume,
  486. #if (YTPHY_ENABLE_WOL)
  487.         .get_wol        = &ytphy_get_wol,
  488.         .set_wol        = &ytphy_set_wol,
  489. #endif                
  490.     } 
  491. };
  492.  
  493. module_phy_driver(ytphy_drvs);
  494.  
  495. MODULE_DESCRIPTION("Motorcomm PHY driver");
  496. MODULE_AUTHOR("Leilei Zhao");
  497. MODULE_LICENSE("GPL");
  498.  
  499. static struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
  500.     { PHY_ID_YT8010, MOTORCOMM_PHY_ID_MASK },
  501.     { PHY_ID_YT8510, MOTORCOMM_PHY_ID_MASK },
  502.     { PHY_ID_YT8511, MOTORCOMM_PHY_ID_MASK },
  503.     { PHY_ID_YT8512, MOTORCOMM_PHY_ID_MASK },
  504.     { PHY_ID_YT8512B, MOTORCOMM_PHY_ID_MASK },
  505.     { PHY_ID_YT8521, MOTORCOMM_PHY_ID_MASK },
  506.     { PHY_ID_YT8531S, MOTORCOMM_PHY_ID_MASK },
  507.     { PHY_ID_YT8531, MOTORCOMM_PHY_ID_MASK },
  508.     { PHY_ID_YT8618, MOTORCOMM_MPHY_ID_MASK },
  509.     { PHY_ID_YT8614, MOTORCOMM_MPHY_ID_MASK_8614 },
  510.     { }
  511. };
  512.  
  513. MODULE_DEVICE_TABLE(mdio, motorcomm_tbl);

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