Verilog中的Latch_verilog latch

Latch介绍

功能描述

• Latches are level-sensitive (not edge-sensitive) circuits, so in an always block, they use level-sensitive sensitivity lists.
• However, they are still sequential elements, so should use non-blocking assignments.
• A D-latch acts like a wire (or non-inverting buffer) when enabled, and preserves the current value when disabled.

---

代码实现

module top_module (
    input d, 
    input ena,
    output q);
    assign q=(ena)?d:q;
endmodule
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生成电路

---

module top_module (
    input d, 
    input ena,
    output reg q);
    
    always @(*)begin
        q <= (ena) ? d : q;
    end  
endmodule
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生成电路

---

module top_module (
    input d, 
    input ena,
    output reg q);
    
    always @(*)begin
        q = (ena) ? d : q;
    end  
endmodule
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生成电路

---

总结

可以看出上述3种描述方式生成最终电路是相同的。