windows XP下 iverilog+GTKWave使用（二）_windows verilog

上回讲了iverilog的helloworld版的程序，接下来就讲讲以个计数器的仿真以编译，

首先编写一个counter.v的文件，如下：

module counter(out, clk, reset);
    parameter WIDTH = 8;
    
    output [WIDTH-1 : 0] out;
    input                clk, reset;
    
    reg [WIDTH-1 :0 ] out;
    wire              clk, reset;
    
    always @(posedge clk)
        out <= out + 1;
    
    always @reset
        if (reset)
            assign out = 0;
        else
            deassign out;
endmodule
//counter

其次在编写一个激励文件counter_tb.v，如下：

`timescale 1ns/1ns
module test;
 
    /*Make a reset that pulses once.*/
	reg reset = 0;
	
	initial
		begin
			#17 reset = 1;
			#11 reset = 0;
			#29 reset = 1;
			#11 reset = 0;
			#100 $stop;
		end
	
	/*Make a regular pulsing closk*/
	
	reg clk = 0;
	always #5 clk = !clk;
	
	wire [7:0] value;
	counter c1 (value, clk, reset);
	
	initial
		$monitor("At time %t, value = %h (%0d)",$time, value, value);
endmodule
//test

具体的语法大家去看书啦，这里就不多说了，哈哈！
ok，接下来就是编译了，运用下面的语句：
> iverilog -o my_design  counter_tb.v counter.v
这是会在当前目录下生产一个my_design的文件，默认是vvp格式的文件，
然后再用vvp来运行my_design，
运行结果是：
>vvp mydesign
At time                    0, value = xx (x)
At time                   17, value = 00 (0)
At time                   35, value = 01 (1)
At time                   45, value = 02 (2)
At time                   55, value = 03 (3)
At time                   57, value = 00 (0)
At time                   75, value = 01 (1)
At time                   85, value = 02 (2)
At time                   95, value = 03 (3)
At time                  105, value = 04 (4)
At time                  115, value = 05 (5)
At time                  125, value = 06 (6)
At time                  135, value = 07 (7)
At time                  145, value = 08 (8)
At time                  155, value = 09 (9)
At time                  165, value = 0a (10)
** VVP Stop(0) **
** Flushing output streams.
** Current simulation time is 168 ticks.
> finish

** Continue **

这里要是没有finish的命令，vvp会一直运行，如果用下面的语句：
>vvp -n mydesign
G:\Verilog HDL\iverilog\Demo\counter>vvp -n mydesign
At time                    0, value = xx (x)
At time                   17, value = 00 (0)
At time                   35, value = 01 (1)
At time                   45, value = 02 (2)
At time                   55, value = 03 (3)
At time                   57, value = 00 (0)
At time                   75, value = 01 (1)
At time                   85, value = 02 (2)
At time                   95, value = 03 (3)
At time                  105, value = 04 (4)
At time                  115, value = 05 (5)
At time                  125, value = 06 (6)
At time                  135, value = 07 (7)
At time                  145, value = 08 (8)
At time                  155, value = 09 (9)
At time                  165, value = 0a (10)

G:\Verilog HDL\iverilog\Demo\counter>
这样就避免了上面的尴尬局面，不过以后还要继续学习vvp。

附：这里介绍了两个命令的重要性和使用原理：
The "iverilog" and "vvp" commands are the most important commands available to users of Icarus Verilog. The
"iverilog" command is the compiler, and the "vvp" command is the simulation runtime engine. What sort of output the
compiler actually creates is controlled by command line switches, but normally it produces output in the default vvp
format, which is in turn executed by the vvp program