7系列FPGA内部的block ram资源和原语RAMB18E1深入分析_block ram primitives

我基于自己原来的文章：第一篇——赛灵思的block memory generator用户手册pg058翻译和学习(24)， 主要介绍Selectable Memory Algorithm；第二篇——赛灵思的block memory generator用户手册pg058翻译和学习(25)， 主要介绍Table 3-1: Memory Primitives Used Based on Architecture (Supported in Native BMG)，延伸一下，反刍和复盘。

结合csdn上搜到的一篇文章：FPGA-7系列FPGA内部结构值Memory Resources-01-block RAM资源 （作者Vuko-wxh），重新了解blockram的两种资源模块/原语primitives: 36kb和18kb.（这篇是讲block ram的）

引申查到的文章：csdn作者摆渡沧桑 浅谈XILINX FPGA CLB单元之分布式RAM（Distributed RAM Available in SLICEM Only、RAM128X1D、Verilog原语描述），这篇是讲分布式ram的，也就是distributed ram,这里便于理解原语是怎么使用的。这里常用的ram原语是RAM32X1S，比下面举例的RAMB18E1要小）

ug473第一章 7系列FPGA内部的block ram资源
block ram资源模块有两种：36kb和18kb （具体总的block RAM 资源有多少? K7325T总共有16M bit的Block RAM）
每个36kb可以配置成4kx9 2kx18等简单双口模式
每个18kb可以配置成2kx9 1kx18等简单双口模式
原语RAMB18E1这是直接用吗？和图形向导生成IP有什么异同？

Block RAM 库原语
7 系列 FPGA 的 Block RAM 库原语 RAMB18E1 和 RAMB36E1 是所有 Block RAM 配置的基本构建块。其他块 RAM 原语和宏基于这些原语。某些 Block RAM 属性只能使用这些原语之一进行配置（例如，流水线寄存器、级联）。请参见 Block RAM 属性部分。

输入和输出数据总线由 9 位宽度 (8 + 1)、18 位宽度 (16 + 2) 和 36 位宽度 (32 + 4) 配置的两条总线表示。与每个字节相关的第九位可以存储奇偶校验/纠错位或用作附加数据位。第 9 位不执行特定功能。奇偶校验位的单独总线有助于某些设计。但是，其他设计通过将常规数据总线与奇偶校验总线合并来安全地使用 9 位、18 位或 36 位总线。所有位的读/写和存储操作都是相同的，包括奇偶校验位。
图片

附，原语RAMB18E1本身的代码：
K7 verilog 版

/ RAMB18E1  : In order to incorporate this function into the design,

// Verilog  : the following instance declaration needs to be placed

// instance  : in the body of the design code. The instance name

// declaration : (RAMB18E1_inst) and/or the port declarations within the

// code    : parenthesis may be changed to properly reference and

// : connect this function to the design.  All inputs

// : and outputs must be connected.

// <-----Cut code below this line---->

// RAMB18E1: 18K-bit Configurable Synchronous Block RAM

//          Kintex-7

// Xilinx HDL Language Template, version 2017.4

RAMB18E1 #(

// Address Collision Mode: "PERFORMANCE" or "DELAYED_WRITE"

.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),

// Collision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")

.SIM_COLLISION_CHECK("ALL"),

// DOA_REG, DOB_REG: Optional output register (0 or 1)

.DOA_REG(0),

.DOB_REG(0),

// INITP_00 to INITP_07: Initial contents of parity memory array

.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),

// INIT_00 to INIT_3F: Initial contents of data memory array

.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),

// INIT_A, INIT_B: Initial values on output ports

.INIT_A(18'h00000),

.INIT_B(18'h00000),

// Initialization File: RAM initialization file

.INIT_FILE("NONE"),

// RAM Mode: "SDP" or "TDP"

.RAM_MODE("TDP"),

// READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port

.READ_WIDTH_A(0),                                                                // 0-72

.READ_WIDTH_B(0),                                                                // 0-18

 .WRITE_WIDTH_A(0),                                                               // 0-18

.WRITE_WIDTH_B(0),                                                               // 0-72

// RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")

.RSTREG_PRIORITY_A("RSTREG"),

.RSTREG_PRIORITY_B("RSTREG"),

// SRVAL_A, SRVAL_B: Set/reset value for output

.SRVAL_A(18'h00000),

.SRVAL_B(18'h00000),

// Simulation Device: Must be set to "7SERIES" for simulation behavior

.SIM_DEVICE("7SERIES"),

// WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")

.WRITE_MODE_A("WRITE_FIRST"),

.WRITE_MODE_B("WRITE_FIRST")

)

RAMB18E1_inst (

// Port A Data: 16-bit (each) output: Port A data

.DOADO(DOADO),                 // 16-bit output: A port data/LSB data

.DOPADOP(DOPADOP),             // 2-bit output: A port parity/LSB parity

// Port B Data: 16-bit (each) output: Port B data

.DOBDO(DOBDO),                 // 16-bit output: B port data/MSB data

.DOPBDOP(DOPBDOP),             // 2-bit output: B port parity/MSB parity

// Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals (read port

// when RAM_MODE="SDP")

.ADDRARDADDR(ADDRARDADDR),     // 14-bit input: A port address/Read address

.CLKARDCLK(CLKARDCLK),         // 1-bit input: A port clock/Read clock

.ENARDEN(ENARDEN),             // 1-bit input: A port enable/Read enable

.REGCEAREGCE(REGCEAREGCE),     // 1-bit input: A port register enable/Register enable

.RSTRAMARSTRAM(RSTRAMARSTRAM), // 1-bit input: A port set/reset

.RSTREGARSTREG(RSTREGARSTREG), // 1-bit input: A port register set/reset

.WEA(WEA),                     // 2-bit input: A port write enable

// Port A Data: 16-bit (each) input: Port A data

.DIADI(DIADI),                 // 16-bit input: A port data/LSB data

.DIPADIP(DIPADIP),             // 2-bit input: A port parity/LSB parity

// Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals (write port

// when RAM_MODE="SDP")

.ADDRBWRADDR(ADDRBWRADDR),     // 14-bit input: B port address/Write address

  .CLKBWRCLK(CLKBWRCLK),         // 1-bit input: B port clock/Write clock

.ENBWREN(ENBWREN),             // 1-bit input: B port enable/Write enable

.REGCEB(REGCEB),               // 1-bit input: B port register enable

.RSTRAMB(RSTRAMB),             // 1-bit input: B port set/reset

.RSTREGB(RSTREGB),             // 1-bit input: B port register set/reset

.WEBWE(WEBWE),                 // 4-bit input: B port write enable/Write enable

// Port B Data: 16-bit (each) input: Port B data

.DIBDI(DIBDI),                 // 16-bit input: B port data/MSB data

.DIPBDIP(DIPBDIP)              // 2-bit input: B port parity/MSB parity

);

// End of RAMB18E1_inst instantiation


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