2021-06-26_damiano and rabbit model within simulink

1.实验目的：
下载Quartur ii软件和modlsim并进行联合仿真。

2.实验内容：
参照书本上的代码，然后用quartus ii和modlsim进行联合仿真

3.实验原理：按照视频上的内容，书写和运行代码，完成联合仿真操作。
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4实验工具：
pc机和Quartur ii软件和modlsim软件。

5.实验截图：

6.实验视频：

请下载哔哩哔哩动画打开此网址：
https://www.bilibili.com/video/BV17K4y1M7uR/

【VerilogHDL高级数字设计（第二版）P183 例6.27-哔哩哔哩】
7.实验代码：
module Seq_Rec_3_1s_Mealy(output D_out, input D_in, En, clk, reset);

parameter S_idle=2’d0,
S_0= 2’d1,

              S_1= 2'd2,

              S_2= 2'd3,

              S_3= 2'd4;
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reg [1:0] state, next_state;
reg D_out_reg;
always@(negedge clk)
if (reset1) D_out_reg<=0;
else D_out_reg<=((resetS_2)&&(D_in==1));

always @ (negedge clk)

if (reset==1) state<= S_idle; else state <= next_state;

always @ (state, En, D_in)

begin

next_state=S_idle;

case(state)

S_idle: if ((En1)&&(D_in 1)) next_state=S_1;

                    else if((En== 1)&&(D_in== 0))  next_state=S_0;
                    else                          next_state= S_idle;
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S_0: if(D_in==0) next_state= S_0;

                        else if(D_in== 1)             next_state=S_1;
                        else                        next_state=S_idle;
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S_1: if(D_in== 0) next_state=S_0;

                      else if(D_in== 1)           next_state=S_2;

                     else                      next_state = S_idle;
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S_2: if(D_in==0) next_state=S_0;

                        else if(D_in==1)                   next_state=S_2;

                           else                             next_state= S_idle;
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default: next_state= S_idle;

endcase

end

assign D_out= ((stateS_2)&&(D_in1 ));
endmodule

module Seq_Rec_3_1s_Moore(output D_out, input D_in, En, clk, reset);

parameter S_idle = 3’d0,

              S_0= 3'd1,

              S_1=3'd2,

              S_2= 3'd3,

              S_3=3'd4;
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reg [2:0] state, next_state;
reg D_out_reg;
always@(negedge clk)
if(reset1)D_out_reg<=0;
else D_out_reg<=((stateS_2)&&(next_stateS_2)&&(D_in1));

always @ (negedge clk)

if(reset== 1) state <=S_idle; else state <= next_state;

always @ (state, En, D_in)

begin

case (state)

S_idle: if((En== 1)&&(D_in== 1)) next_state=S_1;

else

if((En== 1)&&(D_in== 0)) next_state=S_0;

   else next_state= S_idle;

   S_0:  if(D_in== 0) next_state=S_0; else

        if(D_in== 1) next_state=S_1;

                                       else 
                                      next_state=S_idle;

       S_1: if(D_in== 0)  next_state=S_0; else

           if(D_in== 1) next_state=S_2; else 
                                 next_state= S_idle;

       S_2,S_3: if(D_in==0) next_state=S_0; else
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if(D_in== 1) next_state=S_3;

else next_state= S_idle;

default: next_state= S_idle;

endcase
end

assign D_out= (state==S_3);

endmodule

8.软件下载网站：
1.复制这段内容后打开百度网盘App，操作更方便哦。 链接:https://pan.baidu.com/s/1ZT0ovNAAZ_j3jTGzVCYfbQ
提取码：5jf2
2.复制这段内容后打开百度网盘App，操作更方便哦。 链接:https://pan.baidu.com/s/1bkD2-5Gwl1HB6y9hkUF14A 提取码:540y