基于FPGA的数字跑表设计VHDL开发包含仿真_基于fpga的数字跑表设计与仿真

部分参考代码

(末尾附文件)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity JSQ is
	port(
			clk:			in		std_logic;
			reset_n:		in		std_logic;
			
			start:		in		std_logic;
			save:			in		std_logic;
			show:			in		std_logic;
			
			start_led:	out	std_logic;
			save_led:	out	std_logic;
			show_led:	out	std_logic;
		
			bee:			out	std_logic;
			
			sm_db_0:		out	std_logic_vector(6 downto 0);		--数码管位选
			sm_db_1:		out	std_logic_vector(6 downto 0);		--数码管位选
			sm_db_2:		out	std_logic_vector(6 downto 0);		--数码管位选
			sm_db_3:		out	std_logic_vector(6 downto 0)		--数码管位选
		);
end JSQ;

architecture rtl of JSQ is

component Counter_1ms is
	port(
		clk:			in		std_logic;
		reset_n:		in		std_logic;
		clk_1ms:		out	std_logic
		);
end component;

component Control is
	port(	
		clk:		in		std_logic;
		reset_n:	in		std_logic;
		key:		in		std_logic_vector(2 downto 0);
		
		start:	out	std_logic;
		save:		out	std_logic;
		show:		out	std_logic;
		
		start_led:	out	std_logic;
		save_led:	out	std_logic;
		show_led:	out	std_logic;
			
		fmq:		out	std_logic
		);
end component;

signal clk_1ms_temp:std_logic;

signal clk_100us_cnt:std_logic_vector(11 downto 0);
signal clk_100us_tmp:std_logic;

signal start_r:std_logic;
signal save_r:std_logic;
signal show_r:std_logic;

signal start_led_r:std_logic;
signal save_led_r:std_logic;
signal show_led_r:std_logic;

signal bee_r:std_logic;

signal key_r:std_logic_vector(2 downto 0);

signal cnt_ms_ge:std_logic_vector(3 downto 0);
signal cnt_ms_shi:std_logic_vector(3 downto 0);
signal cnt_s_ge:std_logic_vector(3 downto 0);
signal cnt_s_shi:std_logic_vector(3 downto 0);

signal scan_cnt:std_logic_vector(3 downto 0);
signal data_0: std_logic_vector(3 downto 0);
signal data_1: std_logic_vector(3 downto 0);
signal data_2: std_logic_vector(3 downto 0);
signal data_3: std_logic_vector(3 downto 0);

signal start_data:std_logic;
signal save_data:std_logic;
signal show_data:std_logic;

--纪录第一组数据
signal cnt_ms_ge_1:std_logic_vector(3 downto 0);
signal cnt_ms_shi_1:std_logic_vector(3 downto 0);
signal cnt_s_ge_1:std_logic_vector(3 downto 0);
signal cnt_s_shi_1:std_logic_vector(3 downto 0);

--纪录第二组数据
signal cnt_ms_ge_2:std_logic_vector(3 downto 0);
signal cnt_ms_shi_2:std_logic_vector(3 downto 0);
signal cnt_s_ge_2:std_logic_vector(3 downto 0);
signal cnt_s_shi_2:std_logic_vector(3 downto 0);

--纪录第三组数据
signal cnt_ms_ge_3:std_logic_vector(3 downto 0);
signal cnt_ms_shi_3:std_logic_vector(3 downto 0);
signal cnt_s_ge_3:std_logic_vector(3 downto 0);
signal cnt_s_shi_3:std_logic_vector(3 downto 0);

--送去显示数据
signal show_cnt_ms_ge:std_logic_vector(3 downto 0);
signal show_cnt_ms_shi:std_logic_vector(3 downto 0);
signal show_cnt_s_ge:std_logic_vector(3 downto 0);
signal show_cnt_s_shi:std_logic_vector(3 downto 0);

signal save_cnt:std_logic_vector(1 downto 0);
signal show_cnt:std_logic_vector(1 downto 0);

begin

	u1:	Counter_1ms port map(clk,reset_n,clk_1ms_temp);
	u2:	Control port map(clk,reset_n,key_r, start_r, save_r, show_r,start_led_r,save_led_r, show_led_r,bee_r);
	
	key_r <= start & save & show;
	
	start_led <= start_led_r;
	save_led <= save_led_r;
	show_led <= show_led_r;
	
	bee <= bee_r;
	
	process(start_r, save_r, show_r,reset_n)
	begin
		if(reset_n = '0') then
			start_data <= '0';
			save_data <= '0';
			show_data <= '0';
		else
			if(start_r = '1') then
				start_data <= '1';
			end if;

			if(save_r = '1') then
				save_data <= '1';
			end if;

			if(show_r = '1') then
				show_data <= '1';
			end if;			
		end if;
	end process;
	
	process(clk,reset_n)
	begin
		if(reset_n = '0') then
			save_cnt <= "00";
		elsif(clk'event and clk = '1') then
			if(save_r = '1') then
				save_cnt <= save_cnt + '1';
				if(save_cnt = X"11") then
					save_cnt <= "00";
				end if;
			end if;
		end if;
	end process;
	
	process(clk,reset_n)
	begin
		if(reset_n = '0') then
			show_cnt <= "00";
		elsif(clk'event and clk = '1') then
			if(show_r = '1') then
				show_cnt <= show_cnt + '1';
				if(show_cnt = X"11") then
					show_cnt <= "00";
				end if;
			end if;
		end if;
	end process;
	
	process(clk,reset_n)
	begin
		if(reset_n = '0') then
			cnt_ms_ge_1 <= (others => '0');
			cnt_ms_shi_1 <= (others => '0');
			cnt_s_ge_1 <= (others => '0');
			cnt_s_shi_1 <= (others => '0');
			
			cnt_ms_ge_2 <= (others => '0');
			cnt_ms_shi_2 <= (others => '0');
			cnt_s_ge_2 <= (others => '0');
			cnt_s_shi_2 <= (others => '0');
			
			cnt_ms_ge_3 <= (others => '0');
			cnt_ms_shi_3 <= (others => '0');
			cnt_s_ge_3 <= (others => '0');
			cnt_s_shi_3 <= (others => '0');
		elsif(clk'event and clk = '1') then
			if(save_r = '1') then
				case save_cnt is
					when "00"	=>
					
						cnt_ms_ge_1 <= cnt_ms_ge;
						cnt_ms_shi_1 <= cnt_ms_shi;
						cnt_s_ge_1 <= cnt_s_ge;
						cnt_s_shi_1 <= cnt_s_shi;
					when "01"	=>
						
						cnt_ms_ge_2 <= cnt_ms_ge;
						cnt_ms_shi_2 <= cnt_ms_shi;
						cnt_s_ge_2 <= cnt_s_ge;
						cnt_s_shi_2 <= cnt_s_shi;
					when "10"	=>					
						cnt_ms_ge_3 <= cnt_ms_ge;
						cnt_ms_shi_3 <= cnt_ms_shi;
						cnt_s_ge_3 <= cnt_s_ge;
						cnt_s_shi_3 <= cnt_s_shi;
						
					when others		=>
						null;
				end case;
			end if;
		end if;
	end process;
	
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链接：https://pan.baidu.com/s/158kXjI33oGnP0A_yF1IzFg
提取码：kxu4

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