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1. MUX
- module top_module (
- input sel,
- input [7:0] a,
- input [7:0] b,
- output [7:0] out );
-
- assign out = sel ? a : b;
-
- endmodule
2.NAND
- module top_module (input a, input b, input c, output out);//
-
- wire t;
- andgate inst1 (t,a,b,c,1'b1,1'b1);
- assign out = ~t;
-
- endmodule
3. 4-1MUX
- module top_module (
- input [1:0] sel,
- input [7:0] a,
- input [7:0] b,
- input [7:0] c,
- input [7:0] d,
- output [7:0] out ); //
-
- wire [7:0]m0, m1;
- mux2 mux0 ( sel[0], a, b, m0 );
- mux2 mux1 ( sel[0], c, d, m1 );
- mux2 mux2 ( sel[1], m0, m1, out );
-
- endmodule
4.Add/Sub
- module top_module (
- input do_sub,
- input [7:0] a,
- input [7:0] b,
- output reg [7:0] out,
- output reg result_is_zero
- );//
-
- always @(*) begin
- case (do_sub)
- 0: out = a+b;
- 1: out = a-b;
- endcase
-
- end
- always@(*)
- begin
- if (out == 0)
- result_is_zero = 1;
- else
- result_is_zero = 0;
- end
-
- endmodule
5.Case Statement
- module top_module (
- input [7:0] code,
- output reg [3:0] out,
- output reg valid);//
-
- always @(*) begin
- case (code)
- 8'h45: out = 4'd0;
- 8'h16: out = 4'd1;
- 8'h1e: out = 4'd2;
- 8'h26: out = 4'd3;
- 8'h25: out = 4'd4;
- 8'h2e: out = 4'd5;
- 8'h36: out = 4'd6;
- 8'h3d: out = 4'd7;
- 8'h3e: out = 4'd8;
- 8'h46: out = 4'd9;
- default: out = 4'd0;
- endcase
- if(out == 4'd0 && code != 8'h45)
- valid = 1'b0;
- else
- valid = 1'b1;
- end
-
- endmodule
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