Verilator_assertion failed: verilator invocation failed

https://en.wikipedia.org/wiki/Verilator

https://www.veripool.org/projects/verilator/wiki/Installing

https://www.veripool.org/ftp/verilator_doc.pdf

https://www.veripool.org/wiki/verilator/Manual-verilator

-------------------------------------------------------------------------------------------------------------

Other users have reported the following relative performance on their designs: (Note they seem contradictory, as they refer to differing designs.)

• Verilator is 90x faster than Icarus Verilog.
• Verilator is 10-40x faster than Modelsim SE.
• Verilator is 3x faster than NC-Verilog.
• Verilator is 1.5x faster than VCS.
• VTOC is 4x faster than Verilator.
• VTOC is 50x faster than NC-Verilog.
• VCS is 3x faster than Verilator.
• VCS is 3x faster than NC-Verilog.
• VCS is 10x faster than NC-Verilog.
• VCS is the same speed as NC-Verilog.
• CVer is the same speed as Icarus Verilog.

--------------------------------------------------------------------------------

Icarus 就是iverilog

http://iverilog.icarus.com/

http://bleyer.org/icarus/

https://segmentfault.com/a/1190000011059615

windows下安装：

https://www.cnblogs.com/goco/p/11399799.html

https://zhuanlan.zhihu.com/p/33443736

仿真步骤：

所需文件是4个，准备3个文件及仿真工程：

Makefile文件：

#*****************************************************************************
#
# DESCRIPTION: Verilator Example: Makefile for inside source directory
#
# This calls the object directory makefile.  That allows the objects to
# be placed in the "current directory" which simplifies the Makefile.
#
# Copyright 2003-2017 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
#
#****************************************************************************/
 
default: show_config test_default
 
# This must point to the root of the VERILATOR kit
#VERILATOR_ROOT := $(shell pwd)/..
#export VERILATOR_ROOT
 
CURRENT_PATH := $(shell pwd)
 
 
# Pick up PERL and other variable settings
include $(VERILATOR_ROOT)/include/verilated.mk
 
DEBUG_QUIET = --debug --debugi 0 --gdbbt --no-dump-tree
DEBUG_ON = --debug --trace-dups --gdbbt
#DEBUG = $(DEBUG_ON)
VALGRIND_ON = $(DEBUG_ON) --gdb "valgrind -v --leak-check=yes"
 
######################################################################
test_default:   prep     compile run wave
test_debug:     prep_dbg compile run
test_valgrind:  prep_vg  compile run
 
#VERILATOR_FLAGS = --cc -f $(VERILATOR_ROOT)/test_v/input.vc top.v
VERILATOR_FLAGS = --cc -f $(CURRENT_PATH)/input.vc $(CURRENT_PATH)/top.v
VERILATOR_FLAGS += --trace
 
#show_config: Is the very first time we've executed Verilator after building
#so we make sure to run with --gdbbt, so if it dumps we'll get a trace.
show_config:
	$(PERL) $(VERILATOR_ROOT)/bin/verilator $(DEBUG_QUIET) -V
 
#prep: Is the very first time we're running a Verilation
#so we make sure to run with --gdbbt, so if it dumps we'll get a trace.
prep:
	$(PERL) $(VERILATOR_ROOT)/bin/verilator $(DEBUG_QUIET) $(VERILATOR_FLAGS)
prep_dbg:
	$(PERL) $(VERILATOR_ROOT)/bin/verilator $(DEBUG_ON)    $(VERILATOR_FLAGS)
prep_vg:
	$(PERL) $(VERILATOR_ROOT)/bin/verilator $(VALGRIND_ON) $(VERILATOR_FLAGS)
 
compile:
	cd obj_dir ; $(MAKE) -j 3 -f ../Makefile_obj
 
run:
	obj_dir/simx
wave:
	gtkwave $(CURRENT_PATH)/vlt_dump.vcd
######################################################################
 
obj_dir:
	mkdir $@
 
######################################################################
 
maintainer-copy::
clean mostlyclean distclean maintainer-clean::
	-rm -rf obj_dir *.log *.dmp *.vpd core

Sim_main.cpp

// DESCRIPTION: Verilator Example: Top level main for invoking model
//
// Copyright 2003-2017 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
 
#include <verilated.h>		// Defines common routines
#include "Vtop.h"		// From Verilating "top.v"
#if VM_TRACE
# include <verilated_vcd_c.h>	// Trace file format header
#endif
 
Vtop *top;			// Instantiation of module
vluint64_t main_time = 0;	// Current simulation time (64-bit unsigned)
 
double sc_time_stamp () {	// Called by $time in Verilog
    return main_time;		// Note does conversion to real, to match SystemC
}
 
int main(int argc, char **argv, char **env) {
    if (0 && argc && argv && env) {}	// Prevent unused variable warnings
    top = new Vtop;		// Create instance of module
 
    Verilated::commandArgs(argc, argv);
    Verilated::debug(0);
 
#if VM_TRACE			// If verilator was invoked with --trace
    Verilated::traceEverOn(true);	// Verilator must compute traced signals
    VL_PRINTF("Enabling waves...\n");
    VerilatedVcdC* tfp = new VerilatedVcdC;
    top->trace (tfp, 99);	// Trace 99 levels of hierarchy
    tfp->open ("vlt_dump.vcd");	// Open the dump file
#endif
 
    top->rst_n = 0;		// Set some inputs
    top->en = 0;
    top->clk = 0;
  
 
    while (main_time < 60) {
 
	if (main_time == 3) {	// Toggle clock
	    top->rst_n = 1;
	}
	else if(main_time == 6){
		top->en = 1;
	}
	
 
 
 
 
 
	top->eval();		// Evaluate model
#if VM_TRACE
	if (tfp) tfp->dump (main_time);	// Create waveform trace for this timestamp
#endif
 
	// Read outputs
//VL_PRINTF ("[%" VL_PRI64 "d] %x %x %x %x %x_%08x_%08x\n",
//		   main_time, top->clk, top->reset_l, top->passed,
//		   top->out_small, top->out_wide[2], top->out_wide[1], top->out_wide[0]);
 
	top->clk = !top->clk;
	main_time++;		// Time passes...
    }
 
    top->final();
 
#if VM_TRACE
    if (tfp) tfp->close();
#endif
 
   /* if (!top->passed) {
	VL_PRINTF ("A Test failed\n");
	abort();
    } else {
	VL_PRINTF ("All Tests passed\n");
    }
*/
    exit(0L);
}

vc文件：是工程路径包含文件

input.vc

 
+librescan +libext+.v
 -y .
 +incdir+.
 +incdir+$(VERILATOR)/include

mk文件：是编译生成文件

仿真源文件：top.v

//
//
module top(
input clk,
input rst_n,
input en,
output clk_o,
output clk_on
   
);
 
 
clk_div #(
	.PMT_CNTT(16'd1)
)
clk_div_i(
  .clk(clk),
  .rst_n(rst_n),
  .en(en),
  .cnt_o(clk_o),
  .cnt_on(clk_on)
);
 
endmodule

clk_div.v

/* 
 PMT_CNTT = 1 , div 2
  in     clk:_|-|_|-|
	out cnt_o:___|---|
 PMT_CNTT = 2 , div 4
 PMT_CNTT = 3 , div 6
    ：            ：
*/
module clk_div
#(  parameter PMT_CNTT = 16'd2)
(
   input clk,
	input rst_n,
	input en,
	output reg cnt_o,
	output  cnt_on
);
/* verilator lint_off UNSIGNED */
assign cnt_on = ~ cnt_o;
reg[15:0] CNT_REG;
always @ ( posedge clk or negedge rst_n)
 begin 
	 if( (~rst_n) || (~en))
	   begin
         CNT_REG <= 'b0;
	   end
	 else
	   begin 
	     if(CNT_REG < (PMT_CNTT - 16'd1))
		    begin
			  CNT_REG <= CNT_REG + 16'd1;
			 end
		   else
		    begin
		      CNT_REG<='d0; 
			 end
	   end
 end
 
 //
 always @ ( posedge clk or negedge rst_n)
 begin 
	 if( (~rst_n) || (~en))
	   begin
		   cnt_o <= 'b1;
	   end
	 else
	   begin 
	     if(CNT_REG == PMT_CNTT - 16'd1)
		    begin
			   cnt_o <= ~cnt_o;
			 end
		   else
		    begin
		      cnt_o <= cnt_o;
			 end
	   end
 end
 
endmodule

指令说明：