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如何使用FT2232H适配器和开源调式工具OpenOCD对ARM Cortex M7系列MCU进行SWD接口调试_如何使用ft223适配器和开源调试工具 openocd

作者：你好赵伟 | 2024-08-14 12:03:06

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如何使用ft223适配器和开源调试工具 openocd

该篇幅介绍如何使用FT2232H适配器和开源调式工具OpenOCD对ARM Cortex M系列MCU进行SWD接口调试？

如何连接FT2232HL Debuger Adapter和目标板的的SWD调试接口？

从OPENOCD开源代码中 https://sourceforge.net/p/openocd/code/ci/master/tree/tcl/interface/ftdi/swd-resistor-hack.cfg 描述：

线连接方式讲的很清楚。FTDI FT2232D芯片侧TDI和TDO之间连接一个(220~470欧姆的电阻)，然后将TDO连到目标板的SWDIO信号上， TCK连接目标板上的SWCLK信号上。

我们从FT2232D的PIN定义看出实际PIN脚连接如下：

   VCC                                           --> VCC
   (AD0) ADBUS0 (PIN #16)  TCK  --> SWCLK
   (AD2) ADBUS2 (PIN #18)  TDO --> SWDIO
   GND                                          --> GND

Debuger Adapter 和目标板连接好后，接下来我们可以用OPENOCD连上目标板。OPENOCD环境搭建大家可以参考如何搭建OpenOCD环境基于Window10+Cygwin？

如何理解Debuger Adapter和目标板CPU配置文件？

在用OPENOCD接入目标板之前，我们必须准备两个配置文件，一个是FT2232D Debuger Adapter配置文件，一个是目标板的配置文件。你也可以弄成一个配置文件。弄成两个会比较符合OPENOCD的使用。Debuger Adapter一般放在..\scripts\interface\ftdi\目录。目标板的配置文件一般放在..\scripts\target\目录。

  1. #
  2. # Connect TDI to SWDIO via a suitable series resistor (220-470 Ohm or
  3. # so depending on the drive capability of the target and adapter);
  4. # connect TDO directly to SWDIO.
  5. #
  6. # You also need to have reliable GND connection between the target and
  7. # adapter. Vref of the adapter should be supplied with a voltage equal
  8. # to the target's (preferrably connect it to Vcc). You can also
  9. # optionally connect nSRST. Leave everything else unconnected.
  10. #
  11. # FTDI                          Target
  12. # ----                          ------
  13. # 1  - Vref   ----------------- Vcc
  14. # 3  - nTRST  -
  15. # 4  - GND    ----------------- GND
  16. # 5  - TDI    ---/\470 Ohm/\--- SWDIO
  17. # 7  - TMS    -
  18. # 9  - TCK    ----------------- SWCLK
  19. # 11 - RTCK   -
  20. # 13 - TDO    ----------------- SWDIO
  21. # 15 - nSRST  - - - - - - - - - nRESET
  22. #
  23. #
  24. # FTDI FT2232HL
  25. #
  26. # https://ftdichip.com/products/ft2232hl/
  27. #
  28.  
  29. adapter driver ftdi
  30.  
  31. # select swd interface protocol 
  32. transport select swd
  33.  
  34. # FT2232D has two USB Serial Converter A/B VendorID (0x0403)  DeviceID (0x6010)
  35. # USB Serial Converter A ADBUS
  36. # USB Serial Converter B ACBUS
  37.  
  38. ftdi_vid_pid 0x0403 0x6010
  39.  
  40. # ftdi_device_desc description
  41. # 指定调试器的描述符。
  42.  
  43. # ftdi_serial serial-number
  44. # 指定调试器的Serial Number。
  45.  
  46. # ftdi_channel channel
  47. # 指定FTDI设备的Channel。对应FT232H来说，只有Channel 0（默认），FT2232H/FT4232H是Channel 0和Channel 1。
  48.  
  49. adapter speed 1000
  50.  
  51. # ftdi_layout_init [data] [direction]
  52. # 指定FTDI GPIO的初始数据和方向，16bit数据宽度。
  53. # 参数data中1表示高电平，0表示低电平，而参数direction中1表示输出，0表示输入（注意与常规的设定不同）
  54. ftdi_layout_init 0x0018 0x05fb
  55. # This means:              ADBUS(bit7~bit0)
  56. # Low output data = 0x18 // 0001  1000
  57. # Low direction   = 0xfb // 1111  1011
  58. # High direction  = 0x05 // 0000  0101
  59.  
  60. # 默认情况下是JTAG，如果要使用SWD，则需要配置SWD_EN。
  61. ftdi_layout_signal SWD_EN -data 0
  62. # ftdi_layout_signal name [-data|-ndata data_mask] [-input|-ninput input_mask] [-oe|-noe oe_mask] [-alias|-nalias name]
  63. # 创建一个名字为name的信号。
  64. # [-data|-ndata data_mask] 
  65. # data_mask:pin mask ndata:invert -data:normal bit
  66. # data_mask是对应pin脚的掩码，-ndata表示输入数据反向，-data则不反向。
  67. # [-input|-ninput input_mask] 
  68. # input_mask:pin mask -input:input pin enable -ninput:input pin disable
  69. # input_mask：表示对应pin脚是否为输入，-input表示输入，-ninput表示非输入。
  70. # [-oe|-noe oe_mask]  
  71. # oe_mask:pin mask -oe:output pin enable noe:output pin disable
  72. # oe_mask：表示对应pin脚是否为输出，-oe表示输出，-noe表示非输出。
  73. # [-alias|-nalias name] 
  74. # -alias:Normal logic -nalias:Opposite logic
  75. # 如果使用-alias（或-nalias），则创建的信号相同（或数据取反）到已指定的信号名称。
  76.  
  77. ftdi_layout_signal nSRST -data 0x0010
  78.  
  79. # ftdi_set_signal name 0|1|z
  80. # 输出信号
  81. # -0：输出低
  82. # -1：输出高
  83. # -z：设置为高阻态
  84.  
  85. # ftdi_get_signal name
  86. # 读取信号
  87.  
  88. # ftdi_tdo_sample_edge rising|falling
  89. # -rising, TCK上升沿采样TDO，默认
  90. # -falling, TCK下降沿采样TDO

在ftdi_ft2232d.cfg文件中注释已经很清楚的介绍了每条针对debuger adatper的配置命令。

  1. 下面是我写的目标板的配置文件nxp_s32k3x4.cfg
  2. # script for s32k3xx family
  3. #
  4. # s32k3xx devices support both JTAG and SWD transports.
  5. # 下面两个文件是必须的因为涉及到JTAG 和 SWD 接口通用，即使你由SWD换成了JTAG方式一下脚本一样支持
  6. source [find target/swj-dp.tcl]
  7. source [find mem_helper.tcl]
  8.  
  9. # 如果芯片名不存在使用s32k3xx为芯片名
  10. if { [info exists CHIPNAME] } {
  11.    set _CHIPNAME $CHIPNAME
  12. } else {
  13.    set _CHIPNAME s32k3xx
  14. }
  15.  
  16. # 设置芯片大小端格式
  17.    set _ENDIAN little
  18.  
  19. # 为加载RAM BIOS ELF文件,设置256KB的RAM空间并且准备清零
  20. # Work-area is a space in RAM used for flash programming
  21. # By default use 256kB
  22. if { [info exists WORKAREASIZE] } {
  23.    set _WORKAREASIZE $WORKAREASIZE
  24. } else {
  25.    set _WORKAREASIZE 0x40000
  26. }
  27.  
  28. # 检查芯片的DAP/TAP的ID是否是0x6ba00477, Cortex M7的DAP ID统一为0x6ba00477
  29. #jtag scan chain
  30. if { [info exists CPUTAPID] } {
  31.    set _CPUTAPID $CPUTAPID
  32. } else {
  33.    if { [using_jtag] } {
  34.       # See STM Document RM0385
  35.       # Section 40.6.3 - corresponds to Cortex-M7 with FPU r1p2
  36.       set _CPUTAPID 0x6ba00477
  37.    } {
  38.       set _CPUTAPID 0x6ba02477
  39.    }
  40. }
  41.  
  42. # 检测_CPUTAPID是不是0x6ba02477，如果是创建芯片的DAP,创建DAP接口后便可以通过DAP访问芯片所有AP接口寄存器。
  43. swj_newdap $_CHIPNAME armv7m -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  44. dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.armv7m
  45.  
  46. if {[using_jtag]} {
  47.    jtag newtap $_CHIPNAME bs -irlen 5
  48. }
  49.  
  50. global TARGET
  51.  
  52. set TARGET       $_CHIPNAME.armv7m
  53. set TARGET_MEMAP $_CHIPNAME.memap
  54.  
  55. # 创建芯片 Target,这个过程中通过DAP接口搜索所有AP。
  56. # 由于NXP S32K344存在多cortex_m 内核互联的MEM AP.会导致target_examine失败。
  57. # 因为我知道S32K344的Cortex M7 core 0的MEM AP为4，所以我指定检索-ap-num 4
  58. target create ${TARGET}.cm7_0    cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 4 -coreid 0
  59.  
  60. # 必须init target相关的dap mmw mdw 才能在脚本成功被调用,不然后报错。
  61. init
  62.  
  63. # 我在ftdi_ft2232d.cfg中,我设定了ADBUS4管脚为目标板的硬件RST
  64. # 硬件复位
  65. ftdi_set_signal nSRST 0
  66. # 延时100ms
  67. adapter srst delay 100
  68. # 硬件解复位
  69. ftdi_set_signal nSRST 1
  70.  
  71. # 注意：由于S32K344的debug 模式不是默认开启，需要通过DAP访问SDA-AP使能Debug模式
  72. # 如果不使能DAP是无法接入Cortex M7 core 0的MEM AP
  73. # Enable Cortex-M7 Core0 debug request
  74. s32k3xx.dap  apreg 7 0x80 0x300000f0
  75.  
  76. # 复位Cortex-M7 Core0内部寄存器配置
  77. cortex_m reset_config sysresetreq
  78. cortex_m reset_config vectreset
  79.  
  80. # 启动调试模式，让Cortex-M7 Core0 halt等待下面得加载命令。
  81. halt
  82.  
  83. # 为加载RAM BIOS ELF文件,设置256KB的RAM空间并且准备清零
  84. ${TARGET}.cm7_0 configure -work-area-phys 0x20400000 -work-area-size $_WORKAREASIZE -work-area-backup 0	
  85. # 这里是加载我特意准备为实现烧写功能得RAM ELF文件。该RAM ELF是通过调试串口UART实现FLASH文件烧写。
  86. # 注意在load_image之前必须得把target halt。
  87. load_image D:/Work_Data/my_projects/S32K344_EVB/xpack-openocd-0.10.0-15-win32-x64/xpack-openocd-0.10.0-15/bin/Dio_example_DS.elf
  88. # 这里我RAM ELF得起始地址是0x20400010，这里指定从0x20400010恢复。resume 是把PC指针指向0x20400010，释放了debug 模式。
  89. resume 0x20400010
  90.  
  91. #下面是Target事件,其实它得实现方式类似于我们在代码里函数钩子。
  92. # 因为每个芯片得Target Events处理是不一样的。这些事件需要做特殊处理
  93.  
  94. # 由于S32K3芯片的特殊性，如果不使能DAP是无法接入Cortex M7 core 0的MEM AP。
  95. # 所以我增加了SDA AP使能在examine-start,确保在target_examine之前物理通路是通的。
  96. ${TARGET}.cm7_0 configure -event examine-start {
  97. 	# Enable Cortex-M7 Core0 debug request
  98. 	s32k3xx.dap  apreg 7 0x80 0x300000f0
  99. }
  100.  
  101. # 为了在Telnel或者gdb调试过程中发起reset init/halt
  102. ${TARGET}.cm7_0 configure -event reset-init {
  103. 	# Keep the old DEMCR value.
  104. 	set old [mrw 0xE000EDFC]
  105.     mww 0xE000ED08 0x20430000
  106. 	# Enable vector catch on reset.
  107. 	mww 0xE000EDFC 0x01000001
  108.  
  109. 	# Issue local reset via AIRCR.
  110. 	mww 0xE000ED0C 0x05FA0001
  111.  
  112. 	# Restore old DEMCR value.
  113. 	mww 0xE000EDFC $old
  114.  
  115. 	cortex_m reset_config sysresetreq
  116. 	cortex_m reset_config vectreset
  117.  
  118. 	mww 0x402DC140 0x00000001 1
  119. 	mww 0x402DC144 0x00000001 1
  120. 	
  121. 	mww 0x402DC134 0x0000F7DF 1
  122. 	mww 0x402DC100 0x00000001 1
  123. 	mww 0x402DC104 0x00000001 1
  124. 	mww 0x402DC000 0x00005AF0 1
  125. 	mww 0x402DC000 0x0000A50F 1
  126. 	
  127. 	mww 0x402DC330 0xB1E0FFF8 1
  128. 	mww 0x402DC334 0x812AA407 1
  129. 	mww 0x402DC338 0xBBF3FE7E 1
  130. 	mww 0x402DC33C 0x00000141 1
  131. 	mww 0x402DC300 0x00000001 1
  132. 	mww 0x402DC304 0x00000001 1
  133. 	mww 0x402DC000 0x00005AF0 1
  134. 	mww 0x402DC000 0x0000A50F 1
  135. 	
  136. 	mww 0x402DC530 0x29FFFFF0 1
  137. 	mww 0x402DC534 0xC48987F9 1
  138. 	mww 0x402DC500 0x00000001 1
  139. 	mww 0x402DC504 0x00000001 1
  140. 	mww 0x402DC000 0x00005AF0 1
  141. 	mww 0x402DC000 0x0000A50F 1
  142. 	
  143. 	# Disable WATCHDOG
  144. 	mwb 0x40280003 0x80 1
  145. 	mww 0x40210020 0x00400000 1
  146. 	mww 0x40210024 0x03030000 1
  147. 	mww 0x40210028 0x00050000 1
  148. 	mww 0x4021002C 0x00000000 1
  149. 	
  150. 	mww 0x40210030 0x20400000 1
  151. 	mww 0x40210034 0x00080008 1
  152. 	mww 0x40210038 0xFFFB0000 1
  153. 	mww 0x4021003C 0x00000001 1
  154. }

在运行OPENOCD之前必须得需要安装SysProgs USB Driver Tool。
处理用于OpenOCD的USB驱动程序可能会很麻烦，尤其是在Windows上。 SysProgs USB驱动程序工具简化了很多操作：
•从 https://visualgdb.com/UsbDriverTool 下载该工具并安装（实际上，它只是将文件解压缩到您选择的文件夹中）
•运行工具

看到USB Serial Converter A/B Vendor ID 0403 Device ID 6010的两个USB设备。

选择USB Serial Converter A，将它的USB驱动安装成WinUSB.

把ftdi_ft2232d.cfg和nxp_s32k3x4.cfg拷贝到你想运行的目录。我这里的目录是D:\cygwin64\home\$user

  1. $ openocd.exe  -f ftdi_ft2232d.cfg -f nxp_s32k3x4.cfg
  2. Open On-Chip Debugger 0.11.0 (2021-03-23-12:47)
  3. Licensed under GNU GPL v2
  4. For bug reports, read
  5.         http://openocd.org/doc/doxygen/bugs.html
  6. Info : FTDI SWD mode enabled
  7. Error: libusb_open() failed with LIBUSB_ERROR_NOT_SUPPORTED  #忽略这两个错误
  8. Error: libusb_open() failed with LIBUSB_ERROR_NOT_SUPPORTED
  9. Info : clock speed 1000 kHz
  10. Info : SWD DPIDR 0x6ba02477
  11. Info : s32k3xx.armv7m.cm7_0: hardware has 8 breakpoints, 4 watchpoints
  12. Info : starting gdb server for s32k3xx.armv7m.cm7_0 on 3333
  13. Info : Listening on port 3333 for gdb connections
  14. Info : Listening on port 6666 for tcl connections
  15. Info : Listening on port 4444 for telnet connections

OPENOCD默认调试信息等级是2，如果你想看到更多的调试信息命令如下：

  1. $ openocd.exe  -f ftdi_ft2232d.cfg -f nxp_s32k3x4.cfg -d3
  2. Open On-Chip Debugger 0.11.0 (2021-03-23-12:47)
  3. Licensed under GNU GPL v2
  4. For bug reports, read
  5.         http://openocd.org/doc/doxygen/bugs.html
  6. User : 13 3 options.c:63 configuration_output_handler(): debug_level: 3
  7. User : 14 5 options.c:63 configuration_output_handler():
  8. Debug: 15 7 options.c:244 add_default_dirs(): bindir=/usr/local/bin
  9. Debug: 16 8 options.c:245 add_default_dirs(): pkgdatadir=/usr/local/share/openocd
  10. Debug: 17 10 options.c:246 add_default_dirs(): exepath=/usr/local/bin
  11. Debug: 18 12 options.c:247 add_default_dirs(): bin2data=../share/openocd
  12. Debug: 19 14 configuration.c:42 add_script_search_dir(): adding C:/Users/wezhu/AppData/Roaming/OpenOCD
  13. Debug: 20 16 configuration.c:42 add_script_search_dir(): adding /home/WeZhu/.config/openocd
  14. Debug: 21 18 configuration.c:42 add_script_search_dir(): adding /home/WeZhu/.openocd
  15. Debug: 22 20 configuration.c:42 add_script_search_dir(): adding /usr/local/bin/../share/openocd/site
  16. Debug: 23 23 configuration.c:42 add_script_search_dir(): adding /usr/local/bin/../share/openocd/scripts
  17. Debug: 24 25 configuration.c:97 find_file(): found ftdi_ft2232d.cfg
  18. Debug: 25 26 command.c:146 script_debug(): command - adapter driver ftdi
  19. Debug: 27 28 command.c:146 script_debug(): command - transport select swd
  20. Info : 28 30 ftdi.c:1035 ftdi_swd_init(): FTDI SWD mode enabled
  21. Debug: 29 31 command.c:146 script_debug(): command - ftdi_vid_pid 0x0403 0x6010
  22. Debug: 31 33 command.c:146 script_debug(): command - adapter speed 1000
  23. Debug: 33 35 core.c:1822 jtag_config_khz(): handle jtag khz
  24. Debug: 34 37 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
  25. Debug: 35 39 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
  26. Debug: 36 41 command.c:146 script_debug(): command - ftdi_layout_init 0x0018 0x05fb
  27. Debug: 38 42 command.c:146 script_debug(): command - ftdi_layout_signal SWD_EN -data 0
  28. Debug: 40 44 command.c:146 script_debug(): command - ftdi_layout_signal nSRST -data 0x0010
  29. ……
  30. ……
  31. Debug: 206 1311 ftdi.c:648 ftdi_initialize(): ftdi interface using shortest path jtag state transitions
  32. Debug: 207 1363 mpsse.c:422 mpsse_purge(): -
  33. Debug: 208 1366 mpsse.c:703 mpsse_loopback_config(): off
  34. Debug: 209 1369 mpsse.c:748 mpsse_set_frequency(): target 1000000 Hz
  35. Debug: 210 1372 mpsse.c:740 mpsse_rtck_config(): off
  36. Debug: 211 1376 mpsse.c:729 mpsse_divide_by_5_config(): off
  37. Debug: 212 1379 mpsse.c:709 mpsse_set_divisor(): 29
  38. Debug: 213 1388 mpsse.c:772 mpsse_set_frequency(): actually 1000000 Hz
  39. Debug: 214 1395 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
  40. Debug: 215 1399 core.c:1789 adapter_khz_to_speed(): have interface set up
  41. Debug: 216 1406 mpsse.c:748 mpsse_set_frequency(): target 1000000 Hz
  42. Debug: 217 1410 mpsse.c:740 mpsse_rtck_config(): off
  43. Debug: 218 1418 mpsse.c:729 mpsse_divide_by_5_config(): off
  44. Debug: 219 1430 mpsse.c:709 mpsse_set_divisor(): 29
  45. Debug: 220 1432 mpsse.c:772 mpsse_set_frequency(): actually 1000000 Hz
  46. Debug: 221 1441 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
  47. Debug: 222 1446 core.c:1789 adapter_khz_to_speed(): have interface set up
  48. Info : 223 1452 core.c:1565 adapter_init(): clock speed 1000 kHz
  49. Debug: 224 1462 openocd.c:157 handle_init_command(): Debug Adapter init complete
  50. Debug: 225 1466 command.c:146 script_debug(): command - transport init
  51. Debug: 227 1475 transport.c:239 handle_transport_init(): handle_transport_init
  52. Debug: 228 1480 command.c:146 script_debug(): command - dap init
  53. Debug: 230 1486 arm_dap.c:106 dap_init_all(): Initializing all DAPs ...
  54. Debug: 231 1497 ftdi.c:1209 ftdi_swd_switch_seq(): JTAG-to-SWD
  55. Info : 233 1500 adi_v5_swd.c:136 swd_connect(): SWD DPIDR 0x6ba02477
  56. Debug: 234 1510 arm_adi_v5.c:653 dap_dp_init(): s32k3xx.dap
  57. Debug: 235 1514 arm_adi_v5.c:698 dap_dp_init(): DAP: wait CDBGPWRUPACK
  58. Debug: 236 1521 arm_adi_v5.h:506 dap_dp_poll_register(): DAP: poll 4, mask 0x20000000, value 0x20000000
  59. Debug: 237 1532 arm_adi_v5.c:706 dap_dp_init(): DAP: wait CSYSPWRUPACK
  60. Debug: 238 1538 arm_adi_v5.h:506 dap_dp_poll_register(): DAP: poll 4, mask 0x80000000, value 0x80000000
  61. Debug: 239 1552 openocd.c:174 handle_init_command(): Examining targets...
  62. Debug: 240 1563 target.c:1644 target_call_event_callbacks(): target event 19 (examine-start) for core s32k3xx.armv7m.cm7_0
  63. Debug: 241 1569 arm_adi_v5.c:776 mem_ap_init(): MEM_AP Packed Transfers: enabled
  64. Debug: 242 1576 arm_adi_v5.c:787 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0
  65. Debug: 243 1584 target.c:2406 target_read_u32(): address: 0xe000ed00, value: 0x411fc272
  66. Debug: 244 1587 cortex_m.c:2194 cortex_m_examine(): Cortex-M7 r1p2 processor detected
  67. Debug: 245 1596 cortex_m.c:2206 cortex_m_examine(): cpuid: 0x411fc272
  68. Debug: 246 1600 target.c:2406 target_read_u32(): address: 0xe000ef40, value: 0x10110021
  69. Debug: 247 1611 target.c:2406 target_read_u32(): address: 0xe000ef44, value: 0x11000011
  70. Debug: 248 1619 cortex_m.c:2226 cortex_m_examine(): Cortex-M7 floating point feature FPv5_SP found
  71. Debug: 249 1629 target.c:2406 target_read_u32(): address: 0xe000edf0, value: 0x01010001
  72. Debug: 250 1633 target.c:2494 target_write_u32(): address: 0xe000edfc, value: 0x01000000
  73. Debug: 251 1643 target.c:2406 target_read_u32(): address: 0xe0002000, value: 0x10000081
  74. Debug: 252 1646 target.c:2494 target_write_u32(): address: 0xe0002008, value: 0x00000000
  75. Debug: 253 1654 target.c:2494 target_write_u32(): address: 0xe000200c, value: 0x00000000
  76. Debug: 254 1664 target.c:2494 target_write_u32(): address: 0xe0002010, value: 0x00000000
  77. Debug: 255 1669 target.c:2494 target_write_u32(): address: 0xe0002014, value: 0x00000000
  78. Debug: 256 1678 target.c:2494 target_write_u32(): address: 0xe0002018, value: 0x00000000
  79. Debug: 257 1683 target.c:2494 target_write_u32(): address: 0xe000201c, value: 0x00000000
  80. Debug: 258 1690 target.c:2494 target_write_u32(): address: 0xe0002020, value: 0x00000000
  81. Debug: 259 1694 target.c:2494 target_write_u32(): address: 0xe0002024, value: 0x00000000
  82. Debug: 260 1700 cortex_m.c:2308 cortex_m_examine(): FPB fpcr 0x10000081, numcode 8, numlit 0
  83. Debug: 261 1708 target.c:2406 target_read_u32(): address: 0xe0001000, value: 0x40000000
  84. Debug: 262 1712 cortex_m.c:2024 cortex_m_dwt_setup(): DWT_CTRL: 0x40000000
  85. Debug: 263 1719 target.c:2406 target_read_u32(): address: 0xe0001fbc, value: 0x00000000
  86. Debug: 264 1730 cortex_m.c:2031 cortex_m_dwt_setup(): DWT_DEVARCH: 0x0
  87. Debug: 265 1733 target.c:2494 target_write_u32(): address: 0xe0001028, value: 0x00000000
  88. Debug: 266 1743 target.c:2494 target_write_u32(): address: 0xe0001038, value: 0x00000000
  89. Debug: 267 1751 target.c:2494 target_write_u32(): address: 0xe0001048, value: 0x00000000
  90. Debug: 268 1763 target.c:2494 target_write_u32(): address: 0xe0001058, value: 0x00000000
  91. Debug: 269 1767 cortex_m.c:2078 cortex_m_dwt_setup(): DWT dwtcr 0x40000000, comp 4, watch/trigger
  92. Info : 270 1776 cortex_m.c:2318 cortex_m_examine(): s32k3xx.armv7m.cm7_0: hardware has 8 breakpoints, 4 watchpoints
  93. Debug: 271 1784 target.c:1644 target_call_event_callbacks(): target event 21 (examine-end) for core s32k3xx.armv7m.cm7_0
  94. Debug: 272 1799 command.c:146 script_debug(): command - flash init
  95. Debug: 274 1806 tcl.c:1324 handle_flash_init_command(): Initializing flash devices...
  96. Debug: 275 1818 command.c:146 script_debug(): command - nand init
  97. Debug: 277 1822 tcl.c:498 handle_nand_init_command(): Initializing NAND devices...
  98. Debug: 278 1827 command.c:146 script_debug(): command - pld init
  99. Debug: 280 1832 pld.c:206 handle_pld_init_command(): Initializing PLDs...
  100. Info : 281 1841 gdb_server.c:3503 gdb_target_start(): starting gdb server for s32k3xx.armv7m.cm7_0 on 3333
  101. Info : 282 1850 server.c:310 add_service(): Listening on port 3333 for gdb connections
  102. Debug: 283 1858 command.c:146 script_debug(): command - s32k3xx.dap apreg 7 0x80 0x300000f0
  103. Info : 285 1864 server.c:310 add_service(): Listening on port 6666 for tcl connections
  104. Info : 286 1870 server.c:310 add_service(): Listening on port 4444 for telnet connections
  105. Debug: 287 1879 command.c:146 script_debug(): command - init

你几乎可以看到每条配置文件中每条命令的响应，可以帮助你理解整个接入流程。

下面我可以通过Telent 端口4444登录到目标板内核Cortex-M7内部查看响应DAP的信息。
Windows10系统自带Telnet客户端安装。由于我的系统是英文版的，所以步骤我这里就直接用英文了：

  1. 1. Click Start.
  2. 2. Select Control Panel.
  3. 3. Choose Programs and Features.
  4. 4. Click Turn Windows features on or off.
  5. 5. Select the Telnet Client option.
  6. Click OK. A dialog box appears to confirm installation. The telnet command should now be available.

安装完Telnet客户端后，我们直接在运行里敲cmd进入windows 命令行. 进入到命令行后执行telnet localhost 4444

  1. Open On-Chip Debugger
  2. > dap
  3. adapter
  4.   adapter assert |deassert [srst|trst [assert|deassert srst|trst]]
  5.   adapter deassert |assert [srst|trst [deassert|assert srst|trst]]
  6.   adapter driver driver_name
  7.   adapter list
  8.   adapter name
  9.   adapter speed [khz]
  10.   adapter srst
  11.     adapter srst delay [milliseconds]
  12.     adapter srst pulse_width [milliseconds]
  13.   adapter transports transport ...
  14.   adapter usb
  15.     adapter usb location [<bus>-port[.port]...]
  16. dap
  17.   dap create name '-chain-position' name
  18.   dap info [ap_num]
  19.   dap init
  20.   dap names
  21. reset_config [none|trst_only|srst_only|trst_and_srst]
  22.           [srst_pulls_trst|trst_pulls_srst|combined|separate]
  23.           [srst_gates_jtag|srst_nogate] [trst_push_pull|trst_open_drain]
  24.           [srst_push_pull|srst_open_drain]
  25.           [connect_deassert_srst|connect_assert_srst]
  26. s32k3xx.dap
  27.   s32k3xx.dap apcsw [value [mask]]
  28.   s32k3xx.dap apid [ap_num]
  29.   s32k3xx.dap apreg ap_num reg [value]
  30.   s32k3xx.dap apsel [ap_num]
  31.   s32k3xx.dap baseaddr [ap_num]
  32.   s32k3xx.dap dpreg reg [value]
  33.   s32k3xx.dap info [ap_num]
  34.   s32k3xx.dap memaccess [cycles]
  35.   s32k3xx.dap ti_be_32_quirks [enable]
  36.   swd newdap
  37. dap: command requires more arguments

通过dap info [ap_num]可以查看到到底有多少个AP连接到SWD上

  1. > dap info 1
  2. SWD DPIDR 0x6ba02477
  3. AP ID register 0x54770002
  4.         Type is MEM-AP APB
  5. MEM-AP BASE 0x80000003
  6.         Valid ROM table present
  7.                 Component base address 0x80000000
  8.                 Peripheral ID 0x000008e995
  9.                 Designer is 0x08e, Freescale (Motorola)
  10.                 Part is 0x995, Unrecognized
  11.                 Component class is 0x1, ROM table
  12.                 MEMTYPE system memory not present: dedicated debug bus
  13.         ROMTABLE[0x0] = 0x1003
  14.                 Component base address 0x80001000
  15.                 Peripheral ID 0x04003bb908
  16.                 Designer is 0x4bb, ARM Ltd
  17.                 Part is 0x908, CoreSight CSTF (Trace Funnel)
  18.                 Component class is 0x9, CoreSight component
  19.                 Type is 0x12, Trace Link, Funnel, router
  20.         ROMTABLE[0x4] = 0x2003
  21.                 Component base address 0x80002000
  22.                 Peripheral ID 0x04003bb908
  23.                 Designer is 0x4bb, ARM Ltd
  24.                 Part is 0x908, CoreSight CSTF (Trace Funnel)
  25.                 Component class is 0x9, CoreSight component
  26.                 Type is 0x12, Trace Link, Funnel, router
  27.         ROMTABLE[0x8] = 0x3003
  28.                 Component base address 0x80003000
  29.                 Peripheral ID 0x04003bb908
  30.                 Designer is 0x4bb, ARM Ltd
  31.                 Part is 0x908, CoreSight CSTF (Trace Funnel)
  32.                 Component class is 0x9, CoreSight component
  33.                 Type is 0x12, Trace Link, Funnel, router
  34.         ROMTABLE[0xc] = 0x4003
  35.                 Component base address 0x80004000
  36.                 Peripheral ID 0x04001bb961
  37.                 Designer is 0x4bb, ARM Ltd
  38.                 Part is 0x961, CoreSight TMC (Trace Memory Controller)
  39.                 Component class is 0x9, CoreSight component
  40.                 Type is 0x32, Trace Link, FIFO, buffer
  41.         ROMTABLE[0x10] = 0x5003
  42.                 Component base address 0x80005000
  43.                 Peripheral ID 0x04001bb961
  44.                 Designer is 0x4bb, ARM Ltd
  45.                 Part is 0x961, CoreSight TMC (Trace Memory Controller)
  46.                 Component class is 0x9, CoreSight component
  47.                 Type is 0x32, Trace Link, FIFO, buffer
  48.         ROMTABLE[0x14] = 0x6003
  49.                 Component base address 0x80006000
  50.                 Peripheral ID 0x04001bb961
  51.                 Designer is 0x4bb, ARM Ltd
  52.                 Part is 0x961, CoreSight TMC (Trace Memory Controller)
  53.                 Component class is 0x9, CoreSight component
  54.                 Type is 0x32, Trace Link, FIFO, buffer
  55.         ROMTABLE[0x18] = 0x7003
  56.                 Component base address 0x80007000
  57.                 Peripheral ID 0x04001bb961
  58.                 Designer is 0x4bb, ARM Ltd
  59.                 Part is 0x961, CoreSight TMC (Trace Memory Controller)
  60.                 Component class is 0x9, CoreSight component
  61.                 Type is 0x32, Trace Link, FIFO, buffer
  62.         ROMTABLE[0x1c] = 0x8003
  63.                 Component base address 0x80008000
  64.                 Peripheral ID 0x04004bb917
  65.                 Designer is 0x4bb, ARM Ltd
  66.                 Part is 0x917, CoreSight HTM (AHB Trace Macrocell)
  67.                 Component class is 0x9, CoreSight component
  68.                 Type is 0x43, Trace Source, Bus
  69.         ROMTABLE[0x20] = 0x9003
  70.                 Component base address 0x80009000
  71.                 Peripheral ID 0x04005bb906
  72.                 Designer is 0x4bb, ARM Ltd
  73.                 Part is 0x906, CoreSight CTI (Cross Trigger)
  74.                 Component class is 0x9, CoreSight component
  75.                 Type is 0x14, Debug Control, Trigger Matrix
  76.         ROMTABLE[0x24] = 0xa003
  77.                 Component base address 0x8000a000
  78.                 Can't read component, the corresponding core might be turned off
  79. > dap info 2
  80. AP ID register 0x84770001
  81.         Type is MEM-AP AHB3
  82. MEM-AP BASE 0xf0000003
  83.         Valid ROM table present
  84.                 Component base address 0xf0000000
  85.                 Can't read component, the corresponding core might be turned off
  86.  
  87. > dap info 4
  88. AP ID register 0x84770001
  89.         Type is MEM-AP AHB3
  90. MEM-AP BASE 0xe00fe003
  91.         Valid ROM table present
  92.                 Component base address 0xe00fe000
  93.                 Peripheral ID 0x04000bb4c8
  94.                 Designer is 0x4bb, ARM Ltd
  95.                 Part is 0x4c8, Cortex-M7 ROM (ROM Table)
  96.                 Component class is 0x1, ROM table
  97.                 MEMTYPE system memory present on bus
  98.         ROMTABLE[0x0] = 0x1003
  99.                 Component base address 0xe00ff000
  100.                 Peripheral ID 0x04000bb4c7
  101.                 Designer is 0x4bb, ARM Ltd
  102.                 Part is 0x4c7, Cortex-M7 PPB ROM (Private Peripheral Bus ROM Table)
  103.                 Component class is 0x1, ROM table
  104.                 MEMTYPE system memory present on bus
  105.         [L01] ROMTABLE[0x0] = 0xfff0f003
  106.                 Component base address 0xe000e000
  107.                 Peripheral ID 0x04000bb00c
  108.                 Designer is 0x4bb, ARM Ltd
  109.                 Part is 0xc, Cortex-M4 SCS (System Control Space)
  110.                 Component class is 0xe, Generic IP component
  111.         [L01] ROMTABLE[0x4] = 0xfff02003
  112.                 Component base address 0xe0001000
  113.                 Peripheral ID 0x04000bb002
  114.                 Designer is 0x4bb, ARM Ltd
  115.                 Part is 0x2, Cortex-M3 DWT (Data Watchpoint and Trace)
  116.                 Component class is 0xe, Generic IP component
  117.         [L01] ROMTABLE[0x8] = 0xfff03003
  118.                 Component base address 0xe0002000
  119.                 Peripheral ID 0x04000bb00e
  120.                 Designer is 0x4bb, ARM Ltd
  121.                 Part is 0xe, Cortex-M7 FPB (Flash Patch and Breakpoint)
  122.                 Component class is 0xe, Generic IP component
  123.         [L01] ROMTABLE[0xc] = 0xfff01003
  124.                 Component base address 0xe0000000
  125.                 Peripheral ID 0x04000bb001
  126.                 Designer is 0x4bb, ARM Ltd
  127.                 Part is 0x1, Cortex-M3 ITM (Instrumentation Trace Module)
  128.                 Component class is 0xe, Generic IP component
  129.         [L01] ROMTABLE[0x10] = 0xfff41002
  130.                 Component not present
  131.         [L01] ROMTABLE[0x14] = 0xfff42002
  132.                 Component not present
  133.         [L01] ROMTABLE[0x18] = 0x0
  134.         [L01]   End of ROM table
  135.         ROMTABLE[0x4] = 0xfff43003
  136.                 Component base address 0xe0041000
  137.                 Peripheral ID 0x04001bb975
  138.                 Designer is 0x4bb, ARM Ltd
  139.                 Part is 0x975, Cortex-M7 ETM (Embedded Trace)
  140.                 Component class is 0x9, CoreSight component
  141.                 Type is 0x13, Trace Source, Processor
  142.         ROMTABLE[0x8] = 0xfff44003
  143.                 Component base address 0xe0042000
  144.                 Peripheral ID 0x04004bb906
  145.                 Designer is 0x4bb, ARM Ltd
  146.                 Part is 0x906, CoreSight CTI (Cross Trigger)
  147.                 Component class is 0x9, CoreSight component
  148.                 Type is 0x14, Debug Control, Trigger Matrix
  149.         ROMTABLE[0xc] = 0x1ff02002
  150.                 Component not present
  151.         ROMTABLE[0x10] = 0x0
  152.                 End of ROM table
  153.  
  154. > dap info 6
  155. AP ID register 0x001c0030
  156.         Unknown AP type
  157.  
  158. > dap info 7
  159. AP ID register 0x001c0040
  160.         Unknown AP type

基本看到对应关系如下：

dap info 显示的内容我就不再展开了，里面的对应内容大家可以在Arm CoreSight SoC-400 Technical Reference Manual , CoreSight Components Technical Reference Manual ，ARM® Debug Interface Architecture Specification ADIv5.0 to ADIv5.2 和 Arm Cortex-M7 Processor Technical Reference Manual 找到对应关系和解释。

大家还可以通过 s32k3xx.dap apreg ap_num reg [value] 访问所有可以见到的AP的寄存器内容。

我们选择AP4 MEM-AP AHB AP 参考文档ARM® Debug Interface Architecture Specification ADIv5.0 to ADIv5.2 章节 7.The Memory Access Port (MEM-AP)  Table 7-6 Summary of Memory Access Port (MEM-AP) registers

读取0xFC IDR, Identification Register

  1. > s32k3xx.dap apreg 4 0xFC
  2. 0x84770001

读取0xF8 BASE, Debug Base Address register

  1. > s32k3xx.dap apreg 4 0xF8
  2. 0xe00fe003

如果你想获取Cortex M7内部寄存器的访问，

  1. > s32k3xx.armv7m.cm7_0    #这个是我们在目标板配置文件中给Target的命名
  2. s32k3xx.armv7m.cm7_0
  3.   s32k3xx.armv7m.cm7_0 arm
  4.     s32k3xx.armv7m.cm7_0 arm core_state ['arm'|'thumb']
  5.     s32k3xx.armv7m.cm7_0 arm disassemble address [count ['thumb']]
  6.     s32k3xx.armv7m.cm7_0 arm mcr cpnum op1 CRn CRm op2 value
  7.     s32k3xx.armv7m.cm7_0 arm mrc cpnum op1 CRn CRm op2
  8.     s32k3xx.armv7m.cm7_0 arm reg
  9.     s32k3xx.armv7m.cm7_0 arm semihosting ['enable'|'disable']
  10.     s32k3xx.armv7m.cm7_0 arm semihosting_cmdline arguments
  11.     s32k3xx.armv7m.cm7_0 arm semihosting_fileio ['enable'|'disable']
  12.     s32k3xx.armv7m.cm7_0 arm semihosting_resexit ['enable'|'disable']
  13.   s32k3xx.armv7m.cm7_0 arp_examine ['allow-defer']
  14.   s32k3xx.armv7m.cm7_0 arp_halt
  15.   s32k3xx.armv7m.cm7_0 arp_halt_gdb
  16.   s32k3xx.armv7m.cm7_0 arp_poll
  17.   s32k3xx.armv7m.cm7_0 arp_reset
  18.   s32k3xx.armv7m.cm7_0 arp_waitstate
  19.   s32k3xx.armv7m.cm7_0 array2mem arrayname bitwidth address count
  20.   s32k3xx.armv7m.cm7_0 cget target_attribute
  21.   s32k3xx.armv7m.cm7_0 configure [target_attribute ...]
  22.   s32k3xx.armv7m.cm7_0 cortex_m
  23.     s32k3xx.armv7m.cm7_0 cortex_m maskisr ['auto'|'on'|'off'|'steponly']
  24.     s32k3xx.armv7m.cm7_0 cortex_m reset_config ['sysresetreq'|'vectreset']
  25.     s32k3xx.armv7m.cm7_0 cortex_m vector_catch ['all'|'none'|('bus_err'|'chk_err'|...)*]
  26.   s32k3xx.armv7m.cm7_0 curstate
  27.   s32k3xx.armv7m.cm7_0 eventlist
  28.   s32k3xx.armv7m.cm7_0 examine_deferred
  29.   s32k3xx.armv7m.cm7_0 invoke-event event_name
  30.   s32k3xx.armv7m.cm7_0 itm
  31.     s32k3xx.armv7m.cm7_0 itm port <port> (0|1|on|off)
  32.     s32k3xx.armv7m.cm7_0 itm ports (0|1|on|off)
  33.   s32k3xx.armv7m.cm7_0 mdb address [count]
  34.   s32k3xx.armv7m.cm7_0 mdd address [count]
  35.   s32k3xx.armv7m.cm7_0 mdh address [count]
  36.   s32k3xx.armv7m.cm7_0 mdw address [count]            #双字节读取
  37.   s32k3xx.armv7m.cm7_0 mem2array arrayname bitwidth address count
  38.   s32k3xx.armv7m.cm7_0 mwb address data [count]
  39.   s32k3xx.armv7m.cm7_0 mwd address data [count]
  40.   s32k3xx.armv7m.cm7_0 mwh address data [count]
  41.   s32k3xx.armv7m.cm7_0 mww address data [count]        #双字节写入
  42.   s32k3xx.armv7m.cm7_0 rtt
  43.     s32k3xx.armv7m.cm7_0 rtt channellist
  44.     s32k3xx.armv7m.cm7_0 rtt channels
  45.     s32k3xx.armv7m.cm7_0 rtt polling_interval [interval]
  46.     s32k3xx.armv7m.cm7_0 rtt setup <address> <size> <ID>
  47.     s32k3xx.armv7m.cm7_0 rtt start
  48.     s32k3xx.armv7m.cm7_0 rtt stop
  49.   s32k3xx.armv7m.cm7_0 tpiu
  50.     s32k3xx.armv7m.cm7_0 tpiu config (disable | ((external | internal (<filename> | <:port> | -)) (sync <port
  51.               width> | ((manchester | uart) <formatter enable>))
  52.               <TRACECLKIN freq> [<trace freq>]))
  53.   s32k3xx.armv7m.cm7_0 was_examined
  54. s32k3xx.armv7m.cm7_0: command requires more arguments

或者你直接使用mww 和mdw 命令也可以。因为OpenOCD默认使用 s32k3xx.armv7m.cm7_0 mww 和 s32k3xx.armv7m.cm7_0 mdw替换。

举例：向寄存器0x402DC000 ，写入0x0000A50F

> mww 0x402DC000 0x0000A50F 1

读取寄存器0x402DC000

  1. > mdw 0x402DC000 1
  2. 0x402dc000: 00005af0

我们可以使用arm-none-eabi-gdb 工具进行断点调试。GDB登录端口3333

arm-none-eabi-gdb 软件资源很多Windows10的资源如下：

  1. D:\Program Files (x86)\GNU Arm Embedded Toolchain\10 2020-q4-major\bin>arm-none-eabi-gdb.exe D:\Work_Data\my_projects\S32K344_EVB\xpack-openocd-0.10.0-15-win32-x64\xpack-openocd-0.10.0-15\bin\Dio_example_DS.elf
  2. D:\Program Files (x86)\GNU Arm Embedded Toolchain\10 2020-q4-major\bin\arm-none-eabi-gdb.exe: warning: Couldn't determine a path for the index cache directory.
  3. GNU gdb (GNU Arm Embedded Toolchain 10-2020-q4-major) 10.1.90.20201028-git
  4. Copyright (C) 2020 Free Software Foundation, Inc.
  5. License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
  6. This is free software: you are free to change and redistribute it.
  7. There is NO WARRANTY, to the extent permitted by law.
  8. Type "show copying" and "show warranty" for details.
  9. This GDB was configured as "--host=i686-w64-mingw32 --target=arm-none-eabi".
  10. Type "show configuration" for configuration details.
  11. For bug reporting instructions, please see:
  12. <https://www.gnu.org/software/gdb/bugs/>.
  13. Find the GDB manual and other documentation resources online at:
  14.     <http://www.gnu.org/software/gdb/documentation/>.
  15.  
  16. For help, type "help".
  17. Type "apropos word" to search for commands related to "word"...
  18. Reading symbols from D:\Work_Data\my_projects\S32K344_EVB\xpack-openocd-0.10.0-15-win32-x64\xpack-openocd-0.10.0-15\bin\Dio_example_DS.elf...
  19. (gdb) target remote 127.0.0.1:3333
  20. Remote debugging using 127.0.0.1:3333
  21. main () at ../src/main.c:74
  22. 74                      DelayCount++;
  23. (gdb) bt
  24. #0  main () at ../src/main.c:74
  25. (gdb) b main
  26. Breakpoint 1 at 0x204002a0: file ../src/main.c, line 55.
  27. (gdb) c
  28. Continuing.
  29.  
  30. Program received signal SIGINT, Interrupt.
  31. 0x204002d8 in main () at ../src/main.c:74
  32. 74                      DelayCount++;
  33. (gdb) bt
  34. #0  0x204002d8 in main () at ../src/main.c:74
  35. (gdb) list
  36. 69                  /* Dio_WriteChannel(DioConf_DioChannel_Digital_Output_LED_D78, STD_LOW); */
  37. 70                  Siul2_Dio_Ip_WritePin(PTB_L_HALF, LED_PIN_PIN, 0U);
  38. 71                  /*delay*/
  39. 72                  while(DelayCount<10000)
  40. 73                  {
  41. 74                      DelayCount++;
  42. 75                  }
  43. 76                  DelayCount = 0;
  44. 77          }
  45. 78
  46. (gdb) print
  47. The history is empty.
  48. (gdb) print DelayCount
  49. $1 = 0
  50. (gdb) set step-mode
  51. (gdb) si
  52. 72                  while(DelayCount<10000)
  53. (gdb) si
  54. 0x204002ce      72                  while(DelayCount<10000)
  55. (gdb) si
  56. 74                      DelayCount++;
  57. (gdb) c
  58. Continuing.
  59.  
  60. Program received signal SIGINT, Interrupt.
  61. main () at ../src/main.c:74
  62. 74                      DelayCount++;
  63. (gdb) list
  64. 69                  /* Dio_WriteChannel(DioConf_DioChannel_Digital_Output_LED_D78, STD_LOW); */
  65. 70                  Siul2_Dio_Ip_WritePin(PTB_L_HALF, LED_PIN_PIN, 0U);
  66. 71                  /*delay*/
  67. 72                  while(DelayCount<10000)
  68. 73                  {
  69. 74                      DelayCount++;
  70. 75                  }
  71. 76                  DelayCount = 0;
  72. 77          }
  73. 78
  74. (gdb)

GDB的命令大家可以看宋宝华的Linux gdb调试器用法全面解析和GDB GUI 工具Eclipse使用方法在如何结合Eclipse+OpenOCD+arm-none-eabi-gdb实现可视化在线调试ARM Cortex M7内核？文章中介绍。

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