HDLbits答案_程序改错: moduleexab(a,b,cde) input ab,c outputd,e; na

目录

• 1 Getting Started

•  1.1 Getting Started

module top_module( output one );

// Insert your code here
    assign one = 1'b1;

endmodule

  1.2 Output Zero

module top_module(
    output zero=0
);// Module body starts after semicolon

endmodule

• 2 Verilog Language

  • 2.1 Basics

2.1.1  Simple Wires

module top_module( input in, output out );
assign out=in;
endmodule

2.1.2  Four wires

module top_module( 
    input a,b,c,
    output w,x,y,z );
assign w=a,x=b,y=b,z=c;
endmodule

2.1.3 Inverter

module top_module( input in, output out );
assign out=!in;
endmodule
 

2.1.4 AND Gate

module top_module( 
    input a, 
    input b, 
    output out );
assign out=a&b;
endmodule

2.1.5 NOR Gate

module top_module( 
    input a, 
    input b, 
    output out );
    assign out=!(a|b);
endmodule

2.1.6 XNOR Gate

module top_module( 
    input a, 
    input b, 
    output out );
assign out=a^~b;
endmodule

2.1.7 Declearing Chips

`default_nettype none
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
wire e,f;
    assign e=a&b,f=c&d;
    assign out=e|f,out_n=!(e|f);
endmodule

2.1.8 7458 Chips

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
wire a,b,c,d;
    assign a=p2a&p2b,b=p2c&p2d,c=p1a&p1b&p1c,d=p1d&p1e&p1f;
    assign p1y=c|d,p2y=a|b;

endmodule

• • 2.2 Vectors

2.2.1 Vectors

module top_module ( 
    input wire [2:0] vec,
    output wire [2:0] outv,
    output wire o2,
    output wire o1,
    output wire o0  ); // Module body starts after module declaration
    assign outv[2:0]=vec[2:0],o2=vec[2],o1=vec[1],o0=vec[0];
endmodule

2.2.2 Vectors in more datail

`default_nettype none     // Disable implicit nets. Reduces some types of bugs.
module top_module( 
    input wire [15:0] in,
    output wire [7:0] out_hi,
    output wire [7:0] out_lo );
    assign out_hi=in[15:8],out_lo=in[7:0];
endmodule

2.2.3 Vector part select

module top_module( 
    input [31:0] in,
    output [31:0] out );//

    // assign out[31:24] = ...;
    assign out[31:0]={in[7:0],in[15:8],in[23:16],in[31:24]};
endmodule
 

2.2.4 Bitwise operators

module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);
    assign out_or_bitwise[2:0]=a[2:0]|b[2:0],
           out_or_logical=a||b,
        out_not[5:0]={~b[2:0],~a[2:0]};
endmodule

2.2.5 Four-input gates

module top_module( 
    input [3:0] in,
    output out_and,
    output out_or,
    output out_xor
);
    assign out_and=in[3]&in[2]&in[1]&in[0],
        out_or=in[3]|in[2]|in[1]|in[0],
        out_xor&