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FPGA——spi代码篇_spi指令

作者：喵喵爱编程 | 2024-07-15 13:03:23

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spi指令

一、FPGA 开发SPI基础

        为了避免每次SPI驱动重写，直接参数化，尽量一劳永逸。SPI master有啥用呢，你发现各种外围芯片的配置一般都是通过SPI配置的，只不过有三线和四线。SPI slave有什么用呢，当外部主机（cpu）要读取FPGA内部寄存器值，那就很有用了，FPGA寄存器就相当于RAM，cpu通过SPI寻址读写数据。代码仅供参考，勿做商业用途。

二、SPI三线，四线区别

        三线制指的是CS，CLK，MOMI，是半双工方式；四线制指的是 CS，CLK，MOSI和MISO，是全双工方式。

三、SPI代码构思      

      1. SPI salve

                1.支持三线SPI或者四线SPI。通过define切换。                                 

                2.支持指令长度、帧长自定义。                               

                3.工作时钟可自定义，大于SPI clk的2倍。

        用户只需修改：（1）几线SPI。（2）单帧长度。（3）指令长度。（4）寄存器开辟。

        注意：指令最高bit表示读写，低写高读，其余bit表示地址。指令接着为数据端，两者位宽之和即为SPI单帧长。

  1. //`define SPI_LINE  //是否是三线SPI
  2. `define SPI_FRAME_WIDTH 16 //SPI一帧长度为16
  3. `define SPI_INS_WIDTH 8    //SPI指令长
  4. `timescale 1ns/1ps
  5.  
  6. module spi_slave 
  7. (
  8.     input     i_clk               , //work clk
  9.     input     i_rst_n             ,  
  10.   
  11.     input     i_spi_clk           , //SPI clk
  12.     input     i_spi_cs            , //SPI cs
  13.  
  14.     `ifdef SPI_LINE                 //条件编译
  15.     inout     io_spi_sdio          
  16.     `else
  17.     input     i_spi_mosi          , //SPI mosi
  18.     output    o_spi_miso            //SPI miso
  19.     `endif          
  20. );
  21. //位宽计算函数
  22. function integer clogb2 (input integer depth);
  23. begin
  24.     for (clogb2=0; depth>0; clogb2=clogb2+1) 
  25.         depth = depth >>1;                          
  26. end
  27. endfunction
  28. reg r_cs = 1'b1; //打一拍
  29. always @(posedge i_clk)
  30. begin
  31.     r_cs <= i_spi_cs;
  32. end
  33. reg [1:0] r_spi_clk_edge = 2'b00; //SPI clk边沿检测
  34. always @(posedge i_clk)
  35. begin
  36.     r_spi_clk_edge <= {r_spi_clk_edge[0],i_spi_clk};
  37. end //always
  38. reg [clogb2(`SPI_FRAME_WIDTH-1)-1:0] r_spi_cnt = 'd0;
  39. always @(posedge i_clk)
  40. begin
  41.     if (r_cs) //cs为高则归零
  42.         r_spi_cnt <= 'd0;
  43.     else if (r_spi_clk_edge == 2'b10) //下降沿才计数
  44.         r_spi_cnt <= r_spi_cnt + 'd1;
  45. end
  46. 指令锁存
  47. reg [`SPI_INS_WIDTH-1:0] r_ins = 'd0;
  48. always @(posedge i_clk)
  49. begin
  50.     if ((~r_cs) && (r_spi_clk_edge == 2'b01)) //上升沿锁存数据
  51.     begin
  52.         if ((r_spi_cnt >= 0) && (r_spi_cnt <= `SPI_INS_WIDTH-1))
  53.         `ifdef SPI_LINE                 //条件编译
  54.             r_ins <= {r_ins[`SPI_INS_WIDTH-2:0],io_spi_sdio};  
  55.         `else
  56.             r_ins <= {r_ins[`SPI_INS_WIDTH-2:0],i_spi_mosi};  
  57.         `endif 
  58.     end 
  59. end
  60. 数值写入
  61. reg [`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-1:0] r_data_rx = 'd0;
  62. always @(posedge i_clk)
  63. begin
  64.     if ((~r_cs) && (r_spi_clk_edge == 2'b01)) //上升沿锁存数据
  65.     begin
  66.         if (r_spi_cnt >= `SPI_INS_WIDTH)
  67.         `ifdef SPI_LINE
  68.             r_data_rx <= {r_data_rx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],io_spi_sdio};
  69.         `else
  70.             r_data_rx <= {r_data_rx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],i_spi_mosi};   
  71.         `endif
  72.     end
  73. end
  74. 用户寄存器定义
  75. reg [`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-1:0] r_reg0 = 'd0;
  76. reg [`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-1:0] r_reg1 = 'd0;
  77. reg [`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-1:0] r_reg2 = 'd0;
  78. reg [`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-1:0] r_reg3 = 'd0;
  79.  
  80. always @(posedge i_clk,negedge i_rst_n)
  81. begin
  82.     if (~i_rst_n)
  83.     begin
  84.         r_reg0 <= 'd0;
  85.         r_reg1 <= 'd0;
  86.         r_reg2 <= 'd0;
  87.         r_reg3 <= 'd0;
  88.  
  89.  
  90.  
  91.     end
  92.     else if ((~r_ins[`SPI_INS_WIDTH-1]) && (r_spi_cnt == (`SPI_FRAME_WIDTH-1)) && (~r_cs) && (r_spi_clk_edge == 2'b01))
  93.     begin
  94.     `ifdef SPI_LINE
  95.         case (r_ins[`SPI_INS_WIDTH-2:0])
  96.             'd0:begin r_reg0 <= {r_data_rx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],io_spi_sdio}; end
  97.             'd1:begin r_reg1 <= {r_data_rx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],io_spi_sdio}; end
  98.             'd2:begin r_reg2 <= {r_data_rx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],io_spi_sdio}; end
  99.             'd3:begin r_reg3 <= {r_data_rx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],io_spi_sdio}; end
  104.         endcase 
  105.     `else
  106.         case (r_ins[`SPI_INS_WIDTH-2:0])
  107.             'd0:begin r_reg0 <= {r_data_rx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],i_spi_mosi}; end
  108.             'd1:begin r_reg1 <= {r_data_rx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],i_spi_mosi}; end
  109.             'd2:begin r_reg2 <= {r_data_rx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],i_spi_mosi}; end
  110.             'd3:begin r_reg3 <= {r_data_rx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],i_spi_mosi}; end
  115.         endcase 
  116.     `endif 
  117.     end
  119. end
  120. 寄存器值读出
  121. reg [`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-1:0] r_data_tx = 'd0;
  122. always @(posedge i_clk)
  123. begin
  124.     if (r_ins[`SPI_INS_WIDTH-1] && (~r_cs) && (r_spi_clk_edge == 2'b10))
  125.     begin 
  126.         if (r_spi_cnt == (`SPI_INS_WIDTH-1))
  127.         begin
  128.             case (r_ins[`SPI_INS_WIDTH-2:0])
  129.                 'd0:begin r_data_tx <= r_reg0; end 
  130.                 'd1:begin r_data_tx <= r_reg1; end 
  131.                 'd2:begin r_data_tx <= r_reg2; end 
  132.                 'd3:begin r_data_tx <= r_reg3; end 
  133.     
  134.             endcase 
  135.         end
  136.         else 
  137.             r_data_tx <= {r_data_tx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],1'b0};
  138.     end 
  139. end
  140.  
  141. 读取输出
  142. `ifdef SPI_LINE
  143. assign io_spi_sdio = (r_ins[`SPI_INS_WIDTH-1]) ? (((r_spi_cnt>=`SPI_INS_WIDTH) && (r_spi_cnt<`SPI_FRAME_WIDTH)) ? r_data_tx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-1] : 1'bz) : 1'bz;
  144. `else 
  145. assign o_spi_miso = ((r_spi_cnt>=`SPI_INS_WIDTH) && (r_spi_cnt<`SPI_FRAME_WIDTH)) ? r_data_tx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-1] : 1'b0;
  146. `endif
  148. endmodule // end the spi_slave model

     2.SPI master

        spi master内部仅仅封装SPI驱动，写入值读出控制由上层控制，这部分逻辑很simple，不赘述。用户只需给入SPI帧及控制使能即可。

        用户只需修改parameter参数：（1）单帧长；（2）指令长；（3）数据长；（4）工作时钟；（5）SPI clk。

        实现不使用状态机，采用线性序列计数法。

  1. //`define SPI_LINE  //是否是三线SPI
  2. `timescale 1ns/1ps
  3. module spi_master 
  4. #(parameter p_spi_frame_width = 16, //SPI单帧长度
  5.   parameter p_spi_ins_width = 8   , //指令长度
  6.   parameter p_spi_data_width = 8    //读出数据长度
  7.  )
  8. (
  9.     input                                i_clk             , //系统时钟
  10.     input                                i_rst_n           ,
  11.     input                                i_flag            , //检测到flag的上升沿则启动一次传输,一个时钟周期即可
  12.    
  13.     input     [p_spi_frame_width-1:0]    i_spi_data        ,
  14.     output                               o_spi_cs          ,
  15.     output                               o_spi_clk         ,
  16.  
  17.     `ifdef SPI_LINE                 //条件编译
  18.     inout                                io_spi_sdio       ,          
  19.     `else
  20.     input                                i_spi_miso        , //SPI miso
  21.     output                               o_spi_mosi        , //SPI mosi
  22.     `endif 
  23.     
  24.     output                               o_transfer_done   , //单次传输完成
  25.     output    [p_spi_data_width-1:0]     o_spi_data          //读取数据           
  26. );
  27. parameter p_clk_fre = 200; //XXM时钟频率
  28. parameter p_spi_clk_fre = 0.5*1000; //SPI 时钟速率,表示1M
  29. parameter p_clk_div = p_clk_fre * 1000/p_spi_clk_fre/2-1;
  30. parameter p_spi_cnt_max = p_spi_frame_width*2-1;
  31. parameter p_spi_ins_max = p_spi_ins_width*2-1;
  32. //位宽计算函数
  33. function integer clogb2 (input integer depth);
  34. begin
  35.     for (clogb2=0; depth>0; clogb2=clogb2+1) 
  36.         depth = depth >>1;                          
  37. end
  38. endfunction
  39. //把最大值赋值给线型，直接用p_clk_div仿真有问题，但实际上板是可以的
  40. wire [clogb2(p_clk_div)-1:0] w_clk_div;
  41. assign w_clk_div = p_clk_div;
  42. 时钟分频
  43. reg [clogb2(p_clk_div)-1:0] r_cnt_div = 'd0;
  44. always @(posedge i_clk)
  45. begin
  46.     if (r_cnt_div == w_clk_div)
  47.         r_cnt_div <= 'd0;
  48.     else 
  49.         r_cnt_div <= r_cnt_div + 'd1;
  50. end //always
  51. wire w_clk_en; //分频时钟使能
  52. assign w_clk_en = (r_cnt_div == w_clk_div) ? 1'b1 : 1'b0;
  53. reg [1:0] r_flag_edge = 2'b00;
  54. reg [clogb2(p_spi_cnt_max)-1:0] r_spi_cnt = 'd0;
  55. always @(posedge i_clk) //flag边沿检测
  56. begin
  57.     r_flag_edge <= {r_flag_edge[0],i_flag};
  58. end
  59. //flag信号展宽到低速时钟域
  60. reg r_flag_enlarge = 1'b0;
  61. always @(posedge i_clk)
  62. begin
  63.     if (r_flag_edge == 2'b01) //上升沿拉高
  64.         r_flag_enlarge <= 1'b1;
  65.     else if (r_spi_cnt == p_spi_ins_max) //足够长的高电平才拉低
  66.         r_flag_enlarge <= 1'b0;
  67. end
  68. reg [1:0] r_flag_enlarge_edge = 2'b00;
  69. always @(posedge i_clk)
  70. begin
  71.     if (w_clk_en)
  72.         r_flag_enlarge_edge <= {r_flag_enlarge_edge[0],r_flag_enlarge};
  73. end
  74. reg r_cs = 1'b1;
  75. always @(posedge i_clk)
  76. begin
  77.     if (w_clk_en)
  78.     begin
  79.         if (r_flag_enlarge_edge == 2'b01) //检测到需要进行SPI操作
  80.             r_cs <= 1'b0;
  81.         else if (r_spi_cnt == p_spi_cnt_max) //计数到最大值表示一次SPI完成
  82.             r_cs <= 1'b1;
  83.     end
  84. end
  85. always @(posedge i_clk)
  86. begin
  87.     if (w_clk_en)
  88.     begin
  89.         if(~r_cs) //在操作区间计数
  90.             r_spi_cnt <= r_spi_cnt + 'd1;
  91.         else 
  92.             r_spi_cnt <= 'd0;
  93.     end    
  94. end
  95. 数据传输段
  96. reg [p_spi_frame_width-1:0] r_data = 'd0;
  97. always @(posedge i_clk)
  98. begin
  99.     if (w_clk_en)
  100.     begin
  101.         if (r_flag_enlarge_edge == 2'b01) //上升沿刷入
  102.             r_data <= i_spi_data;
  103.         else if (r_spi_cnt[0] == 1'b1) //数据移动
  104.             r_data <= {r_data[p_spi_frame_width-2:0],1'b1};
  105.     end
  106. end
  107. 数据读取段
  108. reg [p_spi_data_width-1:0] r_data_read = 'd0;
  109. always @(posedge i_clk)
  110. begin
  111.     if (w_clk_en)
  112.     begin
  113.         if (i_spi_data[p_spi_frame_width-1] && (r_spi_cnt > p_spi_ins_max) && (r_spi_cnt[0] == 1'b0)) //是读
  114.         `ifdef SPI_LINE
  115.             r_data_read <= {r_data_read[p_spi_data_width-2:0],io_spi_sdio};
  116.         `else
  117.             r_data_read <= {r_data_read[p_spi_data_width-2:0],i_spi_miso};
  118.         `endif 
  119.     end    
  120. end
  121. SPI输出段
  122. assign o_spi_cs = r_cs;
  123. assign o_spi_clk = r_cs ? 1'b0 : r_spi_cnt[0];
  124. SPI SDIO的输入输出切换
  125. `ifdef SPI_LINE
  126. assign io_spi_sdio = (i_spi_data[p_spi_frame_width-1]) ? (((r_spi_cnt >= 'd0) && (r_spi_cnt <= p_spi_ins_max)) ? r_data[p_spi_frame_width-1] : 1'bz ) : r_data[p_spi_frame_width-1];
  127. `else 
  128. assign o_spi_mosi = r_data[p_spi_frame_width-1];
  129. `endif 
  130. assign o_transfer_done = ((~r_cs) && (r_spi_cnt == p_spi_cnt_max)) ? 1'b1:1'b0;
  131. assign o_spi_data = r_data_read;
  133. endmodule // end the spi_master model

        3.前仿真代码

 

  1.  
  2. `define DATA 8'ha5
  3. //`define SPI_LINE
  4. timeunit 1ns;
  5. timeprecision 1ps;
  6. module top;
  7. parameter p_sim_end_time = 1000000; //ns
  8. logic l_clk = 1'b0;
  9. always #2.5 l_clk = ~l_clk;
  10. 复位
  11. logic l_rst_n  = 1'b0;
  12. initial begin
  13.     #100 l_rst_n = 1'b1;
  14. end
  15.  
  16.  
  17. wire io_sdio;
  18. wire o_spi_cs;
  19. wire o_spi_clk;
  20. wire o_transfer_done;
  21. wire [7:0] o_spi_data;
  22. 多个数据操作模式
  23. reg r_flag = 1'b0;
  24. reg [1:0] r_first_cnt = 2'b00;
  25. always @(posedge l_clk,negedge l_rst_n)
  26. begin
  27.     if (~l_rst_n)
  28.         r_first_cnt <= 2'b00;
  29.     else if (r_first_cnt == 2'd3)
  30.         r_first_cnt <= r_first_cnt;
  31.     else 
  32.         r_first_cnt <= r_first_cnt + 2'd1;
  33. end
  34. reg [1:0] r_transfer_done_edge = 2'b00;
  35. always @(posedge l_clk)
  36. begin
  37.     r_transfer_done_edge <= {r_transfer_done_edge[0],o_transfer_done};
  38. end
  39. reg [3:0] r_transfer_cnt = 4'd0;
  40. always @(posedge l_clk)
  41. begin
  42.     if ((r_first_cnt == 2'd2) && (r_transfer_cnt < `TRANSFER_NUMBER))
  43.         r_flag <= 1'b1;
  44.     else if ((r_transfer_done_edge == 2'b10) && (r_transfer_cnt < `TRANSFER_NUMBER-1))
  45.         r_flag <= 1'b1;
  46.     else 
  47.         r_flag <= 1'b0;        
  48. end
  49. always @(posedge l_clk)
  50. begin
  51.     if (r_transfer_done_edge == 2'b10)
  52.         r_transfer_cnt <= r_transfer_cnt + 'd1;
  53. end
  54. reg [15:0] r_in_data  = 16'd0;
  55. always @(*)
  56. begin
  57.     if (~l_rst_n) //仿真不执行此段仿真会有问题
  58.         r_in_data  = 16'h0000;
  59.     else 
  60.     begin 
  61.     case(r_transfer_cnt)
  62.         4'd0:begin  r_in_data  = {8'h00,8'h43}; end 
  63.         4'd1:begin  r_in_data  = 16'h0132; end 
  64.         4'd2:begin  r_in_data  = 16'h0245; end 
  65.         4'd3:begin  r_in_data  = 16'h0367; end 
  66.         4'd4:begin  r_in_data  = 16'h8000; end 
  67.         4'd5:begin  r_in_data  = 16'h8100; end 
  68.         4'd6:begin  r_in_data  = 16'h8200; end 
  69.         4'd7:begin  r_in_data  = 16'h8300; end 
  71.         default:begin  r_in_data  = 16'h0000; end
  72.     endcase
  73.     end 
  74. end
  75.  
  76. wire w_spi_miso;
  77. wire w_spi_mosi;
  78.  
  79. spi_master inst_spi_master (
  80.     .i_clk             (l_clk),
  81.     .i_rst_n           (),
  82.     .i_flag            (r_flag),
  83.     .i_spi_data        (r_in_data),
  84.     .o_spi_cs          (o_spi_cs),
  85.     .o_spi_clk         (o_spi_clk),
  86.     `ifdef SPI_LINE
  87.     .io_spi_sdio       (io_sdio),
  88.     `else
  89.     .i_spi_miso        (w_spi_miso),
  90.     .o_spi_mosi        (w_spi_mosi),
  91.     `endif
  92.     .o_transfer_done   (o_transfer_done),
  93.     .o_spi_data        (o_spi_data)
  94.     
  95. );
  96.  
  97. spi_slave  inst_spi_slave (
  98.     .i_clk                            (l_clk),
  99.     .i_rst_n                          (l_rst_n),
  100.  
  101.     .i_spi_clk                        (o_spi_clk),
  102.     .i_spi_cs                         (o_spi_cs),
  103.     `ifdef SPI_LINE
  104.     .io_spi_sdio                      (io_sdio)
  105.     `else
  106.     .i_spi_mosi                      (w_spi_mosi),
  107.     .o_spi_miso                      (w_spi_miso)
  108.     `endif
  109.  
  110. );
  111.  
  112. initial begin
  113.     #p_sim_end_time $stop;
  114. end
  115.  
  116.     
  117. endmodule

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