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vivado 时序约束_vivado timespec

作者：小丑西瓜9 | 2024-06-02 00:50:36

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vivado timespec

时间限制
以下ISE设计套件时序约束可以表示为XDC时序约束
Vivado设计套件。每个约束描述都包含一个UCF示例和
等效的XDC示例。
在未直接连接到边界的网络上创建时钟时，UCF和XDC不同
的设计（如端口）。在XDC中，当在上定义带有create_clock的主时钟时
net源点是网络的驱动引脚。
忽略该点之前的时钟插入延迟。计时时钟时可能会出现此问题
与另一个相关的时钟；偏斜将不准确。
使用create_clock Tcl命令
首先，要注意create_clock命令的不同起点如何影响计时
精确
在ISE中
在ISE中，以下时间限制是等效的：

NET "clk" TNM_NET = sys_clk;
TIMESPEC TS_sys_clk = PERIOD "sys_clk" 10 ns HIGH 50%;
NET "clk_IBUF_BUFG" TNM_NET = sys_clk;
TIMESPEC TS_sys_clk = PERIOD "sys_clk" 10 ns HIGH 50%;
In the Vivado Design Suite
In the Vivado Design Suite, the following create_clock constraints differ.
• create_clock -period 10.000 -name clk -waveform {0.000 5.000}
[get_ports clk]
• create_clock -period 10.000 -name clk -waveform {0.000 5.000}
[get_pins clk_IBUF_BUFG_inst/O]
约束不同，因为它们使用不同的起点来定义
Vivado IDE在计算松弛方程的时钟延迟和不确定性时进行分配。看见
如下图所示。
Vivado IDE忽略来自位于点上游的单元的所有时钟树延迟
其定义了主时钟。如果在
在设计中，只有一部分延迟用于时序分析。如果这个时钟
与设计中的其他相关时钟通信，因为偏斜，因此
时钟之间的值可能不准确。
在时钟树不位于
设计（例如输入端口或GT时钟输出引脚）。在的中间创建生成的时钟
仅设计。
时钟约束
Period
UCF Example
NET "clka" TNM_NET = "clka";
TIMESPEC "TS_clka" = PERIOD "clka" 13.330 ns
HIGH 50.00%;
XDC Example
create_clock -name clka -period 13.330 -
waveform {0 6.665}\ [get_ports clka]
Period Constraints with Uneven Duty Cycle
UCF Example
NET "clka" TNM_NET = "clka";
TIMESPEC "TS_clka" = PERIOD "clka" 13.330 ns HIGH 40.00%;
XDC Example
create_clock -name clka -period 13.330 -waveform {0 5.332}\[get_ports
clka]
Generated Clocks Constraints
UCF Example
NET "gen_clk" TNM_NET = "gen_clk";
TIMESPEC "TS_gen_clk" = PERIOD "gen_clk" "TS_clka" * 0.500 HIGH 50.00%;
XDC Example
create_generated_clock -source [get_ports clka] -name gen_clk\-
multiply_by 2 [get_ports gen_clk]
Period Constraints with LOW Keyword
UCF Example
NET "clka" TNM_NET = "clka";
TIMESPEC "TS_clka" = PERIOD "clka" 13.330 ns LOW 50.00%;
XDC Example
create_clock -name clka -period 13.330 -waveform {6.665 13.330}\
[get_ports clka]
Net PERIOD Constraints
UCF Example
NET "clk_bufg" PERIOD = 10 ns;
XDC Example
create_clock -name clk_bufg -period 10 -waveform {0 5}\
[get_pins clk_bufg/O}
Note : Unless there is specific reason to define the clock on bufg/O, define it at an upstream
top-level port.
OFFSET IN
BEFORE
UCF Example
OFFSET = IN 8 BEFORE clka;
XDC Example
set_input_delay -clock clka 2 [all_inputs]
Note : This assumes the clock period is 10 ns.
AFTER
UCF Example
OFFSET = IN 2 AFTER clka;
XDC Example
set_input_delay -clock clka 2 [all_inputs]
Note : This assumes the clock period is 10 ns.
BEFORE an Input Port Net
UCF Example
NET enable OFFSET = IN 8 BEFORE clka;
XDC Example
set_input_delay 2 [get_ports enable]
Note : This assumes the clock period is 10 ns.
BEFORE an Input Port Bus
UCF Example
INST "processor_data_bus[*]" TNM = "processor_bus";
TIMEGRP "processor_bus" OFFSET = IN 8ns BEFORE "clka";
XDC Example
set_input_delay 2 [get_ports {processor_data_bus[*]}]
Note : Offset is applied to ports only.
To TIMEGROUP
UCF Example
INST "input_ffs[*]" TNM = "input_ffs";
OFFSET = IN 8ns BEFORE "clka" TIMEGRP "input_ffs";
XDC Example
Manual conversion is required. For more information, see TimeGROUP .
FALLING/RISING Edge
UCF Example
OFFSET = IN 8ns BEFORE "clka" FALLING;
XDC Example
set_input_delay -clock clka 2 [all_inputs]
Note : This assumes the clock period is 10 ns.
LOW/HIGH Keyword
UCF Example
OFFSET = IN 8ns BEFORE "clka" HIGH;
XDC Example
Requires manual conversion.
Note : HIGH/LOW keywords are precursors to RISING/FALLING. RISING/FALLING is the
preferred method.
VALID Keyword
UCF Example
OFFSET = IN 1ns VALID 2ns BEFORE clka;
XDC Example
set_input_delay -clock clka -max 9 [all_inputs]
set_input_delay -clock clka -min 1[all_inputs]
Note : This assumes the clock period is 10 ns.
AFTER
UCF Example
OFFSET = OUT 12 AFTER clkc;
XDC Example
set_output_delay -clock clkc -max 8 [all_outputs]
Note : This assumes the clock period is 20 ns.
BEFORE
UCF Example
OFFSET = OUT 8 BEFORE clkc;
XDC Example
set_output_delay -clock clkc 8 [all_outputs]
Note : This assumes the clock period is 20 ns.
Output Net
UCF Example
NET out_net OFFSET = OUT 12 AFTER clkc;
XDC Example
set_output_delay 8 [get_port out_net]
Note : This assumes the clock period is 20 ns.
Group of Outputs
UCF Example
TIMEGRP outputs OFFSET = OUT 12 AFTER clkc;
XDC Example
set_output_delay -clock clkc 8 [get_ports outputs*]
Note : This assumes the clock period is 20 ns.
From a TIMEGROUP
UCF Example
OFFSET = OUT 1.2 AFTER clk TIMEGRP from_ffs;
XDC Example
Manual conversion is required.
FALLING/RISING Edges
UCF Example
OFFSET = OUT 12 AFTER clkc FALLING;
XDC Example
set_output_delay -clock clkc -clock_fall 8 [all_outputs]
LOW Keyword
UCF Example
OFFSET = OUT 12 AFTER clkc LOW;
XDC Example
Requires manual conversion.
Note : HIGH/LOW keywords are precursors to RISING/FALLING. RISING/FALLING is the
preferred method.
REFERENCE_PIN
UCF Example
TIMEGRP mac_ddr_out;
OFFSET = OUT AFTER clk REFERENCE_PIN clk_out RISING;
XDC Example
Requires manual conversion.
Note : REFERENCE_PIN acts as a reporting switch to instruct TRACE to output a bus skew
report. The Vivado Design Suite does not support this feature.
自：到约束
通常，UCF From:To约束会转换为set_max_delay或
set_min_delay XDC约束，与-from、-to和-through设计相关
论据。
UCF约束的目的是使用等效的XDC约束。而大多数UCF
约束是基于网络的，XDC约束必须构造到端口和引脚。
用于这些约束的有用XDC命令有：all_fanout、get_cell和get_pins
以及-from、-to和-through参数。
Assigning Timing Group to an Area Group
UCF Example
TIMEGRP clock_grp = AREA_GROUP clock_ag;
XDC Example
The Vivado Design Suite does not support this constraint in XDC.
EXCEPT
UCF Example
TIMEGRP my_group = FFS EXCEPT your_group;
XDC Example
The Vivado Design Suite does not support this constraint in XDC.
Between Groups
UCF Example
TIMESPEC TS_TIG = FROM reset_ff TO FFS TIG;
XDC Example
Manual conversion is required. Construct a set_false_path that covers the desired paths.
By Net
UCF Example
NET reset TIG;
XDC Example
set_false_path -through [get_nets reset]
A better approach is to find the primary reset port and use:
set_false_path -from [get_ports reset_port]
By Instance
UCF Example
INST reset TIG;
XDC Example
set_false_path -from [get_cells reset]
set_false_path -through [get_cells reset]
set_false_path -to [get_cells reset]
By Pin
UCF Example
PIN ff.d TIG;
XDC Example
set_false_path -to [get_pins ff/D]
set_false_path -from [get_pins ff/C]
set_false_path -through [get_pins lut/I0]
Specific Time Constraints
UCF Example
NET reset TIG = TS_fast TS_even_faster;
XDC Example
The Vivado Design Suite does not support this constraint in XDC.
Note : Constraint-specific TIG tries to disable timing through the net, but only for analysis of
the two referenced constraints.
MAXSKEW
UCF Example
NET local_clock MAXSKEW = 2ns;
XDC Example
The Vivado Design Suite does not support this constraint in XDC.
MAXDELAY
UCF Example
NET local_clock MAXDELAY = 2ns;
XDC Example
The Vivado Design Suite does not support this constraint in XDC. You can, however, use
set_max_delay for specifying the timing requirement for a valid timing path (synchronous
start point to synchronous Endpoint).
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