FPGA在校学习记录系列---实验5-60进制计数器的设计+开发板（Verilog HDL）_60进制可逆计数器有清零功能用verilog实现

此系列记录FPGA在学校的学习过程。

FPGA系列
需要用到的软硬件：
软件：Quartus II 15.0 (64-bit)

硬件：
5CEBA4F23C7芯片

1.创建新的工程和开发板烧录在下面链接

新建工程链接:
FPGA在校学习记录系列—新建一个FPGA工程编写程序并仿真（Verilog HDL）
开发板烧录链接:
FPGA在校学习记录系列—实验4不同状态的LED+开发板（Verilog HDL）


这次创建的新工程名字为：CNT_60

2.基础的60进制计数器

module CNT_60
#(
    parameter   CNT_MAX =   6249999 	//最大计数值 这里是0.25秒
)
(
	input  i_clk,
	input  clr,       //清零
	input  en,
	input  select,     //选择
	input  cin_units,
	
	output reg [3:0] units,  //个位
	output reg [7:0] units_display, //数码管显示个位
	output reg [3:0] tens,  //十位
	output reg [7:0] tens_display, //数码管显示十位
	output reg sec_clk,
	count_units
);
reg [31:0] count;


always @(posedge i_clk or negedge en)
begin
	if(!en) 
	begin
		count <=0;
		sec_clk=1;
	end 
	else
	begin
		if(count == CNT_MAX) 
		begin
			sec_clk = ~sec_clk;
			count <=0;
		end 
		else
		begin
			count <= count +1'b1;
		end
	end
end


always @(posedge sec_clk or negedge en or negedge clr)
begin
	if(!en)
	begin
		
	end
	else
	begin
		if(!clr) units <=0;		
		else 
		begin
			units <=(units == 4'h9)?0:(units + 1);	
			count_units = (units == 4'h9)?1:0;
		end
	end
end

always @(units)
begin

			case(units)
				4'h0:	units_display = 8'hC0;
				4'h1:	units_display = 8'hF9;
				4'h2:	units_display = 8'hA4;
				4'h3:	units_display = 8'hB0;
				4'h4:	units_display = 8'h99;
				4'h5:	units_display = 8'h92;
				4'h6:	units_display = 8'h82;
				4'h7:	units_display = 8'hF8;
				4'h8:	units_display = 8'h80;
				4'h9:	units_display = 8'h90;
			default: units_display = 8'hFF;
			endcase

end

always @(posedge count_units or negedge en or negedge clr)
begin
	if(!en)
	begin
		
	end
	else
	begin
		if(!clr) tens <=0;		
		else 
		begin
			tens <=(tens == 4'h5)?0:(tens + 1);	
		end
	end
end

always @(tens)
begin

			case(tens)
				4'h0:	tens_display = 8'hC0;
				4'h1:	tens_display = 8'hF9;
				4'h2:	tens_display = 8'hA4;
				4'h3:	tens_display = 8'hB0;
				4'h4:	tens_display = 8'h99;
				4'h5:	tens_display = 8'h92;
				4'h6:	tens_display = 8'h82;
				4'h7:	tens_display = 8'hF8;
				4'h8:	tens_display = 8'h80;
				4'h9:	tens_display = 8'h90;
			default: tens_display = 8'hFF;
			endcase

end


endmodule
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3.带暂停按键的60进制计数器

新增一个按键，暂停计数

module CNT_60
#(
    parameter   CNT_MAX =   6249999 	//最大计数值 这里是0.25秒
)
(
	input  i_clk,		//时钟
	input  clr,       //清零
	input  en,			//使能
	input  stop_cnt_60, //停止
	
	output reg [3:0] units,  //个位计数
	output reg [7:0] units_display, //数码管显示个位
	output reg [3:0] tens,  //十位计数
	output reg [7:0] tens_display, //数码管显示十位
	output reg sec_clk,		//分频后的第二个时钟
	cin_units		//个位进位标志		
);
reg [31:0] count;//时钟计数


always @(posedge i_clk or negedge en)
begin
	if(!en) 
	begin
		count <=0;
		sec_clk=1;
	end 
	else
	begin
		if(count == CNT_MAX) 
		begin
			sec_clk = ~sec_clk;
			count <=0;
		end 
		else
		begin
			count <= count +1'b1;
		end
	end
end


always @(posedge sec_clk or negedge en or negedge clr or negedge stop_cnt_60)
begin
	if(!en)
	begin
		units <= 4'h10;
	end
	else
	begin
		if(!clr) units <=0;		
		else 
		begin
			if(!stop_cnt_60) units <= units;
			else
			begin
				units <=(units == 4'h9)?0:(units + 1);	
				cin_units = (units == 4'h9)?1:0;
			end
		end
	end
end

always @(units)
begin

			case(units)
				4'h0:	units_display = 8'hC0;
				4'h1:	units_display = 8'hF9;
				4'h2:	units_display = 8'hA4;
				4'h3:	units_display = 8'hB0;
				4'h4:	units_display = 8'h99;
				4'h5:	units_display = 8'h92;
				4'h6:	units_display = 8'h82;
				4'h7:	units_display = 8'hF8;
				4'h8:	units_display = 8'h80;
				4'h9:	units_display = 8'h90;
			default: units_display = 8'hFF;
			endcase

end

always @(posedge cin_units or negedge en or negedge clr)
begin
	if(!en)
	begin
	tens <= 4'h10;
	end
	else
	begin
		if(!clr) tens <=0;		
		else 
		begin
			tens <=(tens == 4'h5)?0:(tens + 1);	
		end
	end
end

always @(tens)
begin

			case(tens)
				4'h0:	tens_display = 8'hC0;
				4'h1:	tens_display = 8'hF9;
				4'h2:	tens_display = 8'hA4;
				4'h3:	tens_display = 8'hB0;
				4'h4:	tens_display = 8'h99;
				4'h5:	tens_display = 8'h92;
				4'h6:	tens_display = 8'h82;
				4'h7:	tens_display = 8'hF8;
				4'h8:	tens_display = 8'h80;
				4'h9:	tens_display = 8'h90;
			default: tens_display = 8'hFF;
			endcase

end


endmodule
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