求数据绝对值的verilog_systemverilog 绝对值

//取绝对值

moduleabs(

                   input sclk,

                   input prst,

                   input en_p,

                   input signed[15:0] data_A,

                   input signed[15:0] data_B,

                   output reg[15:0]  data_outA=16'd0,

                   output reg[15:0]  data_outB=16'd0                 

);

 

always@(posedgesclk or posedge prst)

         begin

                   if(prst)

                            data_outA<= 16'd0;

                   else

                   if(en_p)

                            begin

                                     case(data_A[15])

                                               1'b0:data_outA <= data_A;                                     

                                               1'b1:data_outA <= ~data_A