VHDL实现计数器_vhdl计数器

10进制同步计数器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt10 IS
	PORT(clk:IN STD_LOGIC;
		data:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		co:OUT STD_LOGIC);
END cnt10;
ARCHITECTURE cnt10_behavior OF cnt10 IS
SIGNAL temp1:STD_LOGIC;
SIGNAL cnt:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
	PROCESS(clk)
	BEGIN
		IF(clk'EVENT AND clk='1')THEN        --一个时钟信号
			IF(cnt="1001")THEN	--10进制
				cnt<="0000";
				temp1<='0';
			ELSIF(cnt="1000")THEN
				temp1<='1';
				cnt<=cnt+1;
			ELSE
				cnt<=cnt+1;
			END IF;
		END IF;
	END PROCESS;
	co<=temp1;
	data<=cnt;
END cnt10_behavior;

16进制异步计数器

--定义底层文件：异步复位的D触发器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dtrigger IS
	PORT(d,clk,r:IN STD_LOGIC;
		q,dq:OUT STD_LOGIC);
END dtrigger;
ARCHITECTURE dtrigger_behavior OF dtrigger IS
BEGIN
	PROCESS(clk,r)
	BEGIN
		IF(r='0')THEN
			q<='0';
			qd<='1';
		ELSIF(cp'EVENT AND clk='1')THEN
			q<=d;
			qd<=NOT d;
		END IF;
	END PROCESS;
END dtrigger_behavior;

--顶层文件，元件例化
LIBRARY	IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY count16 IS
	PORT(clk:IN STD_LOGIC;
		r:IN STD_LOGIC;
		q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END count16;
ARCHITECTURE count16_behavior OF count16 IS
	COMPONENT dtrigger
		PORT(d,clk,r:IN STD_LOGIC;
		q,dq:OUT STD_LOGIC);
	END COMPONENT;
	SIGNAL temp:STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
	temp<=clk;
	G1:FOR i IN 0 TO 3 GENERATE
		dtriggerx:dtrigger PORT MAP(temp(i+1),temp(i),r,q(i),temp(i+1));
	END GENERATE G1;
END count16_behavior;