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module LED_water (clk,led);
input clk;
output [7:0] led;
reg [7:0] led;
integer p;reg clk_1Hz;
reg [7:0] current_state, next_state;always @(posedge clk) begin
if(p==25000000-1)begin
p=0;
clk_1Hz=~clk_1Hz;
end
else begin
p=p+1;
end
endparameter S0 = 8'b00000000;
parameter S1 = 8'b00000001;
parameter S2 = 8'b00000010;
parameter S3 = 8'b00000100;
parameter S4 = 8'b00001000;
parameter S5 = 8'b00010000;
parameter S6 = 8'b00100000;
parameter S7 = 8'b01000000;
parameter S8 = 8'b10000000;always @(posedge clk_1Hz) begin
current_state<=next_state;
endalways @(current_state) begin
case (current_state)
S0: next_state<=S1;
S1: next_state<=S2;
S2: next_state<=S3;
S3: next_state<=S4;
S4: next_state<=S5;
S5: next_state<=S6;
S6: next_state<=S7;
S7: next_state<=S8;
S8: next_state<=S0;
default: next_state<=S0;
endcase
end
always @(current_state) begin
case (current_state)
S0: led<=S0;
S1: led<=S1;
S2: led<=S2;
S3: led<=S3;
S4: led<=S4;
S5: led<=S5;
S6: led<=S6;
S7: led<=S7;
S8: led<=S8;
default: led<=S0;
endcase
end
endmodule
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