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本附录将介绍1.7版本的 S D C ( S y n o p s y s D e s i g n C o n s t r a i n t s ) SDC(Synopsys\ Design\ Constraints) SDC(Synopsys Design Constraints)格式,此格式主要用于指定设计的时序约束。它不包含任何特定工具的命令,例如链接(link)和编译(compile)。它是一个文本文件,可以手写或由程序创建,并由程序读取。某些 S D C SDC SDC命令仅适用于实现(implementation)或综合(synthesis),但是本附录会列出所有 S D C SDC SDC命令。
S
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C
SDC
SDC语法是基于
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C
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TCL
TCL的格式,即所有命令都遵循
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TCL
TCL语法。一个
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D
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SDC
SDC文件会在文件开头包含
S
D
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SDC
SDC版本号,其次是设计约束,注释(注释以字符#
开始,并在行尾处结束)在
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D
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SDC
SDC文件中可以散布在设计约束中。设计约束中较长的命令行可以使用反斜杠(\
)字符分成多行。
以下是基本的 S D C SDC SDC命令:
========================================================================= current_instance [instance_pathname] # Sets the current instance of design. This allows other # commands to set or get attributes from that instance. # If no argument is supplied, then the current instance # becomes the top-level. Examples: current_instance /core/U2/UPLL current_instance .. # Go up one hierarchy. current_instance # Set to top. ========================================================================= expr arg1 arg2 . . . argn ========================================================================= list arg1 arg2 . . . argn ========================================================================= set variable_name value ========================================================================= set_hierarchy_separator separator # Specifies the default hierarchy separator used within # the SDC file. This can be overridden by using the -hsc # option in the individual SDC commands where allowed. Examples: set_hierarchy_separator / set_hierarchy_separator . ========================================================================= set_units [-capacitance cap_unit] [-resistance res_units] [-time time_unit] [-voltage voltage_unit] [-current current_unit] [-power power_unit] # Specifies the units used in the SDC file. Examples: set_units -capacitance pf -time ps =========================================================================
以下命令指明了如何访问一个设计实例中的对象:
========================================================================= all_clocks # Returns a collection of all clocks. Examples: foreach_in_collection clkvar [all_clocks] { . . . } set_clock_transition 0.150 [all_clocks] ========================================================================= all_inputs [-level_sensitive] [-edge_triggered] [-clock clock_name] # Returns a collection of all input ports in the design. Example: set_input_delay -clock VCLK 0.6 -min [all_inputs] ========================================================================= all_outputs [-level_sensitive] [-edge_triggered] [-clock clock_name] # Returns a collection of all output ports in the design. Example: set_load 0.5 [all_outputs] ========================================================================= all_registers [-no_hierarchy] [-clock clock_name] [-rise_clock clock_name] [-fall_clock clock_name] [-cells] [-data_pins] [-clock_pins] [-slave_clock_pins] [-async_pins] [-output_pins] [-level_sensitive] [-edge_triggered] [-master_slave] # Returns the set of registers with the properties # as specified, if any. Examples: all_registers -clock DAC_CLK # Returns all registers clocked by clock DAC_CLK. ========================================================================= current_design [design_name] # Returns the name of the current design. If specified with # an argument, it sets the current design to the one # specified. Examples: current_design FADD # Sets the current context to FADD. current_design # Returns the current context. ========================================================================= get_cells [-hierarchical] [-hsc separator] [-regexp] [-nocase] [-of_objects objects] patterns # Returns a collection of cells in the design that match the # specified pattern. Wildcard can be used to match # multiple cells. Examples: get_cells RegEdge* # Returns all cells that # match pattern. foreach_in_collection cvar [get_cells -hierarchical *] { . . . } # Returns all cells in design by searching # recursively down the hierarchy. ========================================================================= get_clocks [-regexp] [-nocase] patterns # Returns a collection of clocks in the design that match # the specified pattern. When used in context such as -from # or -to, it returns a collection of all flip-flops driven # by the specified clocks. Examples: set_propagated_clock [get_clocks SYS_CLK] set_multicycle_path -to [get_clocks jtag*] ========================================================================= get_lib_cells [-hsc separator] [-regexp] [-nocase] patterns # Creates a collection of library cells that are currently # loaded and those that match the specified pattern. Example: get_lib_cells cmos13lv/AOI3* ========================================================================= get_lib_pins [-hsc separator] [-regexp] [-nocase] patterns # Returns a collection of library cell pins that match the # specified pattern. ========================================================================= get_libs [-regexp] [-nocase] patterns # Returns a collection of libraries that are currently # loaded in the design. ========================================================================= get_nets [-hierarchical] [-hsc separator] [-regexp] [-nocase] [-of_objects objects] patterns # Returns a collection of nets that match the specified # pattern. Examples: get_nets -hierarchical * # Returns list of all nets in # design by searching recursively down the hierarchy. get_nets FIFO_patt* ========================================================================= get_pins [-hierarchical] [-hsc separator] [-regexp] [-nocase] [-of_objects objects] patterns # Returns a collection of pin names that match the # specified pattern. Examples: get_pins * get_pins U1/U2/U3/UAND/Z ========================================================================= get_ports [-regexp] [-nocase] patterns # Returns a collection of port names (inputs and outputs) # of design that match the specified pattern. Example: foreach_in_collection port_name [get_ports clk*] { # For all ports that start with “clk”. . . . } =========================================================================
可以在不“获取”对象的情况下引用诸如端口(port)之类的对象吗?当设计中只有一个具有该名称的对象时,实际上没有任何区别。但是,当多个对象具有相同的名称时,使用get_ *
命令将变得更加重要,它可以避免在引用哪种类型对象方面所带来的任何可能的混淆。假设有一个名为
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_
N
1
BIST\_N1
BIST_N1的网络和一个名为
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I
S
T
_
N
1
BIST\_N1
BIST_N1的端口,考虑以下
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D
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SDC
SDC命令:
set_load 0.05 BIST_N1
问题是要引用哪个 B I S T _ N 1 BIST\_N1 BIST_N1?网络还是端口?在大多数情况下,最好明确表明对象的类型,例如:
set_load 0.05 [get_nets BIST_N1]
现在再假设有一个时钟 M C L K MCLK MCLK和另一个也称为 M C L K MCLK MCLK的端口,考虑以下 S D C SDC SDC命令:
set_propagated_clock MCLK
该对象是引用名为
M
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L
K
MCLK
MCLK的端口还是引用称为
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C
L
K
MCLK
MCLK的时钟?在此特定情况下,它指的是时钟,因为这是set_propagated_clock
命令的优先级所选择的。但是,要明确一点,最好明确表明对象类型,如下所示:
set_propagated_clock [get_clocks MCLK]
set_propagated_clock [get_ports MCLK]
有了这种明确的条件申明,就不必依赖优先级规则了,并且 S D C SDC SDC命令会非常清楚。
该部分描述与时序约束相关的 S D C SDC SDC命令:
========================================================================= create_clock -period period_value [-name clock_name] [-waveform edge_list] [-add] [source_objects] # Defines a clock. # When clock_name is not specified, the clock name is the # name of the first source object. # The -period option specifies the clock period. # The -add option is used to create a clock at a pin that # already has an existing clock definition. Else if this # option is not used, this clock definition overrides any # other existing clock definition at that node. # The -waveform option specifies the rising edge and # falling edge (duty cycle) of the clock. The default # is (0, period/2). If a clock definition is on a path # after another clock, then it blocks the previous clock # from that point onwards. Examples: create_clock -period 20 -waveform {0 6} -name SYS_CLK \ [get_ports SYS_CLK] # Creates a clock of period # 20ns with rising edge at 0ns and the falling edge # at 6ns. create_clock -name CPU_CLK -period 2.33 \ -add [get_ports CPU_CLK] # Adds the clock definition # to the port without overriding any existing # clock definitions. ========================================================================= create_generated_clock [-name clock_name] -source master_pin [-edges edge_list] [-divide_by factor] [-multiply_by factor] [-duty_cycle percent] [-invert] [-edge_shift shift_list] [-add] [-master_clock clock] [-combinational] source_objects # Defines an internally generated clock. # If no -name is specified, the clock name is that of the # first source object. # The source of the generated clock, specified by -source, # is a pin or port in the design. # If more than one clock feeds the source node, # the -master_clock option must be used to specify which of # these clocks to use as the source of the generated clock. # The -divide_by option can be used to specify the clock # division factor; similarly for -multiply_by. # The -duty_cycle can be used to specify the new duty cycle # for clock multiplication. # The -invert option can be specified if the phase of the # clock has been inverted. # Instead of using clock multiplication or division, clock # generation can also be specified using -edges # and -edge_shift options. The -edges option specifies a # list of three numbers specifying the edges of the master # clock edges to use for the first rising edge, the next # falling edge, and the next rising edge. For example, a # clock divider can be specified as -divide_by 2 or # as -edges {1 3 5}. # The -edge_shift option can be used in conjunction with # the -edges option to specify an amount to shift for each # of the three edges. Examples: create_generated_clock -divide_by 2 -source \ [get_ports sys_clk] -name gen_sys_clk [get_pins UFF/Q] create_generated_clock -add -invert -edges {1 2 8} \ -source [get_ports mclk] -name gen_clk_div create_generated_clock -multiply_by 3 -source \ [get_ports ref_clk] -master_clock clk10MHz \ [get_pins UPLL/CLKOUT] -name gen_pll_clk ========================================================================= group_path [-name group_name] [-default] [-weight weight_value] [-from from_list] [-rise_from from_list] [-fall_from from_list] [-to to_list] [-rise_to to_list] [-fall_to to_list] [-through through_list] [-rise_through through_list] [-fall_through through_list] # Gives a name to the specified group of paths. ========================================================================= set_clock_gating_check [-setup setup_value] [-hold hold_value] [-rise] [-fall] [-high] [-low] [object_list] # Provides the ability to specify a clock gating check on # any object. # Clock gating checks are performed only on gates that get # a clock signal. # By default, the setup and hold values are 0. Examples: set_clock_gating_check -setup 0.15 -hold 0.05 \ [get_clocks ck20m] set_clock_gating_check -hold 0.3 \ [get_cells U0/clk_divider/UAND1] ========================================================================= set_clock_groups [-name name] [-logically_exclusive] [-physically_exclusive] [-asynchronous] [-allow_paths] -group clock_list # Specifies a group of clocks with the specific # property and assigns a name to the group. ========================================================================= set_clock_latency [-rise] [-fall] [-min] [-max] [-source] [-late] [-early] [-clock clock_list] delay object_list # Specifies the clock latency for a given clock. # There are two types of latency: network and source. # Source latency is the clock network delay between the # clock definition pin and its source, while network # latency is the clock network delay between the clock # definition pin and the flip-flop clock pins. Examples: set_clock_latency 1.86 [get_clocks clk250] set_clock_latency -source -late -rise 2.5 \ [get_clocks MCLK] set_clock_latency -source -late -fall 2.3 \ [get_clocks MCLK] ========================================================================= set_clock_sense [-positive] [-negative] [-pulse pulse] [-stop_propagation] [-clock clock_list] pin_list # Set clock property on pin. ========================================================================= set_clock_transition [-rise] [-fall] [-min] [-max] transition clock_list # Specifies the clock transition at the clock # definition point. Examples: set_clock_transition -min 0.5 [get_clocks SERDES_CLK] set_clock_transition -max 1.5 [get_clocks SERDES_CLK] ========================================================================= set_clock_uncertainty [-from from_clock] [-rise_from rise_from_clock] [-fall_from fall_from_clock] [-to to_clock] [-rise_to rise_to_clock] [-fall_to fall_to_clock] [-rise] [-fall] [-setup] [-hold] uncertainty [object_list] # Specifies the clock uncertainty for clocks or for # clock-to-clock transfers. # The setup uncertainty is subtracted from the data # required time for a path, and the hold uncertainty is # added to the data required time for each path. Examples: set_clock_uncertainty -setup -rise -fall 0.2 \ [get_clocks CLK2] set_clock_uncertainty -from [get_clocks HSCLK] -to \ [get_clocks SYSCLK] -hold 0.35 ========================================================================= set_data_check [-from from_object] [-to to_object] [-rise_from from_object] [-fall_from from_object] [-rise_to to_object] [-fall_to to_object] [-setup] [-hold] [-clock clock_object] value # Performs the specified check between the two pins. Example: set_data_check -from [get_pins UBLK/EN] \ -to [get_pins UBLK/D] -setup 0.2 set_disable_timing [-from from_pin_name] [-to to_pin_name] cell_pin_list # Disables a timing arc/edge inside the specified cell. Example: set_disable_timing -from A -to ZN [get_cells U1] ========================================================================= set_false_path [-setup] [-hold] [-rise] [-fall] [-from from_list] [-to to_list] [-through through_list] [-rise_from rise_from_list] [-rise_to rise_to_list] [-rise_through -rise_through_list] [-fall_from fall_from_list] [-fall_to fall_to_list] [-fall_through fall_through_list] # Specifies a path exception that is not to be considered # for STA. Examples: set_false_path -from [get_clocks jtag_clk] \ -to [get_clocks sys_clk] set_false_path -through U1/A -through U4/ZN ========================================================================= set_ideal_latency [-rise] [-fall] [-min] [-max] delay object_list # Sets ideal latency to specific objects. ========================================================================= set_ideal_network [-no_propagate] object_list # Identifies points in design that are sources of an # ideal network. ========================================================================= set_ideal_transition [-rise] [-fall] [-min] [-max] transition_time object_list # Specifies the transition time for the ideal networks # and ideal nets. ========================================================================= set_input_delay [-clock clock_name] [-clock_fall] [-rise] [-fall] [-max] [-min] [-add_delay] [-network_latency_included] [-source_latency_included] delay_value port_pin_list # Specifies the data arrival times at the specified input # ports relative to the clock specified. # The default is the rising edge of clock. # The -add_delay option allows the capability to add more # than one constraint to that particular pin or port. # Multiple input delays with respect to different clocks # can be specified using this -add_delay option. # By default, the clock source latency of the launch clock # is added to the input delay value, but when # the -source_latency_included option is specified, the # source network latency is not added because it is # assumed to be factored into the input delay value. # The -max delay is used for clock setup checks and recovery # checks, while the -min delay is used for hold and removal # checks. If only -min or -max or neither is specified, # the same value is used for both. Examples: set_input_delay -clock SYSCLK 1.1 [get_ports MDIO*] set_input_delay -clock virtual_mclk 2.5 [all_inputs] ========================================================================= set_max_delay [-rise] [-fall] [-from from_list] [-to to_list] [-through through_list] [-rise_from rise_from_list] [-rise_to rise_to_list] [-rise_through rise_through_list] [-fall_from fall_from_list] [-fall_to fall_to_list] [-fall_through fall_through_list] delay_value # Sets the maximum delay on the specified path. # This is used to specify delay between two arbitrary pins # instead of from a flip-flop to another flip-flop. Examples: set_max_delay -from [get_clocks FIFOCLK] \ -to [get_clocks MAINCLK] 3.5 set_max_delay -from [all_inputs] \ -to [get_cells UCKDIV/UFF1/D] 2.66 ========================================================================= set_max_time_borrow delay_value object_list # Sets the max time that can be borrowed when analyzing # a path to a latch. Example: set_max_time_borrow 0.6 [get_pins CORE/CNT_LATCH/D] ========================================================================= set_min_delay [-rise] [-fall] [-from from_list] [-to to_list] [-through through_list] [-rise_from rise_from_list] [-rise_to rise_to_list] [-rise_through rise_through_list] [-fall_from fall_from_list] [-fall_to fall_to_list] [-fall_through fall_through_list] delay_value # Sets the min delay for the specified path, which can # be between any two arbitrary pins. Examples: set_min_delay -from U1/S -to U2/A 0.6 set_min_delay -from [get_clocks PCLK] \ -to [get_pins UFF/*/S] ========================================================================= set_multicycle_path [-setup] [-hold] [-rise] [-fall] [-start] [-end] [-from from_list] [-to to_list] [-through through_list] [-rise_from rise_from_list] [-rise_to rise_to_list] [-rise_through rise_through_list] [-fall_from fall_from_list] [-fall_to fall_to_list] [-fall_through fall_through_list] path_multiplier # Specifies a path as a multicycle path. Multiple -through # can also be specified. # Use the -setup option if the multicycle path is just for # setup. Use the -hold option if the multicycle path is # for hold. # If neither -setup nor -hold is specified, the default # is -setup and the default hold multiplier is 0. # The -start refers to the path multiplier being applied to # the launch clock, while -end refers to the path # multiplier being applied to the capture clock. # Default is -start. # The value of the -hold multiplier represents the number # of clock edges away from the default hold multicycle # value which is 0. Examples: set_multicycle_path -start -setup \ -from [get_clocks PCLK] -to [get_clocks MCLK] 4 set_multicycle_path -hold -from UFF1/Q -to UCNTFF/D 2 set_multicycle_path -setup -to [get_pins UEDGEFF*] 4 ========================================================================= set_output_delay [-clock clock_name] [-clock_fall] [-level_sensitive] [-rise] [-fall] [-max] [-min] [-add_delay] [-network_delay_included] [-source_latency_included] delay_value port_pin_list # Specifies the required time of the output relative # to the clock. The rising edge is default. # By default, the clock source latency is added to the # output delay value but when the -source_latency_included # option is specified, the clock latency value is not added # as it is assumed to be included in the output delay value. # The -add_delay option can be used to specify multiple # set_output_delay on a pin/port. ========================================================================= set_propagated_clock object_list # Specifies that clock latency needs to be computed, # that is, it is not ideal. Example: set_propagated_clock [all_clocks] =========================================================================
本部分描述用于建立 D U A DUA DUA环境的命令:
set_case_analysis value port_or_pin_list # Specifies the port or pin that is set to # the constant value. Examples: set_case_analysis 0 [get_pins UDFT/MODE_SEL] set_case_analysis 1 [get_ports SCAN_ENABLE] set_drive [-rise] [-fall] [-min] [-max] resistance port_list # Is used to specify the drive strength of the input port. # It specifies the external drive resistance to the port. # A value of 0 signifies highest drive strength. Example: set_drive 0 {CLK RST} set_driving_cell [-lib_cell lib_cell_name] [-rise] [-fall] [-library lib_name] [-pin pin_name] [-from_pin from_pin_name] [-multiply_by factor] [-dont_scale] [-no_design_rule] [-input_transition_rise rise_time] [-input_transition_fall fall_time] [-min] [-max] [-clock clock_name] [-clock_fall] port_list # Is used to model the drive resistance of the cell # driving the input port. Example: set_driving_cell -lib_cell BUFX4 -pin ZN [all_inputs] set_fanout_load value port_list # Sets the specified fanout load on the output ports. Example: set_fanout_load 5 [all_outputs] set_input_transition [-rise] [-fall] [-min] [-max] [-clock clock_name] [-clock_fall] transition port_list # Specifies the transition time on an input pin. Examples: set_input_transition 0.2 \ [get_ports SD_DIN*] set_input_transition -rise 0.5 \ [get_ports GPIO*] set_load [-min] [-max] [-subtract_pin_load] [-pin_load] [-wire_load] value objects # Set the value of capacitive load on pin or net in design. # The -subtract_pin_load option specifies to subtract the # pin cap from the indicated load. Examples: set_load 50 [all_outputs] set_load 0.1 [get_pins UFF0/Q] # On an internal pin. set_load -subtract_pin_load 0.025 \ [get_nets UCNT0/NET5] # On a net. set_logic_dc port_list set_logic_one port_list set_logic_zero port_list # Sets the specified ports to be a don’t care value, # a logic one or a logic zero. Examples: set_logic_dc SE set_logic_one TEST set_logic_zero [get_pins USB0/USYNC_FF1/Q] set_max_area area_value # Sets the max area limit for current design. Example: set_max_area 20000.0 set_max_capacitance value object_list # Specifies the max capacitance for ports or on a design. # If for a design, it specifies the max capacitance for all # pins in the design. Examples: set_max_capacitance 0.2 [current_design] set_max_capacitance 1 [all_outputs] set_max_fanout value object_list # Specifies the max fanout value for ports or on a design. # If for a design, it specifies the max fanout for all # output pins in the design. Examples: set_max_fanout 16 [get_pins UDFT0/JTAG/ZN] set_max_fanout 50 [current_design] set_max_transition [-clock_path] [-data_path] [-rise] [-fall] value object_list # Specifies the max transition time on a port or # on a design. If for a design, it specifies the max # transition on all pins in a design. Example: set_max_transition 0.2 UCLKDIV0/QN set_min_capacitance value object_list # Specifies a minimum capacitance value for a port # or on pins in design. Example: set_min_capacitance 0.05 UPHY0/UCNTR/B1 set_operating_conditions [-library lib_name] [-analysis_type type] [-max max_condition] [-min min_condition] [-max_library max_lib] [-min_library min_lib] [-object_list objects] [condition] # Sets the specified operating condition for timing # analysis. Analysis type can be single, bc_wc, or # on_chip_variation. Operating conditions are defined in # libraries using the operating_conditions command. Examples: set_operating_conditions -analysis_type bc_wc set_operating_conditions WCCOM set_operating_conditions -analysis_type \ on_chip_variation set_port_fanout_number value port_list # Sets maximum fanout of a port. Example: set_port_fanout_number 10 [get_ports GPIO*] set_resistance [-min] [-max] value list_of_nets # Sets the resistance on the specified nets. Examples: set_resistance 10 -min U0/U1/NETA set_resistance 50 -max U0/U1/NETA set_timing_derate [-cell_delay] [-cell_check] [-net_delay] [-data] [-clock] [-early] [-late] derate_value [object_list] # Specifies derating values. set_wire_load_min_block_size size # Specifies the minimum block size to be used when the # wire load mode is set to enclosed. Example: set_wire_load_min_block_size 5000 set_wire_load_mode mode_name # Defines the mechanism of how a wire load model is to be # used for nets in a hierarchical design. # The mode_name can be top, enclosed, or segmented. # The top mode causes the wire load model defined in the # top-level of the hierarchy to be used at all lower levels. # The enclosed mode causes the wire load model of the block # that fully encloses that net to be used for that net. # The segmented mode causes net segment in the block to use # the block’s wire load model. Example: set_wire_load_mode enclosed set_wire_load_model -name model_name [-library lib_name] [-min] [-max] [object_list] # Defines the wire load model to be used for the current # design or for the specified nets. Example: set_wire_load_model -name “eSiliconLightWLM” set_wire_load_selection_group [-library lib_name] [-min] [-max] group_name [object_list] # Sets the wire load selection group for a design when # determining wire load model based on cell area of the # blocks. Selection groups are typically defined in # technology libraries.
当设计中存在多电压岛(multi-voltage islands)时,以下命令适用。
create_voltage_area -name name [-coordinate coordinate_list] [-guard_band_x float] [-guard_band_y float] cell_list set_level_shifter_strategy [-rule rule_type] set_level_shifter_threshold [-voltage float] [-percent float] set_max_dynamic_power power [unit] # Specify max dynamic power. Example: set_max_dynamic_power 0 mw set_max_leakage_power power [unit] # Specify max leakage power. Example: set_max_leakage_power 12 mw
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