[SV]SystemVerilog Interview Questions_system verilog interview assertion question

Below are the most frequently asked SystemVerilog Interview Questions(link),

1. What is the difference between an initial and final block of the systemverilog?
2. Explain the simulation phases of SystemVerilog verification?
3. What is the Difference between SystemVerilog packed and unpacked array?
4. What is "This " keyword in the systemverilog?
5. What is alias in SystemVerilog?
6. randomized in the systemverilog test bench?
7. in SystemVerilog which array type is preferred for memory declaration and why?
8. How to avoid race round condition between DUT and test bench in SystemVerilog verification?
9. What are the advantages of the systemverilog program block?
10. What is the difference between logic and bit in SystemVerilog?
11. What is the difference between datatype logic and wire?
12. What is a virtual interface?
13. What is an abstract class?
14. What is the difference between $random and $urandom?
15. What is the expect statements in assertions?
16. What is DPI?
17. What is the difference between == and === ?
18. What are the system tasks?
19. What is SystemVerilog assertion binding and advantages of it?
20. What are parameterized classes?
21. How to generate array without randomization?
22. What is the difference between always_comb() and always@(*)?
23. What is the difference between overriding and overloading?
24. Explain the difference between deep copy and shallow copy?
25. What is interface and advantages over the normal way?
26. What is modport and explain the usage of it?
27. What is a clocking block?
28. What is the difference between the clocking block and modport?
29. System Verilog Interview Questions, Below are the most frequently asked questions. 
30. What are the different types of verification approaches?
31. What are the basic testbench components?
32. What are the different layers of layered architecture?
33. What is the difference between a $rose and @ (posedge)?
34. What is the use of extern?
35. What is scope randomization?
36. What is the difference between blocking and non-blocking assignments?
37. What are automatic variables?
38. What is the scope of local and private variables?
39. How to check if any bit of the expression is X or Z?
40. What is the Difference between param and typedef?
41. What is `timescale?
42. Explain the difference between new( ) and new[ ] ?
43. What is the difference between task and function in class and Module?
44. Why always blocks are not allowed in the program block?
45. Why forever is used instead of always in program block?
46. What is SVA?
47. Explain the difference between fork-join, fork-join_none, and fork- join_any?
48. What is the difference between mailboxes and queues?
49. What is casting?
50. What is inheritance and polymorphism?
51. What is callback?
52. What is constraint solve-before?
53. What is coverage and what are different types?
54. What is the importance of coverage in SystemVerilog verification?
55. When you will say that verification is completed?
56. What are illegal bins? Is it good to use it and why?
57. What is the advantage of seed in randomization?
58. What is circular dependency?
59. What is “super “?
60. What is the input skew and output skew in the clocking block?
61. What is a static variable?
62. What is a package?
63. What is the difference between bit [7:0] and byte?
64. What is randomization and what can be 
65. What are the constraints? Is all constraints are bidirectional?
66. What are in line constraints?
67. What is the difference between rand and randc?
68. Explain pass by value and pass by ref?
69. What are the advantages of cross-coverage?
70. What is the difference between associative and dynamic array?
71. What is the type of SystemVerilog assertions?
72. What is the difference between $display,$strobe,$ monitor?
73. Can we write SystemVerilog assertions in class?
74. What is an argument pass by value and pass by reference?