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用PS控制PL_DDR读写测试_ps端读pl写入ddr的数据

作者：小蓝xlanll | 2024-04-27 19:12:30

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ps端读pl写入ddr的数据

用PS控制PL_DDR读写测试

项目功能：用**PS端**通过AXI4总线来**控制PL端DDR的读写**测试，并且改变测试频率，检测芯片性能。

目的：用PS端方便改写程序，烧录可以节省很多时间。

1.ZYNQ 芯片配置

  • UART1: I/O Configuration -> Low Speed -> I/O Peripherals -> UART1 (MIO24,25)
  • QSPI: I/O Configuration -> Low Speed -> Memory Interfaces -> 选中QSPI选项
  • 取消 pl_resetn0 接口: PS-PL Configuration -> Genaral -> 取消选项 Fabric Reset Enable
  • 启动AXI接口：PS-PL Configuration ->PS-PL Interfaces -> Master Interface -> 勾选 AXI HPM0 FPD,128位
  • Clock Configration 保持默认：33.333MHz
  • DDR Configration 如图所示:

在这里插入图片描述

2. DDR3 IP核配置

  • 频率计算示例：若想获得800M的读写速度，则配置DDR的 Memory Device Interface Speed 时，

    1/（800/2）=2500ps (双边沿读写，所以800/2)

  • 参考输入时钟（Reference Input Clock Speed）: 10000(100MHz)

其余配置如图所示:

在这里插入图片描述

在这里插入图片描述

3. 端口连接

  • 配置完这两个IP核后，选择自动连接。

  • 将DDR3 IP核的sys_rst端口删除.

  • 加入vio，进行以下连接：

​ clk(vio) -> pl_clk0(zynq) ;

​ probe_in0(vio) -> c0_init_calib_complete(ddr3) ;

​ probe_out0(vio) -> sys_rst(ddr3)

Block Design截图:

在这里插入图片描述

  • 添加约束文件（见附录）

  • 生成Bitstream

  • 导出硬件平台（包括bitstream文件）

4.vitis 设计

在创建工程时，选择Zynq MP DRAM tests 选项（平常是选择 Empty Application）

如何找到DDR的起始地址和长度？

在vitis中找到 platform.spr -> 点击Hardware Specification -> ddr3_0

Base Address : 起始地址

High Address : 最高位地址

二者相减+1 即为长度

如图，ddr3地址：

在这里插入图片描述

5.修改main.c

点开src文件，在xmt_main.c文件中进行修改

修改内容：

  1. 第71行

//#define XMT_DDR_MAX_SIZE (XMT_DDR_0_SIZE + XMT_DDR_1_SIZE)
#define XMT_DDR_MAX_SIZE 0x480000000U //ddr3的高地址+1

  1. 第662行 （main 函数里）

StartAddr = 0x400000000U; //ddr3起始地址

结果分析

连接好串口，输入7（读写2GB DDR内存）
程序会用13种读写方式来测试DDR，最后一个数据表示所用的时间（s）

在这里插入图片描述

在这里插入图片描述

可能出现的BUG

  • 工程创建在桌面上/C盘中，在导出XSA文件时可能没有反应
  • 串口连接不稳定（可能会断开连接）
  • 检测芯片的正确放置

  • 静态电流:0.3A
    程序烧录成功电流：0.5A

    串口连接注意方向（若反向，则测试版电流=设置的输入电流；再次连接好串口后，要重新拔插电脑上的串口线）

附录

1.约束文件

注意引出来的端口的名称可能要改

set_property PACKAGE_PIN AK2 [get_ports {ddrx_rtl_0_dq[34]}]
set_property PACKAGE_PIN AK3 [get_ports {ddrx_rtl_0_dq[32]}]
set_property PACKAGE_PIN AL1 [get_ports {ddrx_rtl_0_dq[36]}]
set_property PACKAGE_PIN AK1 [get_ports {ddrx_rtl_0_dq[37]}]
set_property PACKAGE_PIN AL3 [get_ports {ddrx_rtl_0_dqs_p[4]}]
set_property PACKAGE_PIN AL2 [get_ports {ddrx_rtl_0_dqs_n[4]}]
set_property PACKAGE_PIN AN1 [get_ports {ddrx_rtl_0_dq[39]}]
set_property PACKAGE_PIN AM1 [get_ports {ddrx_rtl_0_dq[38]}]
set_property PACKAGE_PIN AP3 [get_ports {ddrx_rtl_0_dq[35]}]
set_property PACKAGE_PIN AN3 [get_ports {ddrx_rtl_0_dq[33]}]
set_property PACKAGE_PIN AK4 [get_ports {ddrx_rtl_0_dq[44]}]
set_property PACKAGE_PIN AK5 [get_ports {ddrx_rtl_0_dq[45]}]
set_property PACKAGE_PIN AN4 [get_ports {ddrx_rtl_0_dq[46]}]
set_property PACKAGE_PIN AM4 [get_ports {ddrx_rtl_0_dq[47]}]
set_property PACKAGE_PIN AN6 [get_ports {ddrx_rtl_0_dqs_p[5]}]
set_property PACKAGE_PIN AP6 [get_ports {ddrx_rtl_0_dqs_n[5]}]
set_property PACKAGE_PIN AP4 [get_ports {ddrx_rtl_0_dq[40]}]
set_property PACKAGE_PIN AP5 [get_ports {ddrx_rtl_0_dq[43]}]
set_property PACKAGE_PIN AM5 [get_ports {ddrx_rtl_0_dq[42]}]
set_property PACKAGE_PIN AM6 [get_ports {ddrx_rtl_0_dq[41]}]
set_property PACKAGE_PIN AL7 [get_ports {ddrx_rtl_0_dq[55]}]
set_property PACKAGE_PIN AL8 [get_ports {ddrx_rtl_0_dq[50]}]
set_property PACKAGE_PIN AK7 [get_ports {ddrx_rtl_0_dq[49]}]
set_property PACKAGE_PIN AK8 [get_ports {ddrx_rtl_0_dq[54]}]
set_property PACKAGE_PIN AN7 [get_ports {ddrx_rtl_0_dqs_p[6]}]
set_property PACKAGE_PIN AP7 [get_ports {ddrx_rtl_0_dqs_n[6]}]
set_property PACKAGE_PIN AK9 [get_ports {ddrx_rtl_0_dq[53]}]
set_property PACKAGE_PIN AJ9 [get_ports {ddrx_rtl_0_dq[48]}]
set_property PACKAGE_PIN AM8 [get_ports {ddrx_rtl_0_dq[51]}]
set_property PACKAGE_PIN AM9 [get_ports {ddrx_rtl_0_dq[52]}]
set_property PACKAGE_PIN AK10 [get_ports {ddrx_rtl_0_dq[60]}]
set_property PACKAGE_PIN AJ10 [get_ports {ddrx_rtl_0_dq[57]}]
set_property PACKAGE_PIN AP9 [get_ports {ddrx_rtl_0_dq[62]}]
set_property PACKAGE_PIN AN9 [get_ports {ddrx_rtl_0_dq[56]}]
set_property PACKAGE_PIN AP11 [get_ports {ddrx_rtl_0_dqs_p[7]}]
set_property PACKAGE_PIN AP10 [get_ports {ddrx_rtl_0_dqs_n[7]}]
set_property PACKAGE_PIN AM10 [get_ports {ddrx_rtl_0_dq[59]}]
set_property PACKAGE_PIN AL10 [get_ports {ddrx_rtl_0_dq[58]}]
set_property PACKAGE_PIN AM11 [get_ports {ddrx_rtl_0_dq[63]}]
set_property PACKAGE_PIN AL11 [get_ports {ddrx_rtl_0_dq[61]}]
set_property PACKAGE_PIN AE1 [get_ports {ddrx_rtl_0_dq[70]}]
set_property PACKAGE_PIN AE2 [get_ports {ddrx_rtl_0_dq[65]}]
set_property PACKAGE_PIN AD1 [get_ports {ddrx_rtl_0_dq[69]}]
set_property PACKAGE_PIN AD2 [get_ports {ddrx_rtl_0_dq[66]}]
set_property PACKAGE_PIN AH1 [get_ports {ddrx_rtl_0_dqs_p[8]}]
set_property PACKAGE_PIN AJ1 [get_ports {ddrx_rtl_0_dqs_n[8]}]
set_property PACKAGE_PIN AF1 [get_ports {ddrx_rtl_0_dq[64]}]
set_property PACKAGE_PIN AF2 [get_ports {ddrx_rtl_0_dq[67]}]
set_property PACKAGE_PIN AH3 [get_ports {ddrx_rtl_0_dq[71]}]
set_property PACKAGE_PIN AG3 [get_ports {ddrx_rtl_0_dq[68]}]
set_property PACKAGE_PIN AF6 [get_ports diff_clock_rtl_0_clk_p]
set_property PACKAGE_PIN AG6 [get_ports diff_clock_rtl_0_clk_n]
set_property PACKAGE_PIN W1 [get_ports {ddrx_rtl_0_dq[3]}]
set_property PACKAGE_PIN W2 [get_ports {ddrx_rtl_0_dq[7]}]
set_property PACKAGE_PIN V1 [get_ports {ddrx_rtl_0_dq[2]}]
set_property PACKAGE_PIN V2 [get_ports {ddrx_rtl_0_dq[1]}]
set_property PACKAGE_PIN Y2 [get_ports {ddrx_rtl_0_dqs_p[0]}]
set_property PACKAGE_PIN Y1 [get_ports {ddrx_rtl_0_dqs_n[0]}]
set_property PACKAGE_PIN AA1 [get_ports {ddrx_rtl_0_dq[5]}]
set_property PACKAGE_PIN AA2 [get_ports {ddrx_rtl_0_dq[4]}]
set_property PACKAGE_PIN AC3 [get_ports {ddrx_rtl_0_dq[0]}]
set_property PACKAGE_PIN AB3 [get_ports {ddrx_rtl_0_dq[6]}]
set_property PACKAGE_PIN U4 [get_ports {ddrx_rtl_0_dq[12]}]
set_property PACKAGE_PIN U5 [get_ports {ddrx_rtl_0_dq[8]}]
set_property PACKAGE_PIN V3 [get_ports {ddrx_rtl_0_dq[9]}]
set_property PACKAGE_PIN V4 [get_ports {ddrx_rtl_0_dq[13]}]
set_property PACKAGE_PIN AB4 [get_ports {ddrx_rtl_0_dqs_p[1]}]
set_property PACKAGE_PIN AC4 [get_ports {ddrx_rtl_0_dqs_n[1]}]
set_property PACKAGE_PIN W4 [get_ports {ddrx_rtl_0_dq[10]}]
set_property PACKAGE_PIN W5 [get_ports {ddrx_rtl_0_dq[15]}]
set_property PACKAGE_PIN AA5 [get_ports {ddrx_rtl_0_dq[11]}]
set_property PACKAGE_PIN Y5 [get_ports {ddrx_rtl_0_dq[14]}]
set_property PACKAGE_PIN AA6 [get_ports {ddrx_rtl_0_dq[16]}]
set_property PACKAGE_PIN AA7 [get_ports {ddrx_rtl_0_dq[21]}]
set_property PACKAGE_PIN Y7 [get_ports {ddrx_rtl_0_dq[19]}]
set_property PACKAGE_PIN Y8 [get_ports {ddrx_rtl_0_dq[23]}]
set_property PACKAGE_PIN AB6 [get_ports {ddrx_rtl_0_dqs_p[2]}]
set_property PACKAGE_PIN AB5 [get_ports {ddrx_rtl_0_dqs_n[2]}]
set_property PACKAGE_PIN W6 [get_ports {ddrx_rtl_0_dq[17]}]
set_property PACKAGE_PIN W7 [get_ports {ddrx_rtl_0_dq[20]}]
set_property PACKAGE_PIN AC8 [get_ports {ddrx_rtl_0_dq[18]}]
set_property PACKAGE_PIN AB8 [get_ports {ddrx_rtl_0_dq[22]}]
set_property PACKAGE_PIN Y9 [get_ports {ddrx_rtl_0_dq[28]}]
set_property PACKAGE_PIN Y10 [get_ports {ddrx_rtl_0_dq[26]}]
set_property PACKAGE_PIN AA12 [get_ports {ddrx_rtl_0_dq[27]}]
set_property PACKAGE_PIN Y12 [get_ports {ddrx_rtl_0_dq[29]}]
set_property PACKAGE_PIN AB9 [get_ports {ddrx_rtl_0_dqs_p[3]}]
set_property PACKAGE_PIN AC9 [get_ports {ddrx_rtl_0_dqs_n[3]}]
set_property PACKAGE_PIN AA10 [get_ports {ddrx_rtl_0_dq[31]}]
set_property PACKAGE_PIN AA11 [get_ports {ddrx_rtl_0_dq[30]}]
set_property PACKAGE_PIN AB10 [get_ports {ddrx_rtl_0_dq[25]}]
set_property PACKAGE_PIN AB11 [get_ports {ddrx_rtl_0_dq[24]}]
set_property PACKAGE_PIN K15 [get_ports ddrx_rtl_0_ras_n]
set_property PACKAGE_PIN K13 [get_ports ddrx_rtl_0_cas_n]
set_property PACKAGE_PIN M13 [get_ports {ddrx_rtl_0_ba[2]}]
set_property PACKAGE_PIN N13 [get_ports {ddrx_rtl_0_ba[1]}]
set_property PACKAGE_PIN N8 [get_ports {ddrx_rtl_0_ba[0]}]
set_property PACKAGE_PIN K10 [get_ports {ddrx_rtl_0_cs_n[0]}]
set_property PACKAGE_PIN L12 [get_ports {ddrx_rtl_0_odt[0]}]
set_property PACKAGE_PIN N9 [get_ports ddrx_rtl_0_we_n]
set_property PACKAGE_PIN P10 [get_ports {ddrx_rtl_0_ck_p[0]}]
set_property PACKAGE_PIN P9 [get_ports {ddr3_ck_n[0]}]
set_property PACKAGE_PIN N11 [get_ports {ddrx_rtl_0_cke[0]}]
set_property PACKAGE_PIN M15 [get_ports {ddrx_rtl_0_addr[0]}]
set_property PACKAGE_PIN K14 [get_ports {ddrx_rtl_0_addr[1]}]
set_property PACKAGE_PIN L13 [get_ports {ddrx_rtl_0_addr[2]}]
set_property PACKAGE_PIN K16 [get_ports {ddrx_rtl_0_addr[3]}]
set_property PACKAGE_PIN L11 [get_ports {ddrx_rtl_0_addr[4]}]
set_property PACKAGE_PIN T8 [get_ports {ddrx_rtl_0_addr[5]}]
set_property PACKAGE_PIN R8 [get_ports {ddrx_rtl_0_addr[6]}]
set_property PACKAGE_PIN N12 [get_ports {ddrx_rtl_0_addr[7]}]
set_property PACKAGE_PIN M11 [get_ports {ddrx_rtl_0_addr[8]}]
set_property PACKAGE_PIN L16 [get_ports {ddrx_rtl_0_addr[9]}]
set_property PACKAGE_PIN L10 [get_ports {ddrx_rtl_0_addr[10]}]
set_property PACKAGE_PIN K12 [get_ports {ddrx_rtl_0_addr[11]}]
set_property PACKAGE_PIN M14 [get_ports {ddrx_rtl_0_addr[12]}]
set_property PACKAGE_PIN L15 [get_ports {ddrx_rtl_0_addr[13]}]
set_property PACKAGE_PIN P12 [get_ports {ddrx_rtl_0_addr[14]}]
set_property PACKAGE_PIN AC2 [get_ports {ddr3_dm[0]}]
set_property PACKAGE_PIN Y4 [get_ports {ddr3_dm[1]}]
set_property PACKAGE_PIN AC7 [get_ports {ddr3_dm[2]}]
set_property PACKAGE_PIN AC12 [get_ports {ddr3_dm[3]}]
set_property PACKAGE_PIN AN2 [get_ports {ddr3_dm[4]}]
set_property PACKAGE_PIN AL6 [get_ports {ddr3_dm[5]}]
set_property PACKAGE_PIN AN8 [get_ports {ddr3_dm[6]}]
set_property PACKAGE_PIN AJ12 [get_ports {ddr3_dm[7]}]
set_property PACKAGE_PIN AH2 [get_ports {ddr3_dm[8]}]

set_property IOSTANDARD SSTL15_DCI [get_ports {ddrx_rtl_0_addr[14]}]
set_property IOSTANDARD SSTL15_DCI [get_ports {ddrx_rtl_0_addr[13]}]
set_property IOSTANDARD SSTL15_DCI [get_ports {ddrx_rtl_0_addr[12]}]
set_property IOSTANDARD SSTL15_DCI [get_ports {ddrx_rtl_0_addr[11]}]
set_property IOSTANDARD SSTL15_DCI [get_ports {ddrx_rtl_0_addr[10]}]
set_property IOSTANDARD SSTL15_DCI [get_ports {ddrx_rtl_0_addr[9]}]
set_property IOSTANDARD SSTL15_DCI [get_ports {ddrx_rtl_0_addr[8]}]
set_property IOSTANDARD SSTL15_DCI [get_ports {ddrx_rtl_0_addr[7]}]
set_property IOSTANDARD SSTL15_DCI [get_ports {ddrx_rtl_0_addr[6]}]
set_property IOSTANDARD SSTL15_DCI [get_ports {ddrx_rtl_0_addr[5]}]
set_property IOSTANDARD SSTL15_DCI [get_ports {ddrx_rtl_0_addr[4]}]
set_property IOSTANDARD SSTL15_DCI [get_ports {ddrx_rtl_0_addr[3]}]
set_property IOSTANDARD SSTL15_DCI [get_ports {ddrx_rtl_0_addr[2]}]
set_property IOSTANDARD SSTL15_DCI [get_ports {ddrx_rtl_0_addr[1]}]
set_property IOSTANDARD SSTL15_DCI [get_ports {ddrx_rtl_0_addr[0]}]

####################################################################################
#Constraints from file : ‘xpm_cdc_gray.tcl’
####################################################################################

set_property IOSTANDARD LVCMOS18 [get_ports pl_clk0_0]

set_property PACKAGE_PIN E20 [get_ports pl_clk0_0]

###########################
#Constraints from file : ‘xpm_cdc_gray.tcl’
####################################################################################

set_property IOSTANDARD LVCMOS18 [get_ports pl_clk0_0]

set_property PACKAGE_PIN E20 [get_ports pl_clk0_0]

set_property PACKAGE_PIN P11 [get_ports ddrx_rtl_0_reset_n]

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