Verilog实现3-8译码器

3-8译码器真值表

verilog 代码

module yimaqi_3_8(date_in,out);

	input [2:0] date_in;	
	output reg [7:0]  out;
	
//always块描述的信号赋值，被赋值对象必须定义为reg类型
	always @ (*)  begin
		case(date_in)
			3'b000: out = 8'b0000_0001;
			3'b001: out = 8'b0000_0010;
			3'b010: out = 8'b0000_0100;
			3'b011: out = 8'b0000_1000;
			3'b100: out = 8'b0001_0000;
			3'b101: out = 8'b0010_0000;
			3'b110: out = 8'b0100_0000;
			3'b111: out = 8'b1000_0000;
		endcase
    end
endmodule
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激励代码

module yimaqi_3_8_tb;
    reg [2:0] dat_in;
	wire[7:0] out;
	
	yimaqi_3_8 yimaqiDemo(
				.date_in(dat_in),
				.out(out)
				);
				
	initial begin
	dat_in = 3'b000;
	#200;
	dat_in = 3'b001;
	#200;
	dat_in = 3'b010;
	#200;
	dat_in = 3'b011;
	#200;
	dat_in = 3'b100;
	#200;
	dat_in = 3'b101;
	#200;
	dat_in = 3'b110;
	#200;
	dat_in = 3'b111;
	#200;	
    end
endmodule
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仿真波形