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Vivado 3-8译码器 4-16译码器_virtuoso4-16译码器
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Vivado 摸鱼记录 Day_2 (*˘︶˘*).｡.:*♡
1.review
Day_1学习了vivado使用流程，与Verilog基础语法，实现二选一选择器
2. 3-8译码器
2.1分析
input:a,b,c;//三位拨码开关
output: [7:0]out;//8个led灯,高亮 8bit
2.2 design sources
| module decoder3_8 (input a , input b , input c , output reg [7:0] out); always@(*) begin case({a,b,c}) 3'b000 : out = 8'b0000_0001; ... ... 3'b111 : out = 8'b1000_0000; endcase end endmodule |
| output reg [7:0] out reg 在always@块中，被赋值对象类型为reg [7:0] out：位宽为8的一个向量{7,6,5,4,3,2,1,0} a_1 [7:0] :数组，深度为8，位宽为1 [7:0] a_2 [3:0] : 数组，深度为4，位宽为8 [7:0] a_3 [0:1][0:3] : 2行3列，位宽为8 |
| always@(*) 调用前面的 *所有的 case(a)//case语法 a_1: ; ... ... endcase {a,b,c}位拼接语法 相当于d = {a,b,c} 此时d是3'b 'b二进制 'd十进制 //默认 'h十六进制 |
2.2 simulation sources
| `timescale 1ns / 1ns module decoder3_8_tb(); reg s_a , s_b , s_c ; wire [7:0]out ; decoder3_8 decoder3_82(.a(s_a) , .b(s_b) , .c(s_c) , .out(out)); initial begin s_a = 0 ; s_b = 0 ; s_c = 0; #200; ... ... s_a = 1 ; s_b = 1 ; s_c = 1; #200; $stop; end endmodule |
3. 4-16译码器
input:a,b,c,d;//四位拨码开关
output: [7:0]out;//8个led灯,高亮 0-7 8 = 7+1，16 = 7/6/5亮三个
3.1 design sources
| module decoder4_16(input a , input b , input c , input d , output reg [7:0] out); begin |
3.2 simulation sources
| `timescale 1ns / 1ns module decoder4_16_tb(); reg s_a , s_b , s_c , s_d ; wire [7:0]out ; decoder4_16 decoder4_16_2(.a(s_a) , .b(s_b) , .c(s_c) , .d(s_d) , .out(out)); initial begin s_a = 0 ; s_b = 0 ; s_c = 0 ; s_d = 0 ; #200; s_a = 0 ; s_b = 0 ; s_c = 0 ; s_d = 1 ; #200; s_a = 0 ; s_b = 0 ; s_c = 1 ; s_d = 0 ; #200; s_a = 0 ; s_b = 0 ; s_c = 1 ; s_d = 1 ; #200; s_a = 0 ; s_b = 1 ; s_c = 0 ; s_d = 0 ; #200; s_a = 0 ; s_b = 1 ; s_c = 0 ; s_d = 1 ; #200; s_a = 0 ; s_b = 1 ; s_c = 1 ; s_d = 0 ; #200; s_a = 0 ; s_b = 1 ; s_c = 1 ; s_d = 1 ; #200; s_a = 1 ; s_b = 0 ; s_c = 0 ; s_d = 0 ; #200; s_a = 1 ; s_b = 0 ; s_c = 0 ; s_d = 1 ; #200; s_a = 1 ; s_b = 0 ; s_c = 1 ; s_d = 0 ; #200; s_a = 1 ; s_b = 0 ; s_c = 1 ; s_d = 1 ; #200; s_a = 1 ; s_b = 1 ; s_c = 0 ; s_d = 0 ; #200; s_a = 1 ; s_b = 1 ; s_c = 0 ; s_d = 1 ; #200; s_a = 1 ; s_b = 1 ; s_c = 1 ; s_d = 0 ; #200; s_a = 1 ; s_b = 1 ; s_c = 1 ; s_d = 1 ; #200; $stop; end endmodule |
// 摸鱼结束(*˘︶˘*).｡.:*♡
