Vivado FFT IP核学习

FFT IP核配置

1.点击ip catalog，输入FFT，选择FFT IP核，打开如下界面进行配置
:
2.点击implementation，进行如下配置
3.点击detailed implementation，可进一步配置

4.查看配置完的情况
以及

IP核例化

编写如下代码

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2021/07/30 13:01:15
// Design Name: 
// Module Name: fft_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module fft_top(
input logic aclk,
input logic aresetn,
//input data
input logic [31:0] s_axis_data_tdata,                      // input wire [31 : 0] s_axis_data_tdata
input logic s_axis_data_tvalid,                    // input wire s_axis_data_tvalid
output logic s_axis_data_tready,                    // output wire s_axis_data_tready
input logic s_axis_data_tlast,                      // input wire s_axis_data_tlast
//output result
output logic [47:0] m_axis_data_tdata,                      // output wire [47 : 0] m_axis_data_tdat
output logic [7:0] m_axis_data_tuser,                      // output wire [7 : 0] m_axis_data_tuser
output logic m_axis_data_tvalid,                    // output wire m_axis_data_tvalid
input logic m_axis_data_tready,                    // input wire m_axis_data_tready
output logic m_axis_data_tlast                      // output wire m_axis_data_tlast
    );

xfft_0 U (
  .aclk(aclk),                                                // input wire aclk
  .aresetn(aresetn),                                          // input wire aresetn
  .s_axis_config_tdata(8'd1),                                // input wire [7 : 0] s_axis_config_tdata
  .s_axis_config_tvalid(1'b1),                               // input wire s_axis_config_tvalid
  .s_axis_config_tready(),                                   // output wire s_axis_config_tready
  .s_axis_data_tdata(s_axis_data_tdata),                      // input wire [31 : 0] s_axis_data_tdata
  .s_axis_data_tvalid(s_axis_data_tvalid),                    // input wire s_axis_data_tvalid
  .s_axis_data_tready(s_axis_data_tready),                    // output wire s_axis_data_tready
  .s_axis_data_tlast(s_axis_data_tlast),                      // input wire s_axis_data_tlast
  .m_axis_data_tdata(m_axis_data_tdata),                      // output wire [47 : 0] m_axis_data_tdata
  .m_axis_data_tuser(m_axis_data_tuser),                      // output wire [7 : 0] m_axis_data_tuser
  .m_axis_data_tvalid(m_axis_data_tvalid),                    // output wire m_axis_data_tvalid
  .m_axis_data_tready(1'b1),                    // input wire m_axis_data_tready
  .m_axis_data_tlast(m_axis_data_tlast),                      // output wire m_axis_data_tlast
  .event_frame_started(),                  // output wire event_frame_started
  .event_tlast_unexpected(),            // output wire event_tlast_unexpected
  .event_tlast_missing(),                  // output wire event_tlast_missing
  .event_status_channel_halt(),      // output wire event_status_channel_halt
  .event_data_in_channel_halt(),    // output wire event_data_in_channel_halt
  .event_data_out_channel_halt()  // output wire event_data_out_channel_halt
);
endmodule

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因为我们实现正向FFT，所以config_data设为1

编写测试平台进行仿真测试

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2021/07/30 13:22:53
// Design Name: 
// Module Name: fft_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module fft_tb;
parameter N = 16;
logic aclk;
logic aresetn;
//
logic [31:0] data_in;
logic valid_in;
logic last_in;
logic ready_in;
//
logic [47:0] data_out;
logic valid_out;
logic last_out;
logic ready_out;
//
logic [31:0] data[N];
logic [31:0] count;
logic start;
logic [20:0] out_real;
logic [20:0] out_imag;
//start
initial begin
    start=0;
    #110
    start=1;
    #10
    start=0;
end
//
initial begin
    for(int i=0;i<N;i++)
        data[i]={16'd0,i<<11};                 //虚部，实部，16位定点数,15位是小数
end
//aclk
initial begin
    aclk=0;
    forever begin
        #5 aclk=~aclk;
    end
end
//aresetn
initial begin
    aresetn=0;
    #100
    aresetn=1;
end
//count
always_ff@(posedge aclk)
if(start)
    count<=0;
else if(ready_in&&valid_in)
    count<=count+1;
//data_in
always_comb
if(count<N)
    data_in=data[count];
else
    data_in=0;
//valid_in
always_ff @(posedge aclk) 
begin
if(start)
    valid_in<=1;
else if(count==N-1)
    valid_in<=0;
end
//last_in
assign last_in=(count==N-1)?1:0;
//ready_out
assign ready_out=1;
assign out_real=data_out[20:0];
assign out_imag=data_out[44:24];
//
fft_top U(
.aclk(aclk),
.aresetn(aresetn),
//input data
.s_axis_data_tdata(data_in),                      // input wire [31 : 0] s_axis_data_tdata
.s_axis_data_tvalid(valid_in),                    // input wire s_axis_data_tvalid
.s_axis_data_tready(ready_in),                    // output wire s_axis_data_tready
.s_axis_data_tlast(last_in),                      // input wire s_axis_data_tlast
//output result
.m_axis_data_tdata(data_out),                      // output wire [47 : 0] m_axis_data_tdat
.m_axis_data_tuser(),                      // output wire [7 : 0] m_axis_data_tuser
.m_axis_data_tvalid(valid_out),                    // output wire m_axis_data_tvalid
.m_axis_data_tready(ready_out),                    // input wire m_axis_data_tready
.m_axis_data_tlast(last_out)                      // output wire m_axis_data_tlast
    );
endmodule

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结果

python运行结果
仿真结果:

一定精度误差内，结果正确！

续：多通道FFT IP核

按照下图进行配置，其余和之前相同

配置完成后的具体信息，可以看到，输入数据的第0个通道，为0-31位，第一个通道，为32-63位，以此类推，配置信息和输出数据也类似。