Modelsim/QuestaSim教程——DO文件篇_do sim.do

如果你对Modelsim/QuestaSim还不是很熟悉，玩熟再来，点击转至《基础篇》。

你也可以在优酷看到演示的视频。

下面介绍使用DO文件实现自动仿真的功能。

先给个参考的文件/目录路径，建议大家按照这样的路径来放置文件。

源代码在最后面，先介绍如何配置它。

一、设置好testbench文件名。

不需要写后缀名，但必须是.v,.vt,.vhd,.vht文件（注意大小写）。

二、设置仿真时长。

三、自动编译文件或者使用文件列表。

当auto_add_file为1时，sim.do就会自动添加工程目录下的所有源文件，如果不希望它自动处理，可以把auto_add_file设为0，这样，sim.do会创建hdl_design_file_list.tcl文件(每一行前面加#号，代表不添加此文件)用于存放所有的源文件路径，然后还要使用af命令才能生效。

生成的文件列表，会跟工程目录下的一样（已经添加到工程的文件，前面没有#；未添加的，前面有#）。

四、设置备份工程的路径。

如果不需要备份工程的话，可以不管它。

五、设置显示器的分辨率，用于把wave窗口最大化。

六、设置源文件目录的路径。

请把你的源文件都放在工程目录下，do文件会自动找到工程目录下以及子目录下的所有.v，.vt，.vhd，.vht文件。注意这里的路径分隔符，是/，不是\。而且，一定要保留路径最后的/。

七、设置选择仿真库和仿真库的路径。

选择仿真库，这里可以选altera或者lattice。

设置仿真库路径：注意这里的路径分隔符，是/，不是\。路径最后不要加/。

八、选择工程所需的仿真库。

每一条lappend指令都对应着一个库，不需要该库可以注释掉（在前面加#号）。下图所示的是verilog仿真库。

下图所示的是vhdl仿真库。

九、介绍一些命令的别名。

ne新建工程，es加密源文件，ab添加仿真库，af添加文件，cf创建文件列表，cc编译修改过的源文件，cr清空控制台所有信息，ra执行仿真，df显示工程信息，dh显示帮助信息。所有命令的别名均只需左手就能输入了。

十、在wave窗口下，信号的进制、颜色等配置是可以复用的。

只需要在File->Save Format下，保存为wave.do文件(保存的路径要跟sim.do在同一目录下)，这样sim.do就会优先读取wave.do文件的配置信号，再进行仿真。

wave.do必须在工程目录下（子目录无效），否则会读不了。

十一、默认的wave颜色和进制。

就算有了wave.do，但是信号太多的时候，第一次还要一个个设置是比较麻烦的，所以提供了默认的wave颜色和进制。

请注意：使用了默认颜色之后，Modelsim/QuestaSim原先的颜色无效了。这时，可以在Msgs下看到信号的状态。

这里，rst对应橙色orange，而rst是正则表达式的关键词，也就是说，你把复位信号写成n_rst或者RST也能配对为橙色，不分大小写，其它关键词原理一样。这里提供了七种默认的关键词和颜色：

do文件的颜色可以设置为RGB形式（如"#F0F0F0"），也支持 X window的标准颜色名。

在set default_color命令下面，都是标准颜色名，以逗号分隔，使用时替换默认颜色(default_color)即可。

如果要修改关键词和进制（注释部分已提供进制的选项），可以在wave_style_set函数内部修改。

十二、显示工程相关信息。

使用df命令就可以显示工程相关的信息了。

十三、保存、载入vcd文件。

首先要用ra仿真，然后在控制台下输入sw，就直接把仿真后的波形保存为vcd文件（退出仿真之后才真正保存到波形），因为vcd相对于其它两种波形文件格式来说，更为通用些，所以只做这个功能，但是不建议使用do文件来保存，而是在testbench下使用系统函数来保存。

保存的vcd文件，如下图所示。

而aw后面加上vcd文件名，就可以载入vcd文件了(不需要写后缀.vcd)。

load_wave的功能有问题，请不要使用它。

十四、清空控制台的信息。

cr命令就可以清空了。

十五、加密源代码。

你可以使用es命令，把工程目录下所有的.v .vt .vhd .vht文件，都加密，并放在工程目录下的encrypt_src目录里面。

这样的话，就可以把一些IP加密了，但是最顶层的tb不要加密，不然没法看到波形了。

所以说，你把所有的已经加密好的其它文件，和不加密的tb文件都添加到工程，再用cc编译，ra运行仿真，就能看到波形了。

这样一来，你可以把你的源文件发到网上，让别人仿真，又不怕ip被偷了。加密后的文件，如下图所示。

注意，在使用加密命令之前得先把源代码编译通过。

十六、新建工程。

首先在前面设置好要新建的工程名和工程目录。

然后在控制台下面，使用ne命令后面跟着你要新建的工程名，即可以新建工程，并打开这个新工程，在新工程的路径下创建了src目录，和copy好sim.do文件。

效果如下图所示。

你还可以在以下命令下，修改新建工程的路径，但是必须使用do sim.do才能生效。

十七、输出报告。

如下图所示，使用wr命令，即可在工程目录下的report目录（自动创建）生成report.txt和instance.txt。

其中report.txt是生成的报告，里面有工程相关的信息，而instance.txt里面有仿真实例名。

使用show命令可以显示实例相关的信息，在instance.txt已经添加好show命令，只要copy一行到控制台里面运行就能看到结果了。

十八、备份工程。

如下图所示，br命令，后面要跟着你要添加的备注，一定要加双引号。

在备份目录下，就会备份当前的工程，以及增加一个README文件，这个文件里面的就是备注信息了。

十九、源代码。

请保存为sim.do文件，然后放在工程目录下。

######## this is a .do file running for modelsim or questasim ########
# you can copy the command as below to run it :


#           do sim.do


# testbench name without .v , .vt , .vhd , .vht
set testbench_name DDS_tb
# simulation time ; ns/us/ms/min
set sim_time 1us

# auto add files when $auto_add_file==1; add file list when $auto_add_file==0
quietly set auto_add_file 1

# project path
set prj_path D:/Projects/ProQuestaSim/DDS_sim/
# backup path
set bkp_path D:/Projects/ProQuestaSim/backup

# you can select "altera" or "lattice" device
quietly set device "altera"

# default wave color :         rst     clk      en    cnt    data     flag   default
quietly set default_color { "orange" "silver" "pink" "gold" "olive" "purple" "green" }
#################### standard X Window color name ####################
# alice blue, antique white, aqua, aquamarine, azure,
# beige, bisque, black, blanched almond, blue, blue violet, brown, burlywood,
# cadet blue, chartreuse, chocolate, coral, cornflower, cornsilk, crimson, cyan,
# dark blue, dark cyan, dark goldenrod, dark gray, dark green, dark khaki,
# dark magenta, dark olive green, dark orange, dark orchid, dark red,
# dark salmon, dark sea green, dark slate blue, dark slate gray, dark turquoise,
# dark violet, deep pink, deep sky blue, dim gray, dodger blue,
# firebrick, floral white, forest green, fuchsia,
# gainsboro, ghost white, gold, goldenrod, gray, green, green yellow,
# honeydew, hot pink, indian red, indigo, ivory, khaki,
# lavender, lavender blush, lawn green, lemon chiffon, light blue, light coral,
# light cyan, light goldenrod, light gray, light green,
# light pink, light salmon, light sea green, light sky blue, light slate gray,
# light steel blue, light yellow, lime, lime green, linen,
# magenta, maroon, medium aquamarine, medium blue, medium orchid, medium purple,
# medium sea green, medium slate blue, medium spring green, medium turquoise,
# medium violet red, midnight blue, mint cream, misty rose, moccasin
# navajo white, navy blue, old lace, olive, olive drab, orange, orange red, orchid,
# pale goldenrod, pale green, pale turquoise, pale violet red, papaya whip,
# peach puff, peru, pink, plum, powder blue, purple,
# rebecca purple, red, rosy brown, royal blue,
# saddle brown, salmon, sandy brown, sea green, seashell, sienna, silver,
# sky blue, slate blue, slate gray, snow, spring green, steel blue,
# tan, teal, thistle, tomato, turquoise, violet,
# wheat, white, white smoke, yellow, yellow green,
#######################################################################

# monitor resolution ratio , for example : 1920 x 1080
quietly set m_width 1920
quietly set m_height 1080

# altera simulation library path
quietly set altera_lib_path D:/altera/13.0sp1/quartus/eda/sim_lib
# lattice simulation library path
quietly set lattice_lib_path C:/lscc/diamond/1.4/cae_library/simulation

# add altera quartus simulation library
namespace eval lib_ns {
    proc lattice_lib_list {} {
        set lib_name {}
        # lappend lib_name ec
        # lappend lib_name ecp
        # lappend lib_name ecp2
        # lappend lib_name ecp3
        # lappend lib_name ecp5u
        # lappend lib_name lptm
        # lappend lib_name lptm2
        # lappend lib_name machxo
        lappend lib_name machxo2
        # lappend lib_name machxo3l
        # lappend lib_name pmi
        # lappend lib_name sc
        # lappend lib_name scm
        # lappend lib_name xp
        # lappend lib_name xp2
        return $lib_name
    }

    proc altera_verilog_lib_list {} {
        set lib_name {}
        ##################### verilog libraries ####################
        lappend lib_name 220model
        lappend lib_name altera_mf
        # lappend lib_name altera_primitives
        # lappend lib_name altera_primitives_quasar
        # lappend lib_name sgate
        # lappend lib_name arriagx_atoms
        # lappend lib_name arriagx_hssi_atoms
        # lappend lib_name arriaiigz_atoms
        # lappend lib_name arriaiigz_hssi_atoms
        # lappend lib_name arriaiigz_pcie_hip_atoms
        # lappend lib_name arriaii_atoms
        # lappend lib_name arriaii_hssi_atoms
        # lappend lib_name arriaii_pcie_hip_atoms
        # lappend lib_name arriavgz_atoms
        # lappend lib_name arriavgz_hssi_atoms
        # lappend lib_name arriavgz_pcie_hip_atoms
        # lappend lib_name arriav_atoms
        # lappend lib_name arriav_hssi_atoms
        # lappend lib_name arriav_pcie_hip_atoms
        # lappend lib_name cycloneiiils_atoms
        # lappend lib_name cycloneiii_atoms
        # lappend lib_name cycloneii_atoms
        # lappend lib_name cycloneive_atoms
        # lappend lib_name cycloneiv_atoms
        # lappend lib_name cycloneiv_hssi_atoms
        # lappend lib_name cycloneiv_pcie_hip_atoms
        # lappend lib_name cyclonev_atoms
        # lappend lib_name cyclonev_hssi_atoms
        # lappend lib_name cyclonev_pcie_hip_atoms
        # lappend lib_name cyclone_atoms
        # lappend lib_name hardcopyiii_atoms
        # lappend lib_name hardcopyii_atoms
        # lappend lib_name hardcopyiv_atoms
        # lappend lib_name hardcopyiv_hssi_atoms
        # lappend lib_name hardcopyiv_pcie_hip_atoms
        # lappend lib_name maxii_atoms
        # lappend lib_name maxv_atoms
        # lappend lib_name max_atoms
        # lappend lib_name stratixgx_atoms
        # lappend lib_name stratixgx_hssi_atoms
        # lappend lib_name stratixgx_mf
        # lappend lib_name stratixiigx_atoms
        # lappend lib_name stratixiigx_hssi_atoms
        # lappend lib_name stratixiii_atoms
        # lappend lib_name stratixii_atoms
        # lappend lib_name stratixiv_atoms
        # lappend lib_name stratixiv_hssi_atoms
        # lappend lib_name stratixiv_pcie_hip_atoms
        # lappend lib_name stratixv_atoms
        # lappend lib_name stratixv_hssi_atoms
        # lappend lib_name stratixv_pcie_hip_atoms
        # lappend lib_name stratix_atoms
        return $lib_name
    }

    proc altera_vhdl_lib_list {} {
        set lib_name {}
        ##################### vhdl libraries ####################
        # lappend lib_name 220pack
        # lappend lib_name 220model
        # lappend lib_name altera_europa_support_lib
        # lappend lib_name altera_lnsim_components
        # lappend lib_name altera_mf
        # lappend lib_name altera_mf_components
        # lappend lib_name altera_primitives
        # lappend lib_name altera_primitives_components
        # lappend lib_name altera_standard_functions
        # lappend lib_name altera_syn_attributes
        # lappend lib_name alt_dspbuilder_package
        # lappend lib_name arriagx_atoms
        # lappend lib_name arriagx_components
        # lappend lib_name arriagx_hssi_atoms
        # lappend lib_name arriagx_hssi_components
        # lappend lib_name arriaiigz_atoms
        # lappend lib_name arriaiigz_components
        # lappend lib_name arriaiigz_hssi_atoms
        # lappend lib_name arriaiigz_hssi_components
        # lappend lib_name arriaiigz_pcie_hip_atoms
        # lappend lib_name arriaiigz_pcie_hip_components
        # lappend lib_name arriaii_atoms
        # lappend lib_name arriaii_components
        # lappend lib_name arriaii_hssi_atoms
        # lappend lib_name arriaii_hssi_components
        # lappend lib_name arriaii_pcie_hip_atoms
        # lappend lib_name arriaii_pcie_hip_components
        # lappend lib_name arriavgz_atoms
        # lappend lib_name arriavgz_components
        # lappend lib_name arriavgz_hssi_atoms
        # lappend lib_name arriavgz_hssi_components
        # lappend lib_name arriavgz_pcie_hip_atoms
        # lappend lib_name arriavgz_pcie_hip_components
        # lappend lib_name arriav_atoms
        # lappend lib_name arriav_components
        # lappend lib_name arriav_hssi_atoms
        # lappend lib_name arriav_hssi_components
        # lappend lib_name cycloneiiils_atoms
        # lappend lib_name cycloneiiils_components
        # lappend lib_name cycloneiii_atoms
        # lappend lib_name cycloneiii_components
        # lappend lib_name cycloneii_atoms
        # lappend lib_name cycloneii_components
        # lappend lib_name cycloneive_atoms
        # lappend lib_name cycloneive_components
        # lappend lib_name cycloneiv_atoms
        # lappend lib_name cycloneiv_components
        # lappend lib_name cycloneiv_hssi_atoms
        # lappend lib_name cycloneiv_hssi_components
        # lappend lib_name cycloneiv_pcie_hip_atoms
        # lappend lib_name cycloneiv_pcie_hip_components
        # lappend lib_name cyclonev_atoms
        # lappend lib_name cyclonev_components
        # lappend lib_name cyclone_atoms
        # lappend lib_name cyclone_components
        # lappend lib_name hardcopyiii_atoms
        # lappend lib_name hardcopyiii_components
        # lappend lib_name hardcopyii_atoms
        # lappend lib_name hardcopyii_components
        # lappend lib_name hardcopyiv_atoms
        # lappend lib_name hardcopyiv_components
        # lappend lib_name hardcopyiv_hssi_atoms
        # lappend lib_name hardcopyiv_hssi_components
        # lappend lib_name hardcopyiv_pcie_hip_atoms
        # lappend lib_name hardcopyiv_pcie_hip_components
        # lappend lib_name maxii_atoms
        # lappend lib_name maxii_components
        # lappend lib_name maxv_atoms
        # lappend lib_name maxv_components
        # lappend lib_name max_atoms
        # lappend lib_name max_components
        # lappend lib_name sgate
        # lappend lib_name sgate_pack
        # lappend lib_name stratixgx_atoms
        # lappend lib_name stratixgx_components
        # lappend lib_name stratixgx_hssi_atoms
        # lappend lib_name stratixgx_hssi_components
        # lappend lib_name stratixgx_mf
        # lappend lib_name stratixgx_mf_components
        # lappend lib_name stratixiigx_atoms
        # lappend lib_name stratixiigx_components
        # lappend lib_name stratixiigx_hssi_atoms
        # lappend lib_name stratixiigx_hssi_components
        # lappend lib_name stratixiii_atoms
        # lappend lib_name stratixiii_components
        # lappend lib_name stratixii_atoms
        # lappend lib_name stratixii_components
        # lappend lib_name stratixiv_atoms
        # lappend lib_name stratixiv_components
        # lappend lib_name stratixiv_hssi_atoms
        # lappend lib_name stratixiv_hssi_components
        # lappend lib_name stratixiv_pcie_hip_atoms
        # lappend lib_name stratixiv_pcie_hip_components
        # lappend lib_name stratixv_atoms
        # lappend lib_name stratixv_components
        # lappend lib_name stratixv_hssi_atoms
        # lappend lib_name stratixv_hssi_components
        # lappend lib_name stratixv_pcie_hip_atoms
        # lappend lib_name stratixv_pcie_hip_components
        # lappend lib_name stratix_atoms
        # lappend lib_name stratix_components
        return $lib_name
    }
}

proc new_prj {new_prj_name} {
    global prj_path
    set new_prj_path D:/Projects/ProQuestaSim/$new_prj_name/

    quit -sim
    project close
    if { [file exists $new_prj_path]==0 } {
        file mkdir $new_prj_path
    }
    project new $new_prj_path $new_prj_name work
    if { [file exists $new_prj_path/src]==0 } {
        file mkdir $new_prj_path/src
    }
    file copy -force -- $prj_path/sim.do $new_prj_path
    puts "create new project successfully!"
    puts "current project path : "
    pwd
}

proc encrypt_src {} {
    global prj_path
    set encrypt_path $prj_path/encrypt_src/
    file mkdir $encrypt_path
    set paths {}
    set paths [glob -nocomplain -directory $paths */]
    lappend paths $prj_path
    foreach one_path $paths {
        set vfiles [glob -nocomplain -directory $one_path *.v *.vt]
        foreach one_file $vfiles {
            set one_file_path $prj_path
            vencrypt [append one_file_path $one_file] -d $encrypt_path -e v -quiet
        }
    }
    foreach one_path $paths {
        set vhdfiles [glob -nocomplain -directory $one_path *.vhd *.vht]
        foreach one_file $vhdfiles {
            set one_file_path $prj_path
            vhencrypt [append one_file_path $one_file] -d $encrypt_path -e vhd -quiet
        }
    }
    puts "encrypt HDL design file(s) successfully!"
}

proc add_lib {} {
    global altera_lib_path lattice_lib_path device
    vlib verilog_lib
    vmap verilog_lib verilog_lib
    if {$device == "altera"} {
        foreach lib_name [lib_ns::altera_verilog_lib_list] {
            vlog -work verilog_lib $altera_lib_path/$lib_name.v
        }
    } else {
        foreach lib_path [lib_ns::lattice_lib_list] {
            set vfiles [glob -nocomplain -directory $lattice_lib_path/verilog/$lib_path *.v]
            foreach one_file $vfiles {
                vlog -work verilog_lib $one_file
            }
        }
    }
    
    vlib vhdl_lib
    vmap vhdl_lib vhdl_lib
    if {$device == "altera"} {
        foreach lib_name [lib_ns::altera_vhdl_lib_list] {
            vcom -work vhdl_lib $altera_lib_path/$lib_name.vhd
        }
    } else {
        # vcom -work vhdl_lib $lattice_lib_path/vhdl/MACH_Components.vhd
        foreach lib_path [lib_ns::lattice_lib_list] {
            set vhdfiles [glob -nocomplain -directory $lattice_lib_path/vhdl/$lib_path *.vhd]
            foreach one_file $vhdfiles {
                # their something wrong with diamond vhdl library
                # vcom -work vhdl_lib $one_file
            }
        }
    }
    puts -nonewline "add "
    puts -nonewline $device
    puts " libraries successfully!"
}

proc create_file_list {} {
    global prj_path
    set prj_files [project filenames]

    set paths {}
    set paths [glob -nocomplain -directory $paths */]
    lappend paths $prj_path

    set fd [open $prj_path/hdl_design_file_list.tcl w+]
    foreach one_path $paths {
        set vfiles [glob -nocomplain -directory $one_path *.v *.vt *.vhd *.vht]
        foreach one_file $vfiles {
            set exists_num 0
            set one_file_path {}
            append one_file_path $prj_path
            append one_file_path $one_file
            foreach one_prj_file $prj_files {
                if {$one_file_path == $one_prj_file} {
                    incr exists_num
                }
            }
            if {$exists_num == 0} {
                puts -nonewline $fd "# "
            }
            puts $fd $one_file_path
        }
    }
    close $fd
    puts "create file list successfully!"
}

proc add_file {} {
    global prj_path auto_add_file
    set add_count 0
    set del_count 0
    set prj_files [project filenames]

    if {$auto_add_file == 1} {
        set paths [glob -nocomplain -directory $prj_path */]
        lappend paths $prj_path
        foreach one_path $paths {
            set vfiles [glob -nocomplain -directory $one_path *.v *.vt *.vhd *.vht]
            foreach one_file $vfiles {
                set exists_num 0
                foreach one_prj_file $prj_files {
                    if {$one_file == $one_prj_file} {
                        incr exists_num
                    }
                }
                if {$exists_num == 0} {
                    project addfile $one_file
                    incr add_count
                }
            }
        }
    } elseif {$auto_add_file == 0} {
        if {[file exists $prj_path/hdl_design_file_list.tcl] == 0 || \
            [file size $prj_path/hdl_design_file_list.tcl] <= 1} {
                create_file_list
        }
        set fd [open $prj_path/hdl_design_file_list.tcl r]
        set old_content [read -nonewline $fd]
        close $fd
        regsub -all " " $old_content {} new_content
        regsub -all \t+ $new_content {} new_content
        foreach one_file [split $new_content \n] {
            if {[regexp ^# $one_file] == 0 && $one_file != "\n"} {
                set exists_num 0
                foreach one_prj_file $prj_files {
                    if {$one_file == $one_prj_file} {
                        incr exists_num
                    }
                }
                if {$exists_num == 0} {
                    project addfile $one_file
                    incr add_count
                }
            } elseif {[regexp ^# $one_file] == 1 && $one_file != "\n"} {
                set one_file [string trim $one_file "#"]
                foreach one_prj_file $prj_files {
                    if { $one_file == $one_prj_file} {
                        project removefile $one_file
                        incr del_count
                    }
                }
            }
        }
    }
    puts -nonewline "add "
    puts -nonewline $add_count
    puts " file(s) successfully!"
    puts -nonewline "remove "
    puts -nonewline $del_count
    puts " file(s) successfully!"
}

proc compile_changed {} {
    project compileoutofdate
    puts "compile changed file(s) successfully!"
}

# radix types : binary, ascii, unsigned, decimal, octal, hex, symbolic, time, and default
proc wave_style_set {} {
    global testbench_name default_color
    foreach sig [find signals $testbench_name/*] {
        switch -regexp -nocase -- $sig {
            /*/*rst+     {add wave -radix binary     -color [lindex $default_color 0] $sig}
            /*/*clk+     {add wave -radix binary     -color [lindex $default_color 1] $sig}
            /*/*en+      {add wave -radix binary     -color [lindex $default_color 2] $sig}
            /*/*cnt+     {add wave -radix decimal    -color [lindex $default_color 3] $sig}
            /*/*data+    {add wave -radix hex        -color [lindex $default_color 4] $sig}
            /*/*flag+    {add wave -radix binary     -color [lindex $default_color 5] $sig}
            default      {add wave -radix hex        -color [lindex $default_color 6] $sig}
        }
    }
}

proc run_all {} {
    global testbench_name sim_time m_height m_width prj_path
    compile_changed
    quit -sim
    vsim -novopt -L verilog_lib -L vhdl_lib -l sim_log.log \
         +transport_int_delays +transport_path_delays work.$testbench_name
    if {[file exists $prj_path/wave.do] == 1} {
        do $prj_path/wave.do
    } else {
        wave_style_set
    }
    run $sim_time
    view -undock wave -x 0 -y 0 -width $m_width -height $m_height
    wave zoom full
}

proc backup_prj {msg} {
    global testbench_name bkp_path prj_path  
    set time [clock seconds]
    set bkp_name $testbench_name
    append bkp_name [clock format $time -format "_%Y-%m-%d-%H-%M-%S"]
    if { [file isdirectory $bkp_path] == 0 } {
        file mkdir $bkp_path
    }
    file mkdir $bkp_path/$bkp_name
    file copy -force $prj_path $bkp_path/$bkp_name
    append bkp_name "_README.txt"
    set fd [open $bkp_path/$bkp_name w+]
    puts $fd $msg
    close $fd
    puts "backup current project successfully!"
}

proc save_wave {} {
    global sim_time
    set time [clock seconds]
    set filename "sim_wave_"
    append filename [clock format $time -format "%Y-%m-%d-%H-%M-%S"]
    vcd add -dumpports -r -optcells -file $filename.vcd -internal -ports *
    run $sim_time
    vcd flush $filename.vcd
    vcd off $filename.vcd
}

proc load_wave {vcd_file} {
    append vcd_file ".vcd"
    wave import $vcd_file
}

proc write_report {} {
    global prj_path
    set report_path [append prj_path report]
    if {[file exists $report_path] == 0} {
        file mkdir $report_path
    }
    set txt_file "report.txt"
    write report -l $report_path/$txt_file

    set filename "instances"
    set fd [open $report_path/$filename.txt w+]
    puts $fd "instances :"
    puts $fd "\tshow -all"
    set linstances [find instances -r -nodu /*]
    foreach instance $linstances {
        puts -nonewline $fd \t
        puts -nonewline $fd "show "
        puts $fd $instance
    }
    close $fd
    puts "write report successfully!"
}

proc display_info {} {
    global testbench_name sim_time prj_path m_width m_height default_color device
    puts "========= infomation of current project ========="

    puts -nonewline "monitor resolution ratio : "
    puts -nonewline $m_width
    puts -nonewline "x"
    puts $m_height

    puts "\npreset signals color style"
    puts -nonewline "rst     signals color : "
    puts [lindex $default_color 0]
    puts -nonewline "clk     signals color : "
    puts [lindex $default_color 1]
    puts -nonewline "en      signals color : "
    puts [lindex $default_color 2]
    puts -nonewline "cnt     signals color : "
    puts [lindex $default_color 3]
    puts -nonewline "data    signals color : "
    puts [lindex $default_color 4]
    puts -nonewline "flag    signals color : "
    puts [lindex $default_color 5]
    puts -nonewline "default signals color : "
    puts [lindex $default_color 6]

    puts "\nHDL design files of project path : "
    set paths [glob -nocomplain -directory $prj_path */]
    lappend paths $prj_path
    foreach one_path $paths {
        set vfiles [glob -nocomplain -directory $one_path *.v *.vt *.vhd *.vht]
        foreach one_file $vfiles {
            puts $one_file
        }
    }

    puts -nonewline "\nloaded "
    puts -nonewline $device
    puts " simulation library list : "
    if {$device == "altera"} {
        foreach lib_name [lib_ns::altera_verilog_lib_list] {
            puts $lib_name.v
        }
        foreach lib_name [lib_ns::altera_vhdl_lib_list] {
            puts $lib_name.v
        }
    } else {
        foreach lib_name [lib_ns::lattice_lib_list] {
            puts $lib_name
        }
    }
    
    puts -nonewline "\ntestbench name : "
    puts $testbench_name

    puts -nonewline "\nsimulation time : "
    puts $sim_time
    puts "============= end of infomation ============="
}

proc do_help {} {
    echo "============ display help infomation ============"
    echo "alias ne = new_prj          : new a project"
    echo "alias es = encrypt_src      : encrypt all HDL design file(s)"
    echo "alias ab = add_lib          : add altera simulation library"
    echo "alias af = add_file         : add source files"
    echo "alias bc = backup_prj       : backup current project"
    echo "alias cf = create_file_list : create hdl design file list"
    echo "alias cc = compile_changed  : compile changed files including *.v , *.vt , *.vhd , *.vht"
    echo "alias cr = .main clear      : clear the tcl console"
    echo "alias ra = run_all          : compile_changed and simulate"
    echo "alias rr = run              : run"
    echo "alias sw = save_wave        : save simulation wave in a VCD file"
    echo "alias aw = load_wave        : load simulation wave from a VCD file"
    echo "alias wr = write_report     : write a report to a .txt file"
    echo "alias df = display_info     : echo information of current project"
    echo "alias dh = do_help          : echo help information of this do file"
    echo "============= end of help infomation ============="
}

################# TCL commands alias ##################
alias ne "new_prj"
alias es "encrypt_src"
alias ab "add_lib"
alias af "add_file"
alias br "backup_prj"
alias cf "create_file_list"
alias cc "compile_changed"
alias cr ".main clear"
alias rr "run"
alias ra "run_all"
alias sw "save_wave"
alias aw "load_wave"
alias wr "write_report"
alias df "display_info"
alias dh "do_help"
#######################################################