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SMT32通过SPI读写FPGA的寄存器_spi读写寄存器流程

作者：我家小花儿 | 2024-04-29 21:09:53

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spi读写寄存器流程

关于SPI的主机和从机请看;https://blog.csdn.net/qq_40893012/article/details/103995154

本设计在FPGA用32个寄存器构建了一个8bit*32的ROM，可通过STM32使用SPI写入命令字节来实现对32个寄存器的读写操作。

命令字节的格式：

bit 7:读写控制位，

      1：W

      0：R

bit6-bit2:寄存器地址

bit1-bit0：未使用

stm32的代码基于正电原子的探索者开发板和工程，使用软件模拟SPI，FPGA使用Verilog编写。

SPI的特性为：时钟空闲时为高电平，在时钟的下降沿将数据输出，在时钟的上升沿读取数据。

主要代码：

FPGA代码：

1 SPI从机部分

  1. // 32位二段式状态机spi模块
  2. module spi_slave16bit(
  3. 	input wire clk,
  4. 	input rst_n,
  5. 	input wire CS,
  6. 	input wire SCK,
  7. 	input wire MOSI,
  8. 	output reg MISO,
  9. 	output reg [5:0]rom_addr,
  10. 	output reg busy,//spi给fpga其他模块，busy=1时，禁止FPGA读写
  11. 	input wire[15:0] data_to_out,
  12. 	output reg[15:0] data_had_receive,
  13.   output rxd_over //rx 2byte will generate pulse 
  14.   );
  15.  
  16. reg [1:0] state;
  17. parameter IDLE = 2'b00;
  18. parameter TRANS = 2'b01;
  19. parameter WAIT = 2'b10;
  21. reg [1:0]CS_buf;
  22. wire CS_falling_flag;
  23. wire CS_rising_flag;
  24. always@(posedge clk)
  25. begin
  26. 	CS_buf[1] <= CS_buf[0];
  27. 	CS_buf[0] <= CS;
  28. end
  29. assign CS_falling_flag = CS_buf[1] &(~CS_buf[0]);
  30. assign CS_rising_flag = (~CS_buf[1]) & CS_buf[0];
  32. reg [1:0]SCK_buf;
  33. wire SCK_falling_flag;
  34. wire SCK_rising_flag;
  35. always@(posedge clk)
  36. begin  
  37.      SCK_buf[1] <= SCK_buf[0];
  38. 	  SCK_buf[0] <= SCK;
  39. end
  41. assign SCK_falling_flag = SCK_buf[1]&(~SCK_buf[0]);
  42. assign SCK_rising_flag = (~SCK_buf[1])&SCK_buf[0];
  44. reg [5:0]count;
  45. // state machine
  46. always@(posedge clk)
  47. begin
  48.   
  49. 	case(state)
  50. 		IDLE:begin
  51. 				 if(CS_falling_flag==1) state <= TRANS;
  52. 			  end
  53. 		TRANS:begin
  54. 					if(count == 6'b010000) state <= WAIT; // 传完16个数
  55. 					else if (CS_rising_flag==1) state <= IDLE; // 意外结束
  56. 				end
  57. 		WAIT:begin
  58. 				 if (CS_rising_flag) state <= IDLE;
  59. 			  end
  60. 	endcase
  61. end
  62.  
  63. // count
  64. always@(posedge clk)
  65. begin
  66. 	case(state)
  67. 		IDLE: count<=6'b0;
  68. 		TRANS:begin
  69. 					if(SCK_rising_flag == 1) count <= count + 6'b1;
  70. 				end
  71. 	endcase
  72. end
  73.  
  74. // MISO
  75. always@(posedge clk)
  76. begin
  77. 	if ((state == TRANS)&&(SCK_falling_flag == 1))
  78. 	begin
  79. 		case(count)
  80. 			6'b000000: MISO <= data_to_out[15];
  81. 			6'b000001: MISO <= data_to_out[14];
  82. 			6'b000010: MISO <= data_to_out[13];
  83. 			6'b000011: MISO <= data_to_out[12];
  84. 			6'b000100: MISO <= data_to_out[11];
  85. 			6'b000101: MISO <= data_to_out[10];
  86. 			6'b000110: MISO <= data_to_out[9];
  87. 			6'b000111: MISO <= data_to_out[8];
  88. 			6'b001000: MISO <= data_to_out[7];
  89. 			6'b001001: MISO <= data_to_out[6];
  90. 			6'b001010: MISO <= data_to_out[5];
  91. 			6'b001011: MISO <= data_to_out[4];
  92. 			6'b001100: MISO <= data_to_out[3];
  93. 			6'b001101: MISO <= data_to_out[2];
  94. 			6'b001110: MISO <= data_to_out[1];
  95. 			6'b001111: MISO <= data_to_out[0];
  96. /* 			6'b010000: MISO <= data_to_out[15];
  97. 			6'b010001: MISO <= data_to_out[14];
  98. 			6'b010010: MISO <= data_to_out[13];
  99. 			6'b010011: MISO <= data_to_out[12];
  100. 			6'b010100: MISO <= data_to_out[11];
  101. 			6'b010101: MISO <= data_to_out[10];
  102. 			6'b010110: MISO <= data_to_out[9];
  103. 			6'b010111: MISO <= data_to_out[8];
  104. 			6'b011000: MISO <= data_to_out[7];
  105. 			6'b011001: MISO <= data_to_out[6];
  106. 			6'b011010: MISO <= data_to_out[5];
  107. 			6'b011011: MISO <= data_to_out[4];
  108. 			6'b011100: MISO <= data_to_out[3];
  109. 			6'b011101: MISO <= data_to_out[2];
  110. 			6'b011110: MISO <= data_to_out[1];
  111. 			6'b011111: MISO <= data_to_out[0]; */
  112. 		endcase
  113. 	end
  114. end
  115.  
  116. // MOSI
  117. reg rxd_flag_r;
  118. always@(posedge clk or negedge rst_n)
  119. begin
  120.  if(!rst_n)
  121.    rxd_flag_r <= 0;
  122.   else 
  123.  begin
  124. 	if ((state == TRANS)&&(SCK_rising_flag == 1))
  125. 	begin
  126. 		case(count)
  127. 			6'b000000: begin data_had_receive[15] <= MOSI;rxd_flag_r<=1'b0;end
  128. 			6'b000001: data_had_receive[14] <= MOSI;
  129. 			6'b000010: data_had_receive[13] <= MOSI;
  130. 			6'b000011: data_had_receive[12] <= MOSI;
  131. 			6'b000100: data_had_receive[11] <= MOSI;
  132. 			6'b000101: begin
  133.                   data_had_receive[10] <= MOSI; //set rom addr 
  134.                   rom_addr[5:0] <= {data_had_receive[15:11],MOSI};
  135.                  end
  136. 			6'b000110: data_had_receive[9] <= MOSI;
  137. 			6'b000111: data_had_receive[8] <= MOSI;
  138. 			6'b001000: data_had_receive[7] <= MOSI;
  139. 			6'b001001: data_had_receive[6] <= MOSI;
  140. 			6'b001010: data_had_receive[5] <= MOSI;
  141. 			6'b001011: data_had_receive[4] <= MOSI;
  142. 			6'b001100: data_had_receive[3] <= MOSI;
  143. 			6'b001101: data_had_receive[2] <= MOSI;
  144. 			6'b001110: data_had_receive[1] <= MOSI;
  145. 			6'b001111: begin data_had_receive[0] <= MOSI; rxd_flag_r<=1'b1;end
  146. /* 			6'b010000: data_had_receive[15] <= MOSI;
  147. 			6'b010001: data_had_receive[14] <= MOSI;
  148. 			6'b010010: data_had_receive[13] <= MOSI;
  149. 			6'b010011: data_had_receive[12] <= MOSI;
  150. 			6'b010100: data_had_receive[11] <= MOSI;
  151. 			6'b010101: data_had_receive[10] <= MOSI;
  152. 			6'b010110: data_had_receive[9] <= MOSI;
  153. 			6'b010111: data_had_receive[8] <= MOSI;
  154. 			6'b011000: data_had_receive[7] <= MOSI;
  155. 			6'b011001: data_had_receive[6] <= MOSI;
  156. 			6'b011010: data_had_receive[5] <= MOSI;
  157. 			6'b011011: data_had_receive[4] <= MOSI;
  158. 			6'b011100: data_had_receive[3] <= MOSI;
  159. 			6'b011101: data_had_receive[2] <= MOSI;
  160. 			6'b011110: data_had_receive[1] <= MOSI;
  161. 			6'b011111: data_had_receive[0] <= MOSI; */
  162. 		endcase
  163. 	end
  164.  end
  165. end
  166.  
  167. reg rxd_flag_r0,rxd_flag_r1;
  168. always@(negedge rst_n or posedge clk)
  169. begin
  170.     if(!rst_n)
  171.         begin
  172.             rxd_flag_r0 <= 1'b0;
  173.             rxd_flag_r1 <= 1'b0;
  174.         end
  175.     else
  176.         begin
  177.             rxd_flag_r0 <= rxd_flag_r;
  178.             rxd_flag_r1 <= rxd_flag_r0;
  179.         end
  180. end
  181. assign rxd_over = (~rxd_flag_r1 & rxd_flag_r0)? 1'b1:1'b0; 
  182. // busy
  183. always@(posedge clk)
  184. begin
  185. 	case(state)
  186. 		IDLE: busy <= 0;
  187. 		TRANS: busy <= 1;
  188. 		WAIT: busy <= 0;
  189. 	endcase
  190. end
  191.  
  192. endmodule

2 寄存器构成ROM模块

  1. module spi_rom 
  2.               (
  3.                rst,
  4.                rxd_flag,
  5.                reg_addr,
  6.                reg_out,
  7.                rxd_in_spi
  8.               );
  9.  
  10. input rst,rxd_flag;
  11. input [5:0] reg_addr;
  12. input [15:0] rxd_in_spi;
  13. output reg [7:0] reg_out;              
  14. reg [7:0] REG_ROM[31:0];
  15.  
  16. always@(negedge rst or posedge rxd_flag)
  17. begin
  18.   if(!rst)
  19.   begin
  20.     REG_ROM[0] <= 8'd0;
  21.     REG_ROM[1] <= 8'd1;
  22.     REG_ROM[2] <= 8'd2;
  23.     REG_ROM[3] <= 8'd3;
  24.     REG_ROM[4] <= 8'd4;
  25.     REG_ROM[5] <= 8'd5;
  26.     REG_ROM[6] <= 8'd6;
  27.     REG_ROM[7] <= 8'd7;
  28.     REG_ROM[8] <= 8'd8;
  29.     REG_ROM[9] <= 8'd9;
  30.     REG_ROM[10] <= 8'd10;
  31.     REG_ROM[11] <= 8'd11;    
  32.     REG_ROM[12] <= 8'd12;
  33.     REG_ROM[13] <= 8'd13;
  34.     REG_ROM[14] <= 8'd14;
  35.     REG_ROM[15] <= 8'd15;
  36.     REG_ROM[16] <= 8'd16;
  37.     REG_ROM[17] <= 8'd17;
  38.     REG_ROM[18] <= 8'd18;
  39.     REG_ROM[19] <= 8'd19;
  40.     REG_ROM[20] <= 8'd20;
  41.     REG_ROM[21] <= 8'd21;
  42.     REG_ROM[22] <= 8'd22;  
  43.     REG_ROM[23] <= 8'd23;
  44.     REG_ROM[24] <= 8'd24;    
  45.     REG_ROM[25] <= 8'd25;
  46.     REG_ROM[26] <= 8'd26;
  47.     REG_ROM[27] <= 8'd27;
  48.     REG_ROM[28] <= 8'd28;
  49.     REG_ROM[29] <= 8'd29;
  50.     REG_ROM[30] <= 8'd30;
  51.     REG_ROM[31] <= 8'd31;   
  52.   end
  53.   else
  54.    begin
  55.       if(rxd_in_spi[15]==1'b1)
  56.        REG_ROM[rxd_in_spi[14:10]] = rxd_in_spi[7:0];
  57.    end
  58. end
  59. always@(reg_addr) 
  60. begin
  61.    if(reg_addr[5]==0)
  62.     reg_out=REG_ROM[reg_addr[4:0]];
  63.    else reg_out=8'd0; //if write and next byte will tx 8'b0
  64.    
  65. end
  67. /* always@(posedge rxd_flag)
  68. begin
  69.   if(rxd_in_spi[15]==1'b1)
  70.    REG_ROM[rxd_in_spi[14:10]] = rxd_in_spi[7:0];
  71. end          */   
  72. endmodule

3 顶层模块

  1. module TEST_MODULE
  2.                 (
  3.                 clk,
  4.                 rst,
  5.                 cs,
  6.                 sck,
  7.                 MOSI,
  8.                 MISO,
  9.                 led_pin,
  10.                 rxd_over
  11.                  );
  12.                  
  13. input clk,rst,cs,sck,MOSI;
  14. output MISO,led_pin,rxd_over;
  15. wire rxd_flag;
  16. wire [5:0] rom_addr;  
  17. wire [7:0] reg_out;  
  18. wire [15:0]rxd_in_spi; 
  19. wire spi_busy;
  20. wire rxd_over;
  21. wire [7:0] dat_to_out;
  22.  
  23. //always@(posedge clk)
  24. //begin
  25. // if(!spi_busy)
  26.  //  dat_to_out[15:8] <= 8'd255;
  27. //end
  29. LED_module LED_module_inst
  30.           (
  31.           .clk(clk),
  32.           .rst(rst),
  33.           .led_pin(led_pin)
  34.           );  
  36. spi_slave16bit(
  37. 	 .clk(clk),
  38. 	 .rst_n(rst),
  39. 	 .CS(cs),
  40. 	 .SCK(sck),
  41. 	 .MOSI(MOSI),
  42. 	 .MISO(MISO),
  43. 	 .rom_addr(rom_addr),
  44. 	 .busy(spi_busy),//spi给fpga其他模块，busy=1时，禁止FPGA读写
  45. 	 .data_to_out({8'hff,dat_to_out}),//first byte TX 0hff
  46. 	 .data_had_receive(rxd_in_spi),
  47.    .rxd_over(rxd_over)
  48.   );
  49.           
  50. spi_rom spi_rom_inst
  51.               (
  52.                .rst(rst),
  53.                .rxd_flag(rxd_over),
  54.                .reg_addr(rom_addr),
  55.                .reg_out(dat_to_out),
  56.                .rxd_in_spi(rxd_in_spi)
  57.               );
  58.   
  59. endmodule

SMT32部分

1 头文件及部分定义 

  1. #define SPI_CS  PGout(7) 		 
  2. #define SPI_MISO  PBin(4) 	
  3. #define SPI_MOSI  PBout(5) 	
  4. #define SPI_CLK  PBout(3) 
  5.  
  6. void soft_spi_ioinit(void);
  7. u8 get_cmd(u8 wr,u8 addr);
  8. u8 spi_read2byte(u8 reg_addr);
  9. u8 spi_write2byte(u8 reg_addr,u8 dat);

2 函数声明部分

  1. void soft_spi_ioinit()
  2. {
  3.  
  4. 	GPIO_InitTypeDef  GPIO_InitStructure;
  5. 	RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOG, ENABLE);//ʹÄÜGPIOB,GʱÖÓ
  6.   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;              //CS
  7.   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;//ÆÕͨÊä³öģʽ
  8.   GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;//ÍÆÍìÊä³ö
  9.   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz;//100MHz
  10.   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;//ÉÏÀ­
  11.   GPIO_Init(GPIOG, &GPIO_InitStructure);//³õʼ»¯PG6,7
  12. 	SPI_CS=1;			//SPIƬѡȡÏû	
  13. 	
  14. 	
  15.   RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);//ʹÄÜGPIOAʱÖÓ
  16.  
  17.  
  18.   //GPIOFB3,5³õʼ»¯ÉèÖÃ
  19.   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3|GPIO_Pin_5;//PB3~5¸´Óù¦ÄÜÊä³ö	
  20.   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;//¸´Óù¦ÄÜ
  21.   GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;//ÍÆÍìÊä³ö
  22.   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz;//100MHz
  23.   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;//ÉÏÀ­
  24.   GPIO_Init(GPIOB, &GPIO_InitStructure);//³õʼ»¯
  25. 	SPI_CLK = 1;
  26. 	
  27.   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;//PB3~5¸´Óù¦ÄÜÊä³ö	
  28.   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;//ÆÕͨÊäÈëģʽ
  29.   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz;//100M
  30.   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;//ÉÏÀ­
  31.   GPIO_Init(GPIOB, &GPIO_InitStructure);//³õʼ»¯
  32. 		
  33. }
  34.  
  35. u8 get_cmd(u8 wr,u8 addr)//wr=1:w  wr=0:r addr:0-31
  36.  {
  37.    u8 reg=0;
  38. 	 //if(wr) reg = 128;
  39. 	 reg = wr;
  40. 	 reg = reg<<5;
  41. 	 reg =  reg+addr;
  42. 	 reg =reg<<2;
  43. 	 return reg;
  44.  };
  45.  
  46.  u8 spi_read2byte(u8 reg_addr) //reg_addr:0-31
  47. {
  48.   u32 tmp=0;
  49. 	u8 i=0;
  50. 	u8 addr; 
  51. 	SPI_CS = 1;
  52. 	SPI_CLK = 1;
  53. 	SPI_CS = 0;
  54. 	
  55. 	addr = get_cmd(0,reg_addr);
  56. 	
  57. 	delay_us(1);
  58.   for(i=0;i<8;i++)
  59. 	{
  60. 	 SPI_CLK = 1;
  61. 		if(addr&0x80)SPI_MOSI = 1;
  62. 	   else SPI_MOSI = 0;
  63. 		addr = addr<<1;
  64. 	 delay_us(1);
  65. 	 SPI_CLK = 0;
  66. 	 delay_us(1);
  67. 	 SPI_CLK = 1;
  68. 	 tmp =tmp<<1;
  69. 	 tmp = tmp+SPI_MISO;
  70. 	}
  71. 	delay_us(2);
  72. 	  for(i=0;i<8;i++)
  73. 	{
  74. 	 SPI_CLK = 1;
  75.     SPI_MOSI = 1;
  76. 	 delay_us(1);
  77. 	 SPI_CLK = 0;
  78. 	 delay_us(1);
  79. 	 SPI_CLK = 1;
  80. 	 tmp =tmp<<1;
  81. 	 tmp = tmp+SPI_MISO;
  82. 	}
  83. 	SPI_CLK = 1;
  84. 	SPI_CS = 1;
  85. 	
  86. 	return tmp&0x00ff;
  87. 	
  88. }
  89.  
  90. u8 spi_write2byte(u8 reg_addr,u8 dat)
  91. {
  92.   u32 tmp=0;
  93. 	int i=0;
  94. 	u8 addr;
  95. 	u8 dat_buff = dat;
  96. 	SPI_CS = 1;
  97. 	SPI_CLK = 1;
  98. 	SPI_CS = 0;
  99. 	delay_us(1);
  100. 	
  101. 	addr = get_cmd(1,reg_addr);
  102. 	
  103.   for(i=0;i<8;i++)
  104. 	{
  105. 	 SPI_CLK = 1;
  106. 		if(addr&0x80)SPI_MOSI = 1;
  107. 	   else SPI_MOSI = 0;
  108. 		addr = addr<<1;
  109. 	 delay_us(1);
  110. 	 SPI_CLK = 0;
  111. 	 delay_us(1);
  112. 	 SPI_CLK = 1;
  113. 	 tmp =tmp<<1;
  114. 	 tmp = tmp+SPI_MISO;
  115. 	}
  116. 	
  117. 	delay_us(2);
  118. 	
  119. 	for(i=0;i<8;i++)
  120. 	{
  121. 	 SPI_CLK = 1;
  122. 		 if(dat_buff&0x80)SPI_MOSI = 1;
  123.        else SPI_MOSI = 0;
  124. 		dat_buff = dat_buff<<1;
  125. 	 delay_us(1);
  126. 	 SPI_CLK = 0;
  127. 	 delay_us(1);
  128. 	 SPI_CLK = 1;
  129. 	 tmp =tmp<<1;
  130. 	 tmp = tmp+SPI_MISO;
  131. 	}
  132. 	SPI_CLK = 1;
  133. 	SPI_CS = 1;
  134. 	
  135. 	return tmp&0x00ff;
  136. }

3 主函数

  1. int main(void)
  2. { 
  3. 	u8 key,mode;
  4. 	u8 t=0;
  5. 	u32 error_num=0;
  6. 	u32 read_num=0;
  7.   u32 rec=0;	
  8. 	u8 tmp_buf[33];	
  9. 	NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//ÉèÖÃϵͳÖжÏÓÅÏȼ¶·Ö×é2
  10. 	delay_init(168);  //³õʼ»¯ÑÓʱº¯Êý
  11. 	uart_init(115200);	//³õʼ»¯´®¿Ú²¨ÌØÂÊΪ115200
  12. 	LED_Init();					//³õʼ»¯LED 
  13. // 	LCD_Init();					//LCD³õʼ»¯  
  14. // 	KEY_Init();					//°´¼ü³õʼ»¯
  15. // 	NRF24L01_Init();    		//³õʼ»¯NRF24L01 
  16.    soft_spi_ioinit();
  17.   //NRF24L01_Read_Reg(reg);
  18.  	while(1)
  19. 	{	
  20. 		
  21.     for(t=0;t<32;t++)
  22. 		{
  23. 		//key = get_reg(0,t);
  24. 		key = rand()%100;
  25. 		spi_write2byte(t,key);
  26. 			
  27. 		rec = spi_read2byte(t);
  28.    		
  29. 		if(rec!=key)
  30. 		{
  31. 		 error_num++;
  32. 		 printf("error_num = %d\r\n",error_num);
  33. 		}
  34. 		   read_num++;
  35. 		  if(read_num%100==0) 
  36. 			{
  37. 			 
  38.        printf("error_num = %d\r\n",error_num);				
  39. 			}
  40. 			printf("send = %d   rec_num = %d   read_num = %d\r\n",key,rec,read_num);
  41. 		  rec = 0;
  42. 		//if(key==5)
  43. 			//else  printf("key = %d ERROR\r\n",key);	
  44. 		delay_ms(100);	
  45. 		}
  46. 	 
  47.    
  48. 		t++;		
  49.  
  50. 	
  51. 	}     
  52. 		
  53. }

运行结果

读写上万次无错误

 

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