Verilog编程实现流水灯（基于FPGA的数电课设）_fpga数电课设csdn

编程实现流水灯（verilog）

**

通过编程轮流点亮8个LED灯

**

1. 单流水灯（每次点亮一个LED灯）

module run_led
(
	CLK,RSTn,LED_Out
);

	input CLK;
	input RSTn;
	output [7:0]LED_Out;
	

	led8_module U1
	(
	.CLK(CLK) ,	// input  CLK
	.RSTn(RSTn) ,	// input  RSTn 
	.LED_Out(LED_Out) 	// output [7:0] LED_Out--to top
	);
	
endmodule 
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module led8_module
(
    CLK, RSTn, LED_Out
);

    input CLK;
    input RSTn;
    output [7:0]LED_Out;
        
    parameter T10000MS = 23'd50_000_000;      
    reg [22:0]Count;		//Delay
    reg [7:0]rLED_Out;
	 
    always @ ( posedge CLK or negedge RSTn )
	    if( !RSTn )
			begin
				Count <= 23'd0;
				rLED_Out <= 8'b0000_0001;
			end
	    else if( Count == T10000MS - 1'b1)
			 begin
				Count <= 23'd0;				  
				if( rLED_Out == 8'b0000_0000 )
					rLED_Out <= 8'b0000_0001;
				else
					rLED_Out <= {rLED_Out[0],rLED_Out[7:1]};
			 end
	    else
	        Count <= Count + 1'b1;
	        
	assign LED_Out = rLED_Out;
        
endmodule
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2.双流水灯（每次点亮两个LED灯）

module run_led
(
	CLK,RSTn,LED_Out
);

	input CLK;
	input RSTn;
	output [7:0]LED_Out;
	

	led8_module U1
	(
	.CLK(CLK) ,	// input  CLK
	.RSTn(RSTn) ,	// input  RSTn 
	.LED_Out(LED_Out) 	// output [7:0] LED_Out--to top
	);
	
endmodule 
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module led8_module
(
    CLK, RSTn, LED_Out
);

    input CLK;
    input RSTn;
    output [7:0]LED_Out;
        
    parameter T10000MS = 23'd50_000_000;      
    reg [22:0]Count;		//Delay
    reg [7:0]rLED_Out;
	 
    always @ ( posedge CLK or negedge RSTn )
	    if( !RSTn )
			begin
				Count <= 23'd0;
				rLED_Out <= 8'b0000_0011;
			end
	    else if( Count == T10000MS - 1'b1)
			 begin
				Count <= 23'd0;				  
				if( rLED_Out == 8'b0000_0000 )
					rLED_Out <= 8'b0000_0011;
				else
					rLED_Out <= {rLED_Out[0],rLED_Out[1],rLED_Out[7:2]};
			 end
	    else
	        Count <= Count + 1'b1;
	        
	assign LED_Out = rLED_Out;
        
endmodule
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