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基于FPGA的电子时钟设计与实现 （在EDA开发板上实现电子时钟功能）

作者：我家小花儿 | 2024-07-18 21:29:33

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基于fpga的电子时钟设计

开发板：此款开发板使用的是 ALTERA 公司的 Cyclone IV 系列 FPGA，型号为 EP4CE6F17C8， 256 个引脚的 FBGA 封装。

 题目：在EDA开发板上实现电子时钟功能

要求：实现电子时钟程序编写，实现在7段数码管显示时、分、秒，使用4x4矩阵按键模拟调节时钟指令输入按键，并实现整点报时功能。按键功能包括但不限以下功能：选择（时分秒选择按键、可以一一对应，也可以只用1个按键）、复位、+（时分秒加）、-（时分秒减）。

程序设计步骤：

1、七段数码管显示

1

2.

4

6.

5

7

图1  开机显示画面，其中.为时分秒的间隔

2、 数据输入：在图1所示的状态下，用4x4矩阵按键来进行时分秒的调节。

3、整点报时：到整点时，自动播放一段音乐。

 4、一键复原：完成时间调节后，按“复原”按键，七段数码管显示最初的状态，回到图1所示状态。

以上既是该电子时钟的设计要求。

功能设计部分，分为以下7个模块。

各功能模块简介
EDA_clock顶层模块文件将各个模块进行整合
clk1hz时钟频率将50MHz晶振频率转化为1秒钟的频率，1Hz=1s
cnt2424计数器时钟中 “时”的计数，并判断
cnt6060计数器时钟中“分”、“秒”的计数，并判断个位十位实时状态
key4x4_clock4x4矩阵键盘矩阵键盘功能设置
seg_dynamic七段数码管接收当前计数器值
buzzer蜂鸣器控制当整点时播放音乐3秒钟

对于以下各个代码块有较为详细的标注，请自行对照理解，有疑惑的可以评论区，看到回复

1. EDA_clock.v

创建工程后，该模块为顶层文件

代码如下：

  1. /**
  2.  * @copyright: 2782978674@qq.com
  3.  * @author: xietiancheng
  4.  * @date: 2023.6.4
  5.  * 
  6.  **/
  7.  
  8. ​module EDA_clock(
  9.     input	wire	sys_clk,
  10.     input	wire	rst_n,
  11. 	input 	wire 	[3:0]	key_in_y,	// 输入矩阵键盘的列信号(KEY0~KEY3)
  12. 	output 	wire	[3:0]	key_out_x,	// 输出矩阵键盘的行信号(KEY4~KEY7)
  13. 	output	wire	[5:0] sel 	, //数码管位选信号
  14. 	output	wire	[7:0] seg	, //数码管段选信号	
  15. 	output	wire		buzzer
  16. );
  17.  
  18. wire clk_1hz;
  19. wire count_s;
  20. wire count_m;
  21. wire [6:0]  Sec;		//秒
  22. wire [6:0]  Sec_out;		//秒输出
  23. wire [6:0]  Min;		//分
  24. wire [6:0]  Min_out;		//分输出
  25. wire [6:0]  Hour; 		//时
  26. wire [6:0]  Hour_out; 		//时输出
  27. wire [4:0]  Sec1;  		//秒的个位
  28. wire [4:0]  Sec2;		//秒的十位
  29. wire [4:0]  Min1;		//分的个位
  30. wire [4:0]  Min2;       //分的十位
  31. wire [4:0]  Hour1;		//时的个位
  32. wire [4:0]  Hour2;      //时的十位
  33.  
  34. wire en_s;	//秒的使能信号
  35. wire en_m;	//分的使能信号
  36. wire en_h;	//时的使能信号
  37. wire time_en;//当设置时间时，设置使能信号，当有效时时间停止，进行时钟各位赋值。
  38.  
  39. // assign en_s=1'b1;
  40. assign en_m=count_s && en_s;
  41. assign en_h= (Min_out == 7'd59 && Sec_out == 7'd58)?1:0;
  43. //1hz代表一秒钟，时钟频率设置
  44. clk1hz 
  45. #(
  46. 	.N	(26'd25_000_000	)	//代表
  47. )
  48. clk1hz_inst
  49. (
  50.     .clk(sys_clk),
  51.     .rst_n(rst_n),
  52.     .clk_out(clk_1hz)
  53. );
  54. /*********秒和分使用使能信号en_s和en_m来控制*********/
  55. //秒的代码
  56. cnt60 cnt60_inst1(
  57.     .clk(clk_1hz),
  58.     .rst_n(rst_n),
  59.     .en(en_s),
  60. 	.time_en(time_en),
  61. 	.cnt0(Sec),
  62. 	.cnt_out(Sec_out),
  63.     .cnt1(Sec1),	//秒的个位
  64.     .cnt2(Sec2),	//秒的十位
  65.     .flag(count_s)	//秒的使能信号
  66.     );
  67. //分的代码
  68. cnt60 cnt60_inst2(
  69.     .clk(clk_1hz),
  70.     .rst_n(rst_n),
  71.     .en(en_m),
  72. 	.time_en(time_en),
  73. 	.cnt0(Min),
  74. 	.cnt_out(Min_out),
  75.     .cnt1(Min1),	//分的个位
  76.     .cnt2(Min2),	//分的十位
  77.     .flag(count_m)
  78.     );
  79. //时间的设置
  80. cnt24 cnt24_inst(
  81.     .clk(clk_1hz),
  82.     .rst_n(rst_n),
  83.     .en(en_h),
  84. 	.time_en(time_en),
  85. 	.cnt0(Hour),
  86. 	.cnt_out(Hour_out),
  87.     .cnt1(Hour1),
  88.     .cnt2(Hour2)
  89.     );
  90.  
  91. //数码管控制显示模块
  92. seg_dynamic seg_dynamic_inst
  93. (
  94. 	.clk(sys_clk),
  95. 	.rst_n(rst_n),
  96. 	.Sec1(Sec1),	//秒的个位
  97. 	.Sec2(Sec2),	//秒的十位
  98. 	.Min1(Min1),	//分的个位
  99. 	.Min2(Min2),	//分的十位
  100. 	.Hour1(Hour1),	//时的个位
  101. 	.Hour2(Hour2),	//时的十位
  102. 	.sel (sel), //数码管位选信号
  103. 	.seg(seg) //数码管段选信号	
  104. );
  105.  
  106.  
  107.  
  108. //矩阵键盘设置调节时间
  109. key4x4_clock key4x4_clock_inst(
  110. 	.clk(sys_clk)			,
  111. 	.rst_n(rst_n)			,
  112. 	.Sec_out	(Sec_out)	,	
  113. 	.Min_out	(Min_out)	,
  114. 	.Hour_out	(Hour_out)	,
  115. 	.key_in_y(key_in_y)		,	// 输入矩阵键盘的列信号(KEY0~KEY3)
  116. 	.key_out_x(key_out_x)	,	// 输出矩阵键盘的行信号(KEY4~KEY7)
  117. 	.Sec(Sec)				,	//秒修改
  118. 	.Min(Min)				,	//分修改
  119. 	.Hour(Hour)				,	//时修改	
  120. 	.en(en_s) 				,	//时钟是否运行的使能信号
  121. 	.time_en(time_en)
  122. );
  123. 	
  124. 	
  125. buzzer buzzer_inst(
  126. 	.clk	(sys_clk),
  127. 	.rst_n	(rst_n	),
  128. 	.Sec_out(Sec_out),
  129. 	.Min_out(Min_out),
  130. 	.buzzer (buzzer)
  131.  
  132. );
  133. endmodule	
  134.  
  135.  
  136. /**********************************************************
  137.  
  138. quartusII综合报错（Error (10028): Can't resolve multiple constant drivers for net "txd_cnt[3]"）
  140. 出现这个错误的原因在于，在不同的always逻辑块中，对同一个reg变量进行了赋值。
  141. 在多个alwasy逻辑块同时并行工作的时候，会出现冲突。解决的办法就是，对于一个变量，只在一个always块中，进行赋值。
  143. ***********************************************************/

2. clk1hz.v

将50MHz转化为1Hz的频率，可通过parameter参数N进行更改转化为其他频率

代码如下：

  1. module clk1hz
  2. #(parameter N = 26'd25_000_000)
  3. (
  4.     input clk,
  5.     input rst_n,
  6.     output reg clk_out
  7. );
  8. reg [32:0] tmp;
  9. always @(posedge clk or negedge rst_n) 
  10. begin
  11.     if(!rst_n) begin
  12.         tmp <= 0;
  13. 		  clk_out<=0;
  14.     end
  15.     else if (tmp == N-1)
  16. 		begin 
  17. 			clk_out<= ~clk_out;
  18. 			tmp <= 0;
  19. 		end
  20. 		else
  21. 		begin
  22. 			tmp <= tmp+1;
  23. 			clk_out <=clk_out;
  24. 		end
  25. end
  26. endmodule

3. cnt24.v

代码如下：

  1. module cnt24
  2. // #(parameter CNT = 5'd0)
  3. (
  4.     input	wire		clk		,
  5.     input	wire		rst_n	,
  6.     input	wire		en		,
  7.     input 	wire		time_en	,
  8.     input 	wire	[6:0]	cnt0,
  9. 	output 	reg     [6:0]	cnt_out,	//控制cnt的传入传出
  10.     output	reg		[4:0]	cnt1,
  11.     output	reg		[4:0]	cnt2
  12.     );
  13. reg  [6:0]	cnt;
  14.  
  15. always @(posedge clk or negedge rst_n) 
  16. begin
  17.      if(!rst_n) begin
  18. 		cnt<=cnt0;
  19. 		cnt1<=cnt%10;
  20. 		cnt2<=cnt/10;
  21. 		cnt_out<=cnt;
  22. 	  end
  23.      else 
  24. 	  begin 
  25. 		if(en==1) 
  26. 		begin
  27. 			if(cnt<23)
  28. 			begin
  29. 				cnt<=cnt+1;
  30. 				cnt1<=cnt%10;
  31. 				cnt2<=cnt/10;
  32. 				cnt_out<=cnt;
  33. 			end
  34. 			else begin
  35. 				cnt<=0;
  36. 				cnt1<=cnt%10;
  37. 				cnt2<=cnt/10;
  38. 				cnt_out<=cnt;
  39. 			end
  40. 		end
  41. 	    else  if(time_en==1'b1)begin
  42. 			cnt <=cnt0;
  43. 			cnt1<=cnt%10;
  44. 			cnt2<=cnt/10;
  45. 			cnt_out<=cnt;
  46. 		end 
  47. 		else begin	//if(en_m==0 &&en == 0)begin
  48. 			cnt<=cnt;
  49. 			cnt1<=cnt%10;
  50. 			cnt2<=cnt/10;
  51. 			cnt_out<=cnt;
  52. 		end
  53. 	end
  54. end
  55. endmodule
  57. /*
  58. 				if(cnt1<10)
  59. 					begin
  60. 						cnt1 <= cnt1+1;
  61. 					end
  62. 				else
  63. 					begin
  64. 						cnt1<= 0;
  65. 						cnt2<=cnt2+1;
  66. 					end
  67. */

4. cnt60.v

代码如下：

  1. module cnt60
  2. (
  3.     input 	wire	clk,
  4.     input 	wire	rst_n,
  5.     input 	wire	en,
  6.     input 	wire	time_en,	//修改时钟值的使能信号
  7.     input 	wire [6:0]	cnt0,	//控制cnt的传入传出
  8.     output 	reg  [6:0]	cnt_out,	//控制cnt的传入传出
  9.     output	reg	 [4:0]	cnt1,
  10.     output  reg	 [4:0]	cnt2,
  11.     output	reg			flag
  12. 	);
  13. reg  [6:0]	cnt;	//时钟始终变化着运行着的值
  14.  
  15. always @(posedge clk or negedge rst_n)
  16. begin
  17.      if(!rst_n)
  18. 	 begin
  19. 		cnt<=cnt0;
  20. 		//控制个位和十位的变化
  21. 		cnt1<=cnt%10;
  22. 		cnt2<=cnt/10;
  23. 		cnt_out<=cnt;
  24. 	 end
  25.      else 
  26. 	 begin 
  27. 	  if(en==1)
  28. 	  begin 
  29. 			if(cnt<59)
  30. 			begin
  31. 				cnt <=cnt +1;
  32. 				//控制个位和十位的变化
  33. 				cnt1<=cnt%10;
  34. 				cnt2<=cnt/10;
  35. 				cnt_out<=cnt;
  36. 			end
  37. 			else begin
  38. 				cnt <= 0;
  39. 				cnt1<=cnt%10;
  40. 				cnt2<=cnt/10;
  41. 				cnt_out<=cnt;
  42. 			end
  43. 		end
  44. 	  else  if(time_en==1'b1)begin
  45. 			cnt <=cnt0 ;
  46. 			cnt1<=cnt%10;
  47. 			cnt2<=cnt/10;
  48. 			cnt_out<=cnt;
  49. 		end  
  50. 		else begin
  51. 			cnt <=cnt;
  52. 			cnt1<=cnt%10;
  53. 			cnt2<=cnt/10;
  54. 			cnt_out<=cnt;
  55. 		end
  56. 	 end
  57. end
  59. //当cnt到达58时flag的变化
  60. always @(posedge clk or negedge rst_n)
  61. begin
  62. 	if(!rst_n)
  63. 		flag<=0;
  64. 	else if(cnt <58)
  65. 		flag <=0;
  66. 		else if(cnt == 58)
  67. 		flag <= 1;
  68. 		else flag <= 0;
  69. end
  71. endmodule

5. key4x4_clock.v

代码如下：

  1. `timescale 1ns / 1ps	//精度 可不用
  2. module key4x4_clock(
  3. 	input	wire	clk,
  4. 	input	wire 	rst_n,
  5. 	input 	wire	[6:0]  Sec_out,
  6. 	input 	wire	[6:0]  Min_out,
  7. 	input 	wire	[6:0]  Hour_out,
  8. 	input 	wire 	[3:0]	key_in_y,	// 输入矩阵键盘的列信号(KEY0~KEY3)
  9. 	output 	reg		[3:0]	key_out_x,	// 输出矩阵键盘的行信号(KEY4~KEY7)
  10. 	output	reg		[6:0]   Sec,		//秒修改
  11. 	output	reg		[6:0]   Min,		//分修改
  12. 	output	reg		[6:0]   Hour,		//时修改
  13. 	output	reg		en 			,		//时钟是否运行的使能信号
  14. 	output	reg		time_en 			//时钟是否运行的使能信号
  15. );
  16.  
  17. //寄存器定义
  18. reg [19:0] count;
  19. reg [1:0]  count1;		//时钟修改的时候，在修改时它的值等于当前已经变化后的值，count1作为该修改值的使能信号
  20.  
  21.  
  22. //==============================================
  23. // 输出矩阵键盘的行信号，20ms 扫描矩阵键盘一次,采样频率小于按键毛刺频率，相当于滤除掉了高频毛刺信号。
  24. //==============================================
  25. always @(posedge clk or negedge rst_n) //检测时钟的上升沿和复位的下降沿
  26. begin
  27. 	 if(!rst_n) begin //复位信号低有效
  28. 		count <= 20'd0; //计数器清 0
  29. 		key_out_x <= 4'b1111; 
  30. 	 end
  31. 	 else begin
  32. 	 if(count == 20'd0) //0ms 扫描第一行矩阵键盘
  33. 	 begin
  34. 		key_out_x <= 4'b1110; //开始扫描第一行矩阵键盘,第一行输出0
  35. 		count <= count + 20'b1; //计数器加1
  36. 	 end
  37. 	 else if(count == 20'd249_999) //5ms 扫描第二行矩阵键盘,5ms 计数(50M/200-1=249_999)
  38. 	 begin
  39. 		key_out_x <= 4'b1101; //开始扫描第二行矩阵键盘,第二行输出 0
  40. 		count <= count + 20'b1; //计数器加 1
  41. 	 end
  42. 	else if(count ==20'd499_999) //10ms扫描第三行矩阵键盘 ,10ms计数(50M/100-1=499_999)
  43. 	 begin
  44. 		key_out_x <= 4'b1011; //扫描第三行矩阵键盘,第三行输出0
  45. 		count <= count + 20'b1; //计数器加1
  46. 	 end
  47. 	else if(count ==20'd749_999) //15ms扫描第四行矩阵键盘 ,15ms 计 数(50M/67.7-1=749_999)
  48. 	 begin
  49. 		key_out_x <= 4'b0111; //扫描第四行矩阵键盘,第四行输出0
  50. 		count <= count + 20'b1; //计数器加 1
  51. 	 end
  52. 	 else if(count ==20'd999_999) //20ms 计数(50M/50-1=999_999)
  53. 	 begin
  54. 		count <= 0; //计数器为 0
  55. 	 end
  56. 	 else
  57. 		count <= count + 20'b1; //计数器加 1
  58. 	 end
  59. end
  60. //====================================================
  61. // 采样列的按键信号
  62. //====================================================
  63. reg [3:0] key_h1_scan; //第一行按键扫描值 KEY
  64. reg [3:0] key_h1_scan_r; //第一行按键扫描值寄存器 KEY
  65. reg [3:0] key_h2_scan; //第二行按键扫描值 KEY
  66. reg [3:0] key_h2_scan_r; //第二行按键扫描值寄存器 KEY
  67. reg [3:0] key_h3_scan; //第三行按键扫描值 KEY
  68. reg [3:0] key_h3_scan_r; //第三行按键扫描值寄存器 KEY
  69. reg [3:0] key_h4_scan; //第四行按键扫描值 KEY
  70. reg [3:0] key_h4_scan_r; //第四行按键扫描值寄存器 KEY
  71. always @(posedge clk)
  72. begin
  73. 	if(!rst_n) begin //复位信号低有效
  74. 		key_h1_scan <= 4'b1111; 
  75. 		key_h2_scan <= 4'b1111; 
  76. 		key_h3_scan <= 4'b1111; 
  77. 		key_h4_scan <= 4'b1111; 
  78. 	end
  79. 	else begin
  80. 		 if(count == 20'd124_999) //2.5ms 扫描第一行矩阵键盘值
  81. 			key_h1_scan<=key_in_y; //扫描第一行的矩阵键盘值
  82. 		 else if(count == 20'd374_999) //7.5ms 扫描第二行矩阵键盘值
  83. 			key_h2_scan<=key_in_y; //扫描第二行的矩阵键盘值
  84. 		 else if(count == 20'd624_999) //12.5ms 扫描第三行矩阵键盘值
  85. 			key_h3_scan<=key_in_y; //扫描第三行的矩阵键盘值
  86. 		 else if(count == 20'd874_999) //17.5ms 扫描第四行矩阵键盘值
  87. 			key_h4_scan<=key_in_y; //扫描第四行的矩阵键盘值
  88. 	end
  89. end
  90.  
  91. //====================================================
  92. // 按键信号锁存一个时钟节拍
  93. //====================================================
  94. always @(posedge clk)
  95.  begin
  96. 	key_h1_scan_r <= key_h1_scan; 
  97. 	key_h2_scan_r <= key_h2_scan; 
  98. 	key_h3_scan_r <= key_h3_scan; 
  99. 	key_h4_scan_r <= key_h4_scan; 
  100. end 
  101.  
  102.  
  103. wire [3:0] flag_h1_key = key_h1_scan_r[3:0] & (~key_h1_scan[3:0]); //当检测到按键有下降沿变化时，代表该按键被按下，按键有效
  104. wire [3:0] flag_h2_key = key_h2_scan_r[3:0] & (~key_h2_scan[3:0]); //当检测到按键有下降沿变化时，代表该按键被按下，按键有效
  105. wire [3:0] flag_h3_key = key_h3_scan_r[3:0] & (~key_h3_scan[3:0]); //当检测到按键有下降沿变化时，代表该按键被按下，按键有效
  106. wire [3:0] flag_h4_key = key_h4_scan_r[3:0] & (~key_h4_scan[3:0]); //当检测到按键有下降沿变化时，代表该按键被按下，按键有效
  107.  
  108.  
  109.  
  110.  
  111.  
  112. /* 状态参数的定义  --- 可以使用独热码  */
  113. parameter   IDLE    =   5'b00001,	//初始状态(也是终态)	使能信号正常，可以初次进行时钟正常运行
  114.             ONE     =   5'b00010,	//设置秒的个十位
  115.             TWO     =   5'b00100,	//设置分
  116.             THREE 	=   5'b01000,	//设置时
  117.             SETTING	=   5'b10000;	//时间设置键	使能信号失效
  119. /**************按键排列******************
  120. 	K1设置键		K2设置秒		K3设置分		K4设置时
  121. 	K5确认键		
  122. 	K9时间加		K10时间减
  123. *****************************************/
  124. reg [4:0]  state ;	//状态跳变
  126. //状态跳转
  127. always@ (posedge clk or negedge rst_n)
  128. begin
  129. 	if(rst_n == 1'b0)
  130. 		state <=IDLE;
  131. 	else 
  132. 		case(state)
  133. 			IDLE:	if(flag_h1_key[0]==1'b1)
  134. 						state	<=	SETTING;
  135. 					else 
  136. 						state <= IDLE;
  137. 			SETTING:if(flag_h1_key[1]==1'b1)
  138. 						state <= ONE;
  139. 					else 	if(flag_h1_key[2]==1'b1)
  140. 						state <= TWO;
  141. 					else	if(flag_h1_key[3]==1'b1)
  142. 						state <= THREE;
  143. 					else	if(flag_h2_key[0]==1'b1)
  144. 						state <= IDLE;
  145. 					else 	
  146. 						state <= SETTING;
  147. 			
  148. 			ONE:	if(flag_h1_key[2])
  149. 						state <= TWO;
  150. 					else	if(flag_h1_key[3]==1'b1)
  151. 						state <= THREE;
  152. 					else	if(flag_h2_key[0]==1'b1)
  153. 						state <= IDLE;
  154. 					else 	
  155. 						state <= ONE;
  156. 			TWO:	if(flag_h1_key[1])
  157. 						state <= ONE;
  158. 					else	if(flag_h1_key[3]==1'b1)
  159. 						state <= THREE;
  160. 					else	if(flag_h2_key[0]==1'b1)
  161. 						state <= IDLE;
  162. 					else 	
  163. 						state <= TWO;
  164. 			THREE:	if(flag_h1_key[1]==1'b1)
  165. 						state <= ONE;
  166. 					else	if(flag_h1_key[2]==1'b1)
  167. 						state <= TWO;
  168. 					else	if(flag_h2_key[0]==1'b1)
  169. 						state <= IDLE;
  170. 					else 	
  171. 						state <= THREE;
  172. 			default:state <=IDLE;
  173. 		endcase
  174. end
  175.  
  176. /* 描述状态IDLE和SETTING的输出 */
  177. always@(posedge clk or negedge rst_n)
  178. begin 
  179.     if(rst_n==1'b0)begin
  180. 		en <= 1'b0;
  181. 		time_en <= 1'b0;
  182. 		count1 <=1'b0;
  183. 	end
  184.     else    if(state <= IDLE) begin		//相当于确认按键，按下以后使能信号有效，时钟继续运行
  185.         en  <= 1'b1;
  186. 		time_en <= 1'b0;
  187. 	end
  188. 	else    if(state <= SETTING)begin
  189.         en <= 1'b0;
  190. 		time_en <= 1'b1;
  191. 		count1 <= 1'b1;
  192. 	end
  193. 	else if(flag_h2_key[0]==1'b1) 
  194. 		count1 <= 1'b0;
  195. 	else begin
  196. 		en <= en;
  197. 	end
  198. end 
  200. /* 描述ONE状态的输出 */
  201. always@(posedge clk or negedge rst_n)
  202. begin 
  203.     if(rst_n==1'b0)begin
  204.         Sec <= 7'd57;
  205. 	end
  206. 	else if(state==SETTING && count1 ==1'b0)begin
  207. 		Sec <= Sec_out;
  208. 	end
  209. 	else if (state == ONE && flag_h3_key[0] == 1'b1 && Sec < 59)
  210.         Sec <=Sec + 1'b1;
  211.     else    if (state == ONE && flag_h3_key[1] == 1'b1 && Sec >0)
  212.         Sec <=Sec - 1'b1;
  213. 	else 	if(state == ONE && flag_h3_key[0] == 1'b1 && Sec == 7'd59)
  214. 		Sec<= 7'd0;
  215. 	else 	if(state == ONE && flag_h3_key[1] == 1'b1 && Sec == 7'd0)
  216. 		Sec<=7'd59;
  217. 	else 
  218. 		Sec <=Sec;
  219. end
  220.  
  221. /* 描述TWO状态的输出 */
  222. always@(posedge clk or negedge rst_n)
  223. begin 
  224.     if(rst_n==1'b0)begin
  225.         Min <= 7'd46;
  226. 	end
  227. 	else if(state==SETTING && count1 ==1'b0)begin
  228. 		Min <= Min_out;
  229. 	end
  230. 	else if (state == TWO && flag_h3_key[0] == 1'b1 && Min < 59)
  231.         Min <= Min + 1'b1;
  232.     else    if (state == TWO && flag_h3_key[1] == 1'b1 && Min >0)
  233.         Min <= Min - 1'b1;
  234. 	else 	if(state == TWO && flag_h3_key[0] == 1'b1 && Min == 7'd59)
  235. 		Min<= 7'd0;
  236. 	else 	if(state == TWO && flag_h3_key[1] == 1'b1 && Min == 7'd0)
  237. 		Min<=7'd59;
  238. 	else 
  239. 		Min <= Min;
  240. end
  242. /* 描述THREE状态的输出 */
  243. always@(posedge clk or negedge rst_n)
  244. begin 
  245.     if(rst_n==1'b0)begin
  246.         Hour<= 7'd12;
  247. 	end
  248. 		else if(state==SETTING && count1 ==1'b0)begin
  249. 		Hour <= Hour_out;
  250. 	end
  251. 	else if (state == THREE && flag_h3_key[0] == 1'b1 && Hour < 7'd23)
  252.         Hour <=Hour + 1'b1;
  253.     else    if (state == THREE && flag_h3_key[1] == 1'b1 && Hour > 7'd0)
  254.         Hour <=Hour - 1'b1;
  255. 	else 	if(state == THREE && flag_h3_key[0] == 1'b1 && Hour == 7'd23)
  256. 		Hour<= 7'd0;
  257. 	else 	if(state == THREE && flag_h3_key[1] == 1'b1 && Hour == 7'd0)
  258. 		Hour<=7'd23;
  259. 	else
  260. 		Hour <=Hour;
  261. end
  262.  
  263. endmodule

6. seg_dynamic.v

代码如下：

  1. module seg_dynamic
  2. (
  3. 	input 	wire 	clk,
  4. 	input	wire	rst_n,
  5. 	input	wire	[4:0]	Sec1,	//秒的个位
  6. 	input	wire	[4:0]	Sec2,	//秒的十位
  7. 	input	wire 	[4:0]	Min1,	//分的个位
  8. 	input	wire 	[4:0]	Min2,	//分的十位
  9. 	input	wire 	[4:0]	Hour1,	//时的个位
  10. 	input	wire 	[4:0]	Hour2,	//时的十位
  11. 	output 	reg 	[5:0] 	sel , 	//数码管位选信号
  12. 	output 	reg 	[7:0] 	seg 	//数码管段选信号	
  13. );
  14.  //十六进制数显示编码
  15. parameter 
  16. 	SEG_0 = 8'b1100_0000, 
  17. 	SEG_1 = 8'b1111_1001,
  18. 	SEG_2 = 8'b1010_0100, 
  19. 	SEG_3 = 8'b1011_0000,
  20. 	SEG_4 = 8'b1001_1001, 
  21. 	SEG_5 = 8'b1001_0010,
  22. 	SEG_6 = 8'b1000_0010, 
  23. 	SEG_7 = 8'b1111_1000,
  24. 	SEG_8 = 8'b1000_0000, 
  25. 	SEG_9 = 8'b1001_0000,
  26. 	SEG_A = 8'b1000_1000, SEG_B = 8'b1000_0011,
  27. 	SEG_C = 8'b1100_0110, SEG_D = 8'b1010_0001,
  28. 	SEG_E = 8'b1000_0110, SEG_F = 8'b1000_1110;
  29. parameter IDLE = 8'b1111_1111; //不显示状态
  31. //reg define
  32. reg [23:0] data_reg ; //待显示数据寄存器
  33. reg [15:0] cnt_1ms ; //1ms计数器
  34. reg flag_1ms ; //1ms标志信号
  35. reg [2:0] cnt_sel ; //数码管位选计数器
  36. reg [5:0] sel_reg ; //位选信号
  37. reg [3:0] data_disp ; //当前数码管显示的数据
  38. parameter CNT_MAX = 16'd49_999; //数码管刷新时间计数最大值
  39.  
  40. reg  [7:0]   led_SG   ;  //秒的个位
  41. reg  [7:0]   led_SS   ;  //秒的十位
  42. reg  [7:0]   led_MG   ;  //分的个位
  43. reg  [7:0]   led_MS   ;  //分的十位
  44. reg  [7:0]   led_HG   ;  //时的个位
  45. reg  [7:0]   led_HS   ;  //时的十位
  46.  
  47. /****************************************************
  48. *****************数码管段选信号**********************
  49. ******************************************************/
  50.  
  51. //七段数码管显示秒的个位
  52. always @(posedge clk or negedge rst_n)begin
  53. if(rst_n==1'b0)
  54.   led_SG<=IDLE;
  55. else begin
  56.   case(Sec1)
  57.   0: led_SG<=SEG_0;
  58.   1: led_SG<=SEG_1;
  59.   2: led_SG<=SEG_2;
  60.   3: led_SG<=SEG_3;
  61.   4: led_SG<=SEG_4;
  62.   5: led_SG<=SEG_5;
  63.   6: led_SG<=SEG_6;
  64.   7: led_SG<=SEG_7;
  65.   8: led_SG<=SEG_8;
  66.   9: led_SG<=SEG_9;
  67.    default led_SG<=IDLE;
  68.   endcase
  69.  end
  70. end
  72. //七段数码管显示秒的十位
  73. always @(posedge clk or negedge rst_n)begin
  74. if(rst_n==1'b0)
  75.   led_SS<=IDLE;
  76. else begin
  77.   case(Sec2)
  78.   0: led_SS<=SEG_0;
  79.   1: led_SS<=SEG_1;
  80.   2: led_SS<=SEG_2;
  81.   3: led_SS<=SEG_3;
  82.   4: led_SS<=SEG_4;
  83.   5: led_SS<=SEG_5;
  84.   6: led_SS<=SEG_6;
  85.   7: led_SS<=SEG_7;
  86.   8: led_SS<=SEG_8;
  87.   9: led_SS<=SEG_9;
  88.    default led_SS<=IDLE;
  89.   endcase
  90.  end
  91. end
  92.  
  93. //七段数码管显示分的个位
  94. always @(posedge clk or negedge rst_n)begin
  95. if(rst_n==1'b0)
  96.   led_MG<=IDLE;
  97. else begin
  98.   case(Min1)
  99.   0: led_MG<=8'b0100_0000;
  100.   1: led_MG<=8'b0111_1001;
  101.   2: led_MG<=8'b0010_0100;
  102.   3: led_MG<=8'b0011_0000;
  103.   4: led_MG<=8'b0001_1001;
  104.   5: led_MG<=8'b0001_0010;
  105.   6: led_MG<=8'b0000_0010;
  106.   7: led_MG<=8'b0111_1000;
  107.   8: led_MG<=8'b0000_0000;
  108.   9: led_MG<=8'b0001_0000;
  109.    default led_MG<=8'b0111_1111;
  110.   endcase
  111.  end
  112. end
  113.  
  114. //七段数码管显示分的十位
  115. always @(posedge clk or negedge rst_n)begin
  116. if(rst_n==1'b0)
  117.   led_MS<=IDLE;
  118. else begin
  119.   case(Min2)
  120.   0: led_MS<=SEG_0;
  121.   1: led_MS<=SEG_1;
  122.   2: led_MS<=SEG_2;
  123.   3: led_MS<=SEG_3;
  124.   4: led_MS<=SEG_4;
  125.   5: led_MS<=SEG_5;
  126.   6: led_MS<=SEG_6;
  127.   7: led_MS<=SEG_7;
  128.   8: led_MS<=SEG_8;
  129.   9: led_MS<=SEG_9;
  130.    default led_MS<=IDLE;
  131.   endcase
  132.  end
  133. end
  135. //七段数码管显示时的个位
  136. always @(posedge clk or negedge rst_n)begin
  137. if(rst_n==1'b0)
  138.   led_HG <= IDLE;
  139. else begin
  140.   case(Hour1)
  141.   0: led_HG <= 8'b0100_0000;
  142.   1: led_HG <= 8'b0111_1001;
  143.   2: led_HG <= 8'b0010_0100;
  144.   3: led_HG <= 8'b0011_0000;
  145.   4: led_HG <= 8'b0001_1001;
  146.   5: led_HG <= 8'b0001_0010;
  147.   6: led_HG <= 8'b0000_0010;
  148.   7: led_HG <= 8'b0111_1000;
  149.   8: led_HG <= 8'b0000_0000;
  150.   9: led_HG <= 8'b0001_0000;
  151.    default led_HG <= 8'b0111_1111;
  152.   endcase
  153.  end
  154. end
  156. //七段数码管显示时的十位
  157. always @(posedge clk or negedge rst_n)begin
  158. if(rst_n==1'b0)
  159.   led_HS<=IDLE;
  160. else begin
  161.   case(Hour2)
  162.   0: led_HS<=SEG_0;
  163.   1: led_HS<=SEG_1;
  164.   2: led_HS<=SEG_2;
  165.   3: led_HS<=SEG_3;
  166.   // 4: led_HS<=SEG_4;
  167.   // 5: led_HS<=SEG_5;
  168.   // 6: led_HS<=SEG_6;
  169.   // 7: led_HS<=SEG_7;
  170.   // 8: led_HS<=SEG_8;
  171.   // 9: led_HS<=SEG_9;
  172.    default led_HS<=IDLE;
  173.   endcase
  174.  end
  175. end
  176.  
  177.  
  178.  
  179. /****************************************************
  180. *****************数码管位选信号**********************
  181. ******************************************************/
  182.  
  183.  
  184. //cnt_1ms:1ms循环计数
  185. always@(posedge clk or negedge rst_n)
  186. 	if(rst_n == 1'b0)
  187. 		cnt_1ms <= 16'd0;
  188. 	else if(cnt_1ms == CNT_MAX)
  189. 		cnt_1ms <= 16'd0;
  190. 	else
  191. 		cnt_1ms <= cnt_1ms + 1'b1;
  192. //flag_1ms:1ms标志信号
  193. always@(posedge clk or negedge rst_n)
  194. 	if(rst_n == 1'b0)
  195. 		flag_1ms <= 1'b0;
  196. 	else if(cnt_1ms == CNT_MAX - 1'b1)
  197. 		flag_1ms <= 1'b1;
  198. 	else
  199. 		flag_1ms <= 1'b0;
  200. 		
  201. //cnt_sel：从0到5循环数，用于选择当前显示的数码管
  202. always@(posedge clk or negedge rst_n)
  203. 	if(rst_n == 1'b0)
  204. 		cnt_sel <= 3'd0;
  205. 	else if((cnt_sel == 3'd5) && (flag_1ms == 1'b1))
  206. 		cnt_sel <= 3'd0;
  207. 	 else if(flag_1ms == 1'b1)
  208. 		cnt_sel <= cnt_sel + 1'b1;
  209. 	 else
  210. 		cnt_sel <= cnt_sel;
  211.  
  212.  //数码管位选信号寄存器
  213.  always@(posedge clk or negedge rst_n)
  214. 	 if(rst_n == 1'b0)
  215. 		sel_reg <= 6'b000_000;
  216. 	 else if((cnt_sel == 3'd0) && (flag_1ms == 1'b1))
  217. 		sel_reg <= 6'b000_001;
  218. 	 else if(flag_1ms == 1'b1)
  219. 		sel_reg <= sel_reg << 1;
  220. 	 else
  221. 		sel_reg <= sel_reg;
  223.  //控制数码管的位选信号，使六个数码管轮流显示
  224. always@(posedge clk or negedge rst_n)
  225.  if(rst_n == 1'b0)
  226. 	seg <= 8'hff;
  227.  else if( flag_1ms == 1'b1)
  228. 	case(cnt_sel)
  229. 		3'd0: seg <= led_HS; //给第6个数码管赋十万位值
  230. 		3'd1: seg <= led_HG; //给第5个数码管赋万位值
  231. 		3'd2: seg <= led_MS; //给第4个数码管赋千位值
  232. 		3'd3: seg <= led_MG ; //给第3个数码管赋百位值
  233. 		3'd4: seg <= led_SS ; //给第2个数码管赋十位值
  234. 		3'd5: seg <= led_SG ; //给第1个数码管赋个位值
  235. 	default:seg <= 8'hff;
  236. 	endcase
  237. 	else
  238. 		seg <= seg;
  239.  
  240.  //sel:数码管位选信号赋值
  241. always@(posedge clk or negedge rst_n)
  242.  if(rst_n == 1'b0)
  243.  sel <= 6'b111_111;
  244.  else
  245.  sel <= ~sel_reg;
  246.  
  247. endmodule

7. buzzer.v

buzzer==0响否则=1不响，歌曲放了两首，都能使用，自行选择，但意义不大。

代码如下：

  1. ​
  2. module buzzer(
  3. 	input 	wire	clk		,			//系统时钟50MHz	
  4. 	input	wire	rst_n	,
  5. 	input 	wire	[6:0] Sec_out	,
  6. 	input 	wire	[6:0] Min_out	,
  7. 	// input 	wire	Min1	,
  8. 	// input 	wire	Min2	,
  9. 	output	reg	buzzer					//蜂鸣器输出端
  10.  
  11. );
  12. // assign buzzer =( Sec_out==1'b0 && Min_out==1'b0 )?0:1;	//只响一秒钟
  13.  
  14.  
  15. /**********--------------森林狂想曲-----------------************************/
  16. //模块名称song						
  17. reg		beep_r;				//寄存器
  18. reg[7:0] state;				//乐谱状态机
  19. reg[16:0]count,count_end;
  20. reg[23:0]count1;
  21.  
  22. //乐谱参数:D=F/2K  (D:参数,F:时钟频率,K:音高频率)
  23. parameter   L_3 = 17'd75850,  //低音3
  24. 			L_5 = 17'd63776,  //低音5
  25. 			L_6 = 17'd56818,	//低音6
  26. 			L_7 = 17'd50618,	//低音7
  27. 			M_1 = 17'd47774,	//中音1
  28. 			M_2 = 17'd42568,	//中音2
  29. 			M_3 = 17'd37919,	//中音3
  30. 			M_5 = 17'd31888,	//中音5
  31. 			M_6 = 17'd28409,	//中音6
  32. 			H_1 = 17'd23889;	//高音1			
  33. parameter	TIME = 12000000;	//控制每一个音的长短(250ms)									
  34. // assign buzzer = beep_r;			//输出音乐
  35.  
  36. //★★★以下两个时序逻辑模块较为重点关注
  37. always @(posedge clk or negedge rst_n)
  38. begin
  39.     if(!rst_n)begin
  40. 		buzzer <= 1'b1;
  41. 	end
  42. 	else if(Min_out==1'b0 && Sec_out<=7'd3) 	//整点报时并3s后停止
  43. 		buzzer <= beep_r;
  44. 	else 
  45. 		buzzer <=1'b1;
  46. end
  47.  
  48.  
  49. always@(posedge clk) begin
  50. 	count <= count + 1'b1;		//计数器加1
  51. 	if(count == count_end) begin	
  52. 		count <= 17'h0;			//计数器清零
  53. 		beep_r <= !beep_r;		//输出取反
  54. 	end
  55. end
  56.  
  57. //曲谱 产生分频的系数并描述出曲谱
  58. always @(posedge clk) begin
  59.    if(count1 < TIME)             //一个节拍250mS
  60.       count1 = count1 + 1'b1;
  61.    else begin
  62.       count1 = 24'd0;
  63.       if(state == 8'd63)
  64.          state = 8'd0;
  65.       else
  66.          state = state + 1'b1;
  67.    case(state)
  68.    8'd0:count_end = L_6;  
  69. 	8'd1:count_end=M_1;
  70. 	8'd2:count_end=M_3;
  71. 	8'D3:count_end=M_5;
  72. 	8'D4,8'D5:count_end=M_3;
  73. 	8'D6:count_end=M_3;
  74. 	8'D7:count_end=M_2;
  75.    
  76. 	8'D8,8'D9:count_end=M_3;
  77. 	8'D10:count_end=M_3;
  78. 	8'D11:count_end=M_2;
  79. 	8'D12,8'D13:count_end=M_3;
  80. 	8'D14:count_end=L_6;
  81. 	8'D15:count_end=L_7;
  82. 	
  83. 	8'D16:count_end=M_1;
  84. 	8'D17:count_end=M_3;
  85. 	8'D18:count_end=M_2;
  86. 	8'D19:count_end=M_1;
  87. 	8'D20,8'D21:count_end=L_6;
  88. 	8'D22,8'D23:count_end=L_5;
  89. 	
  90. 	8'D24,8'D25,8'D26,8'D27,8'D28,8'D29,8'D30,8'D31:count_end=L_3;
  91. 	
  92. 	8'd32:count_end = L_6;  
  93. 	8'd33:count_end=M_1;
  94. 	8'd34:count_end=M_3;
  95. 	8'D35:count_end=M_5;
  96. 	8'D36,8'D37:count_end=M_3;
  97. 	8'D38:count_end=M_3;
  98. 	8'D39:count_end=M_2;
  99.    
  100. 	8'D40,8'D41:count_end=M_3;
  101. 	8'D42:count_end=M_3;
  102. 	8'D43:count_end=M_2;
  103. 	8'D44,8'D45:count_end=M_3;
  104. 	8'D46:count_end=L_6;
  105. 	8'D47:count_end=L_7;
  106. 	
  107. 	8'D48:count_end=M_1;
  108. 	8'D49:count_end=M_3;
  109. 	8'D50:count_end=M_2;
  110. 	8'D51:count_end=M_1;
  111. 	8'D52,8'D53:count_end=L_6;
  112. 	8'D54,8'D55:count_end=L_5;
  113. 	
  114. 	8'D56,8'D57,8'D58,8'D59,8'D60,8'D61:count_end=L_6;
  115. 	8'D62:count_end=L_6;
  116. 	8'D63:count_end=L_7;
  117.    default: count_end = 16'h0;
  118.    endcase
  119.    end
  120. end
  121.  
  122.  
  123. /************************************************************************
  124. -------------------------两只老虎----------------------------------------
  125.  
  126. //中间信号定义
  127. reg     [16:0]     cnt0    ;       //产生PWM的计数器
  128. wire               add_cnt0;
  129. wire               end_cnt0;
  130.  
  131. reg     [7:0]      cnt1    ;      //每个音符持续时间的计数器
  132. wire               add_cnt1;
  133. wire               end_cnt1;
  134.  
  135. reg     [5:0]      cnt2    ;     //《两只老虎》共32个音节
  136. wire               add_cnt2;
  137. wire               end_cnt2;
  138.  
  139. reg     [16:0]     pre_set ;    //存放每个音节的频率在系统中的时钟个数
  140.  
  141. //每个音符对应的系统周期计数,中音
  142. localparam  M1=95602,           //音符1do
  143. 	        M2=85178,           //音符rui
  144. 	        M3=75872,           //音符mi
  145. 	        M4=71633,           //音符fa
  146. 	        M5=63775,           //音符so
  147. 	        M6=56818,           //音符la
  148. 	        M7=50607;           //音符xi
  149.  
  150. //每个音符对应的系统周期计数,低音音符so，频率392
  151. //周期是1/392s,换算成ns是2551020ns,每个
  152. //系统时钟周期是20ns，所以上述是2551020/20个系统周期个数127,551
  153. localparam  D5=127551;         //音符so,低音
  154.  
  155.  
  156. //每个音节的频率在系统时钟周期下对应的系统周期个数
  157. //--------------------------------------------
  158. //比如：音符1的频率是523HZ，它的周期是1/523s,换算成ns是1912045ns,每个
  159. //系统时钟周期是20ns，所以上述是1912045/20个系统周期个数，即cnt0的计数
  160. always @(posedge clk or negedge rst_n)begin
  161.     if(!rst_n)begin
  162.         cnt0<=0;
  163.     end
  164.     else if(add_cnt0)begin
  165.         if(end_cnt0)
  166.             cnt0<=0;
  167.         else
  168.             cnt0<=cnt0+1;  
  169.     end
  170. end
  171. assign add_cnt0=1'b1;
  172. assign end_cnt0=add_cnt0 && cnt0==pre_set-1;
  173. // assign buzzer=(cnt0>=(pre_set/2) && Min_out==1'b0)?1:0;          //每个音符的占空比为50%
  174.  
  175. //每个音符持续一段时间
  176. always @(posedge clk or negedge rst_n)
  177. begin
  178.     if(!rst_n)begin
  179. 		buzzer <= 1'b1;
  180. 	end
  181. 	else if(cnt0>=(pre_set/2) && Min_out==1'b0 && Sec_out<=7'd3) 
  182. 		buzzer <= 1'b0;
  183. 	else 
  184. 		buzzer <=1'b1;
  185. end
  188. //每个音符持续一段时间
  189. always @(posedge clk or negedge rst_n)begin
  190.     if(!rst_n)begin
  191.         cnt1<=0;
  192.     end
  193.     else if(add_cnt1)begin
  194.         if(end_cnt1)
  195.             cnt1<=0;
  196.         else
  197.             cnt1<=cnt1+1; 
  198.     end
  199. end
  200. assign add_cnt1=end_cnt0;
  201. assign end_cnt1=add_cnt1 && cnt1==150-1;
  203. //计32个音符(两只老虎共32音节)
  204. always @(posedge clk or negedge rst_n)begin
  205.     if(!rst_n)begin
  206.         cnt2<=0;  
  207.     end
  208.     else if(add_cnt2)begin
  209.         if(end_cnt2)
  210.             cnt2<=0;   
  211.         else 
  212.             cnt2<=cnt2+1;
  213.     end
  214. end
  215. assign add_cnt2=end_cnt1;
  216. assign end_cnt2=add_cnt2 && cnt2==32-1;
  218. //存放歌曲的简谱
  219. always @(posedge clk or negedge rst_n)
  220. begin
  221.     if(!rst_n)begin
  222.         pre_set<=0;  
  223.     end
  224.     else begin
  225.         case(cnt2)
  226.                 0:pre_set<=M1;
  227. 				1:pre_set<=M2;
  228. 				2:pre_set<=M3;
  229. 				3:pre_set<=M1;
  230. 				4:pre_set<=M1;
  231. 				5:pre_set<=M2;
  232. 				6:pre_set<=M3;
  233. 				7:pre_set<=M1;
  234. 				8:pre_set<=M3;
  235. 				9:pre_set<=M4;
  236. 				10:pre_set<=M5;
  237. 				11:pre_set<=M3;
  238. 				12:pre_set<=M4;
  239. 				13:pre_set<=M5;
  240. 				14:pre_set<=M5;
  241. 				15:pre_set<=M6;
  242. 				16:pre_set<=M5;
  243. 				17:pre_set<=M4;
  244. 				18:pre_set<=M3;
  245. 				19:pre_set<=M1;
  246. 				20:pre_set<=M5;
  247. 				21:pre_set<=M6;
  248. 				22:pre_set<=M5;
  249. 				23:pre_set<=M4;
  250. 				24:pre_set<=M3;
  251. 				25:pre_set<=M1;
  252. 				26:pre_set<=M2;
  253. 				27:pre_set<=D5;
  254. 				28:pre_set<=M1;
  255. 				29:pre_set<=M2;
  256. 				30:pre_set<=D5;
  257. 				31:pre_set<=M1;
  258. 				default:pre_set<=0;
  259.         endcase
  260.     end
  261. end
  263. */
  265. endmodule
  267. ​

        对于以上各个模块内，进行了非常清晰的层次化设计，大部分都有了较为详细的标注，并通过了基础测试验证。从顶层文件开始，对照各个参数寄存器等依次往下进行理解比较，最后得出自己的设计结果。

对于各个引脚配置如下：

       对于引脚的配置，可直接将如下配置直接复制到EDA_clock.qsf文件中，然后进行综合即可直接配置完成。

  1. set_location_assignment PIN_E1 -to sys_clk
  2. set_location_assignment PIN_N13 -to rst_n
  3. set_location_assignment PIN_R14 -to seg[0]
  4. set_location_assignment PIN_N9 -to sel[0]
  5. set_location_assignment PIN_P9 -to sel[1]
  6. set_location_assignment PIN_M10 -to sel[2]
  7. set_location_assignment PIN_N11 -to sel[3]
  8. set_location_assignment PIN_P11 -to sel[4]
  9. set_location_assignment PIN_M11 -to sel[5]
  10. set_location_assignment PIN_N16 -to seg[1]
  11. set_location_assignment PIN_P16 -to seg[2]
  12. set_location_assignment PIN_T15 -to seg[3]
  13. set_location_assignment PIN_P15 -to seg[4]
  14. set_location_assignment PIN_N12 -to seg[5]
  15. set_location_assignment PIN_N15 -to seg[6]
  16. set_location_assignment PIN_R16 -to seg[7]
  17. set_location_assignment PIN_B5 -to key_in_y[3]
  18. set_location_assignment PIN_A4 -to key_in_y[2]
  19. set_location_assignment PIN_B4 -to key_in_y[1]
  20. set_location_assignment PIN_A3 -to key_in_y[0]
  21. set_location_assignment PIN_B3 -to key_out_x[3]
  22. set_location_assignment PIN_A2 -to key_out_x[2]
  23. set_location_assignment PIN_B1 -to key_out_x[1]
  24. set_location_assignment PIN_C2 -to key_out_x[0]
  25. set_location_assignment PIN_C11 -to buzzer

运行成功：

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