基于vivado+Verilog FPGA开发 — 使用状态机实现按键消抖_vivado频率计怎么实现消抖

代码规范：Verilog 代码规范_verilog代码编写规范-CSDN博客

开发流程：FPGA基础知识----第二章 FPGA 开发流程_fpga 一个项目的整个流程-CSDN博客 

源码下载：GitHub - Redamancy785/FPGA-Learning-Record: 项目博客：https://blog.csdn.net/weixin_51460407

一、功能定义

二、设计输入 

module key_filter(
    clk_i,
    reset_n_i,
    key_i,
    press_key_flag_o,
    release_key_flag_o
    );
    
    input clk_i,reset_n_i,key_i; 
    output press_key_flag_o,release_key_flag_o;
    
    reg press_key_flag_o,release_key_flag_o;
    reg [1:0] state; 
    wire time_20ms_reached;
    localparam IDLE = 0;
    localparam PRESS_FILTER = 1;
    localparam WAIT = 2;
    localparam RELEASE_FILTER = 3;
    
    // 输入 key_i 同步处理
    reg r_key_i,sync_d_0_key_i,sync_d_1_key_i; 
    wire nedge_key,pedge_key;
    always@(posedge clk_i)
        sync_d_0_key_i <= key_i;
    always@(posedge clk_i)
        sync_d_1_key_i <= sync_d_0_key_i;
    always@(posedge clk_i)
        r_key_i <= sync_d_1_key_i;
   
    assign nedge_key = r_key_i & (~sync_d_1_key_i); 
    assign pedge_key = ~r_key_i & sync_d_1_key_i;
 
    // 状态机 
    always@(posedge clk_i or negedge reset_n_i)
    if(!reset_n_i) begin
        release_key_flag_o <= 0;
        press_key_flag_o <= 0;
        state <= IDLE;
    end
    else begin 
        case(state)
            IDLE :
                begin
                    release_key_flag_o <= 0;
                    if(nedge_key)
                        state <= PRESS_FILTER;
                    else 
                        state <= IDLE;
                end
                
            PRESS_FILTER :
                if(time_20ms_reached) begin
                    state <= WAIT;
                    press_key_flag_o <= 1;
                end
                else if(pedge_key)
                    state <= IDLE;
                else 
                    state <= PRESS_FILTER;
                    
            WAIT :
                begin
                    press_key_flag_o <= 0;
                    if(pedge_key)
                        state <= RELEASE_FILTER;
                    else
                        state <= WAIT;
                end
                
            RELEASE_FILTER :
                if(time_20ms_reached) begin
                    state <= IDLE;
                    release_key_flag_o <= 1;
                end
                else if(nedge_key)
                    state <= WAIT;
                else 
                    state <= RELEASE_FILTER;    
        endcase
    end
    
    // time_20ms_reached 
    parameter MCNT = 1000_000;
    reg [29:0] counter;
    always@(posedge clk_i or negedge reset_n_i)
        if(!reset_n_i)
            counter <= 0;
        else if(state == RELEASE_FILTER || state == PRESS_FILTER) 
            counter <= counter + 1;
        else
            counter <= 0;
    
    assign time_20ms_reached = ( counter >= (MCNT - 1) );    
 
endmodule

三、功能仿真 

`timescale 1ns / 1ns
module key_filter_tb();
    reg u_clk_i,u_reset_n_i,u_key_i;
    wire u_press_key_flag_o,u_release_key_flag_o;
    
    key_filter U_key_filter_0(
        .clk_i(u_clk_i),
        .reset_n_i(u_reset_n_i),
        .key_i(u_key_i),
        .press_key_flag_o(u_press_key_flag_o),
        .release_key_flag_o(u_release_key_flag_o)
    );
    
    initial u_clk_i = 1;
    always #10 u_clk_i = ~u_clk_i; 
 
    initial begin
        u_reset_n_i = 0;
        u_key_i = 1;
        #201;
        u_reset_n_i = 1;
        #10_000_000;
        
        u_key_i = 0; #10_000_000;
        u_key_i = 1; #10_000_000;
        u_key_i = 0; #30_000_000;
        u_key_i = 1; #10_000_000;
        u_key_i = 0; #10_000_000;
        u_key_i = 1; #30_000_000;
        $stop;
    end
endmodule

四、综合优化

五、布局布线

六、时序仿真

七、板级调试