FPGA 综合笔记

仿真时阻塞赋值和非阻塞赋值

Use of Non-Blocking Assignment in Testbench : Verilog

Use of Non-Blocking Assignment in Testbench : Verilog - Stack Overflow

non-blocking assignment does not work as expected in Verilog

non-blocking assignment does not work as expected in Verilog - Electrical Engineering Stack Exchange

This is actually quite similar to a question I answered previously, but I will try to build up a canonical answer for this somewhat common issue.

In a zero-delay simulation like this, the test flip-flop has a setup time and a hold time of zero:

```math

Tsetup=Thold=0

```

What this means is that the instant the sensitive clock edge occurs, the output is updated, regardless of what happened immediately before or after that instant. This is not like real hardware which would usually have a non-zero