基于E310的纯逻辑代码实现AD9361射频收发_antsdr e310

本项目基于微相科技的E310平台实现AD9361的射频收发功能。采用纯逻辑控制的方式，不需要PS参与。实现了用VIO控制收发使能，发射功率，收发频率，数据接口时序控制，接收增益，BIST测试等功能。

顶层代码如下：

module antsdr_e310(

	input			FPGA_GCLK1,

	output			VCRX1_H,
	output			VCRX1_L,
	output			VCTX1_L,
	output			VCTX1_H,
	output			VCRX2_L,
	output			VCRX2_H,
	output			VCTX2_H,
	output			VCTX2_L,

	input			DATA_CLK_P,
	input			DATA_CLK_N,
	input			RX_FRAME_P,
	input			RX_FRAME_N,
	input	[5:0]	RX_D_P,
	input	[5:0]	RX_D_N,
	output			FB_CLK_P,
	output			FB_CLK_N,
	output			TX_FRAME_P,
	output			TX_FRAME_N,
	output	[5:0]	TX_D_P,
	output	[5:0]	TX_D_N,	
	output			RESETB,
	output			ENABLE,
	output			TXNRX,
	output			SPI_CLK,
	output			SPI_ENB,
	output			SPI_DI,
	input			SPI_DO,
	output			ENAGC,
	output			SYNC_IN,
	input	[7:0]	CTRL_OUT,
	output	[3:0]	CTRL_IN
);
	
	//AD9361 config clock and init states
	wire	        clk_80m;
	wire	        rst_n;
	wire	        init_done;
	wire			bb_pll_lock;
	wire			rx_pll_lock;
	wire			tx_pll_lock;

	//ad9361 data interface top
	wire            sample_clk;
    wire            lock_out;
    wire      		dac_valid; //always set to 1
	wire	[11:0]  dac_data_i1,dac_data_q1,dac_data_i2,dac_data_q2;
	wire 	 		adc_valid; //always 1
	wire 	[11:0] 	adc_data_i1,adc_data_q1,adc_data_i2,adc_data_q2;
	
	wire	[7:0]	mgc1_value,mgc2_value;
	wire	[32:0]	tx_lo_freq,rx_lo_freq;
	wire	[7:0]	reg006,reg007;
	wire	[8:0]	tx1_att,tx2_att;
	
	assign SYNC_IN = 0;

	clk_wiz_1 clk_wiz_1_inst(
	  .clk_out1(clk_80m),
	  .reset(1'b0),
	  .locked(rst_n),
	  .clk_in1(FPGA_GCLK1));	
	
	vio_top vio_top_inst(
		.clk		(clk_80m		),
		.probe_in0	(init_done		),
		.probe_in1	(bb_pll_lock	),
		.probe_in2	(rx_pll_lock	),
		.probe_in3	(tx_pll_lock	),		
		.probe_out0	(mgc1_value		),
		.probe_out1	(mgc2_value		), 
		.probe_out2	(tx_lo_freq		),
		.probe_out3	(rx_lo_freq		),
		.probe_out4	(bist_rx		),
		.probe_out5	(bist_loop		),
		.probe_out6	(reg006			),
		.probe_out7	(reg007			),
		.probe_out8	(tx_on			),
		.probe_out9	(rx_on			),
		.probe_out10(tx1_att		),
		.probe_out11(tx2_att		));
    
    ad9361_config ad9361_config_inst (
        .clk            (clk_80m            ),
        .rst_n          (rst_n		        ),
        .spi_clk        (SPI_CLK            ),
        .spi_csn        (SPI_ENB            ),
        .spi_miso       (SPI_DO             ),
        .spi_mosi       (SPI_DI             ),
		.txnrx		    (TXNRX              ),
		.enable		    (ENABLE             ),	
        .init_done      (init_done          ),
		.chip_rst_n	    (RESETB             ),
        .mgc1_value     (mgc1_value        	),
		.mgc2_value     (mgc2_value        	),
		.tx_lo_freq		(tx_lo_freq			),
		.rx_lo_freq		(rx_lo_freq			),		
		.bist_rx	    (bist_rx			),
        .bist_loop	    (bist_loop			),
		.reg006		    (reg006			    ),
		.reg007		    (reg007			    ),
		.tx_fast_lock	(1'b0				),
		.rx_fast_lock	(1'b0				),
		.tx_on			(tx_on				),
		.rx_on			(rx_on				),
		.bb_pll_lock	(bb_pll_lock		),
		.rx_pll_lock	(rx_pll_lock		),
		.tx_pll_lock	(tx_pll_lock		),
		.tx1_att		(tx1_att			),
		.tx2_att		(tx2_att			)
	);   

    //数据接口
	ad9361_data ad9361_data_inst (
		.sample_clk		(sample_clk			),
		.lock_out       (lock_out			),
		.rx_clk_in_p	(DATA_CLK_P	    	),
		.rx_clk_in_n	(DATA_CLK_N	    	),
		.rx_frame_in_p	(RX_FRAME_P	    	),
		.rx_frame_in_n	(RX_FRAME_N	    	),
		.rx_data_in_p	(RX_D_P	    		),
		.rx_data_in_n	(RX_D_N	    		),
		.tx_clk_out_p	(FB_CLK_P	    	),
		.tx_clk_out_n	(FB_CLK_N	    	),
		.tx_frame_out_p	(TX_FRAME_P	    	),
		.tx_frame_out_n	(TX_FRAME_N	    	),
		.tx_data_out_p	(TX_D_P	    		),
		.tx_data_out_n	(TX_D_N	    		),
		.adc_valid		(adc_valid		    ),
		.adc_data_i1	(adc_data_i1	    ),
		.adc_data_q1	(adc_data_q1	    ),
		.adc_data_i2	(adc_data_i2	    ),
		.adc_data_q2	(adc_data_q2	    ),
		.dac_valid		(dac_valid			),
		.dac_data_i1	(dac_data_i1		),
		.dac_data_q1	(dac_data_q1		),
		.dac_data_i2	(dac_data_i2		),
		.dac_data_q2	(dac_data_q2		));
		
    /************************发送测试波形**********************/
    // ad9361 TX test src
	tx_test_src tx_test_src_inst(
		.rst_n		(lock_out		),
		.sample_clk	(sample_clk		),
		.dac_valid	(dac_valid		),
		.dac_data_i1(dac_data_i1	),
		.dac_data_q1(dac_data_q1	),
		.dac_data_i2(dac_data_i2	),
		.dac_data_q2(dac_data_q2	));

	ila_adda ila_adda_inst(
		.clk	(sample_clk		),
		.probe0	(adc_data_i1	),
		.probe1	(adc_data_q1	),
		.probe2	(adc_data_i2	),
		.probe3	(adc_data_q2	),
		.probe4	(dac_data_i1	),
		.probe5	(dac_data_q1	),
		.probe6	(dac_data_i2	),
		.probe7	(dac_data_q2	),
		.probe8 (adc_valid		));

/********************RF SPD*************************/
	assign VCTX1_H = 1;	
	assign VCTX2_H = 1;
	assign VCTX1_L = 0;
	assign VCTX2_L = 0;	
	
	assign VCRX1_H = 1;
	assign VCRX2_H = 1;	
	assign VCRX1_L = 0; 
	assign VCRX2_L = 0;	
	  

endmodule

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测试结果如图