
`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2024/02/24 14:18:11
// Design Name: 
// Module Name: Check_timing
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//
 
 
module Check_timing(clk1,clk2,clk3,rst,d1,d2,S,CLKIN1,CLKIN2,CLKINSEL,CLKFBIN,CLKFBOUT,o_clk,o_lut,O,Q1,Q2,Q3,out_syn,pll_out,ff2);
input clk1,clk2,clk3,rst,d1,S;
input [4:0] d2;
input CLKIN1,CLKIN2,CLKINSEL,CLKFBIN;
output O,Q1,Q2,Q3,out_syn,pll_out,CLKFBOUT,o_clk,o_lut;
reg ff1,pll_ff1,pll_ff2,ff_syn;
output reg [4:0] ff2;
wire o_fdce;
 
 
 
always@(posedge clk1,negedge rst)
     if(!rst)
     begin
         ff1<=1'b0;
         ff2<=1'b0;
     end
     else begin
         ff1<=d1;
         ff2<=d2;
     end
//constant_clock
   (*DONT_TOUCH="YES"*)LUT2 #(
      .INIT(4'b0101)  // Specify LUT Contents
   ) LUT2_inst4 (
      .O(o_lut),   // LUT general output
      .I0(clk3),// LUT input
      .I1(d1) // LUT input
   );
   (*DONT_TOUCH="YES"*) FDCE #(
      .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
   ) FDCE_inst (
      .Q(o_clk),      // 1-bit Data output
      .C(clk3),      // 1-bit Clock input
      .CE(S),    // 1-bit Clock enable input
      .CLR(rst),  // 1-bit Asynchronous clear input
      .D(d1)       // 1-bit Data input
   );
 
 assign sum12=ff1+o_fdce;
 always@(posedge clk2,negedge rst)
     if(!rst)
         ff_syn<=1'b0;
     else begin
         ff_syn<=sum12;
     end
 assign out_syn=ff_syn;
//latch_loop
LDCE #(
      .INIT(1'b1)
   )
   LDCE_inst2 (
      .Q(Q2),     // 1-bit output: Data
      .CLR(rst), // 1-bit input: Asynchronous clear
      .D(Q3),     // 1-bit input: Data
      .G(1'b1),     // 1-bit input: Gate
      .GE(S)    // 1-bit input: Gate enable
   );
   LUT1 #(
      .INIT(2'b01)  // Specify LUT Contents
   ) LUT1_inst3 (
      .O(Q3),   // LUT general output
      .I0(Q2)  // LUT input
   );
 
//loop
LUT1 #(
      .INIT(2'b01)  // Specify LUT Contents
   ) LUT1_inst1 (
      .O(O),   // LUT general output
      .I0(Q0)  // LUT input
   );
LUT1 #(
      .INIT(2'b01)  // Specify LUT Contents
   ) LUT1_inst2 (
      .O(Q0),   // LUT general output
      .I0(O)  // LUT input
   );
 
 PLLE2_ADV #(
      .BANDWIDTH("OPTIMIZED"),  // OPTIMIZED, HIGH, LOW
      .CLKFBOUT_MULT(8),        // Multiply value for all CLKOUT, (2-64)
      .CLKFBOUT_PHASE(0.0),     // Phase offset in degrees of CLKFB, (-360.000-360.000).
      // CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
      .CLKIN1_PERIOD(0.0),
      .CLKIN2_PERIOD(0.0),
      // CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
      .CLKOUT0_DIVIDE(1),
      .CLKOUT1_DIVIDE(2),
      .CLKOUT2_DIVIDE(4),
      .CLKOUT3_DIVIDE(5),
      .CLKOUT4_DIVIDE(1),
      .CLKOUT5_DIVIDE(1),
      // CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
      .CLKOUT0_DUTY_CYCLE(0.4),
      .CLKOUT1_DUTY_CYCLE(0.5),
      .CLKOUT2_DUTY_CYCLE(0.5),
      .CLKOUT3_DUTY_CYCLE(0.5),
      .CLKOUT4_DUTY_CYCLE(0.5),
      .CLKOUT5_DUTY_CYCLE(0.5),
      // CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
      .CLKOUT0_PHASE(0.0),
      .CLKOUT1_PHASE(0.0),
      .CLKOUT2_PHASE(0.0),
      .CLKOUT3_PHASE(0.0),
      .CLKOUT4_PHASE(0.0),
      .CLKOUT5_PHASE(0.0),
      .COMPENSATION("ZHOLD"),   // ZHOLD, BUF_IN, EXTERNAL, INTERNAL
      .DIVCLK_DIVIDE(1),        // Master division value (1-56)
      // REF_JITTER: Reference input jitter in UI (0.000-0.999).
      .REF_JITTER1(0.0),
      .REF_JITTER2(0.0),
      .STARTUP_WAIT("FALSE")    // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
   )
   PLLE2_ADV_inst (
      // Clock Outputs: 1-bit (each) output: User configurable clock outputs
      .CLKOUT0(CLKOUT0),   // 1-bit output: CLKOUT0
      .CLKOUT1(CLKOUT1),   // 1-bit output: CLKOUT1
      .CLKOUT2(CLKOUT2),   // 1-bit output: CLKOUT2
      // Feedback Clocks: 1-bit (each) output: Clock feedback ports
      .CLKFBOUT(), // 1-bit output: Feedback clock
 
      // Clock Inputs: 1-bit (each) input: Clock inputs
      .CLKIN1(CLKIN1),     // 1-bit input: Primary clock
      .CLKIN2(CLKIN2),     // 1-bit input: Secondary clock
      // Control Ports: 1-bit (each) input: PLL control ports
      .CLKINSEL(CLKINSEL), // 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2
      .RST(rst),           // 1-bit input: Reset
      // Feedback Clocks: 1-bit (each) input: Clock feedback ports
      .CLKFBIN(CLKFBIN)    // 1-bit input: Feedback clock
   );
   // End of PLLE2_ADV_inst instantiation
 
always@(posedge CLKOUT0,negedge rst)
    if(!rst)
    begin
        pll_ff1<=1'b0;
        pll_ff2<=1'b0;
    end
    else begin
        pll_ff1<=d1;
        pll_ff2<=S;
    end
assign pll_out=pll_ff1*pll_ff2;
 
wire sum12;
assign sum12=pll_ff1+pll_ff2;
always@(posedge CLKOUT1,negedge rst)
    if(!rst)
        ff_syn<=1'b0;
    else begin
        ff_syn<=sum12;
    end
assign out_syn=ff_syn;
endmodule

2.3 时序约束


create_clock -period 4.000 -name clk1 -waveform {0.000 2.000} -add [get_ports clk1]
create_clock -period 6.000 -name clk1_a -waveform {0.000 3.000} -add [get_ports clk1]
create_clock -period 6.000 -name clkin1 -waveform {0.000 3.000} -add [get_ports CLKIN1]
create_generated_clock -name gen_clk -source [get_pins PLLE2_ADV_inst/CLKOUT1] -multiply_by 2 -add -master_clock clkin2 [get_pins PLLE2_ADV_inst/CLKOUT0]
set_input_delay -clock [get_clocks clk1] -rise 0.111 [get_ports {{d2[0]} {d2[1]}}]
set_output_delay -clock [get_clocks clk1] -min 0.222 [get_ports {ff2[0]}]
create_clock -period 9.000 -name clkin2 -waveform {0.000 4.500} -add [get_ports CLKIN2]
create_generated_clock -name gen_clk -source [get_ports CLKIN1] -multiply_by 2 -add -master_clock clkin2 [get_pins PLLE2_ADV_inst/CLKOUT1]
create_clock -period 10.000 -name clk3 -waveform {0.000 5.000} -add [get_ports clk3]
set_case_analysis 1 [get_ports clk3]