Xilinx VU+系列多DIE FPGA约束

作者：爱喝兽奶帝天荒 | 2024-08-16 12:16:29

踩

die fpga

Xilinx VU+系列多DIE FPGA约束

1、VU+ 多DIE FPGA CELL位置约束
create_pblock pblock_SLR0
set_property IS_SOFT false [get_pblocks pblock_SLR0]
resize_pblock pblock_SRL0 -add SLR0:SLR0
add_cells_to_pblock pblock_SLR0 [get_cells [list U0_xxxx]]
add_cells_to_pblock pblock_SLR0 [get_cells [list U1_xxxx]]
add_cells_to_pblock pblock_SLR0 [get_cells [list U2_xxxx]]
add_cells_to_pblock pblock_SLR0 [get_cells [list UN_xxxx]]

create_pblock pblock_SLR1
set_property IS_SOFT false [get_pblocks pblock_SLR1]
resize_pblock pblock_SRL1 -add SLR1:SLR1
add_cells_to_pblock pblock_SLR1 [get_cells [list U10_xxxx]]
add_cells_to_pblock pblock_SLR1 [get_cells [list U11_xxxx]]
add_cells_to_pblock pblock_SLR1 [get_cells [list U12_xxxx]]
add_cells_to_pblock pblock_SLR1 [get_cells [list U1N_xxxx]]

create_pblock pblock_SLR2
set_property IS_SOFT false [get_pblocks pblock_SLR2]
resize_pblock pblock_SRL2 -add SLR2:SLR2
add_cells_to_pblock pblock_SLR2 [get_cells [list U20_xxxx]]
add_cells_to_pblock pblock_SLR2 [get_cells [list U21_xxxx]]
add_cells_to_pblock pblock_SLR2 [get_cells [list U22_xxxx]]
add_cells_to_pblock pblock_SLR2 [get_cells [list U2N_xxxx]]

2、跨DIE laguna寄存器约束
跨die的资源需要使用laguna专用寄存器做约束处理。
set_property USER_SLL_REG true [get_cells {U0_cdc_top_inst/tvalid_r_reg[]}]
set_property USER_SLL_REG true [get_cells {U0_cdc_top_inst/tdata_r_reg[]}]
set_property USER_SLL_REG true [get_cells {U0_cdc_top_inst/tlast_r_reg[]}]
set_property USER_SLL_REG true [get_cells {U0_cdc_top_inst/tuser_r_reg[]}]
set_property USER_SLL_REG true [get_cells {U0_cdc_top_inst/tready_r_reg[*]}]

声明：本文内容由网友自发贡献，不代表【wpsshop博客】立场，版权归原作者所有，本站不承担相应法律责任。如您发现有侵权的内容，请联系我们。转载请注明出处：https://www.wpsshop.cn/w/爱喝兽奶帝天荒/article/detail/988218