verilog 学习笔记——MULtiplexers 多路复用器_41多路复用器 verilog

1. 2-to-1 multiplexer

module top_module( 
    input a, b, sel,
    output out ); 
    assign out = (sel & b) | (~sel & a);	// Mux expressed as AND and OR
	
	// Ternary operator is easier to read, especially if vectors are used:
	// assign out = sel ? b : a;
 
   
endmodule

 2. 2-to-1 bus multiplexer

module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out );
    assign out = (sel==1)?b:a;
    
    // The following doesn't work. Why?
    //  sel 只有一位，a和b 都是100位的
	// assign out = (sel & b) | (~sel & a);
 
endmodule

3. 9-to-1 multiplexer

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );
    always@(*)
        begin
            case(sel)
                4'b0000 : out = a ;
                4'b0001 : out = b ;
                4'b0010 : out = c ;
                4'b0011 : out = d ;
                4'b0100 : out = e ;
                4'b0101 : out = f ;
                4'b0110 : out = g ;
                4'b0111 : out = h ;
                4'b1000 : out = i ;
                default : out = 16'b1111111111111111;
            endcase
        end
   
endmodule

或者可以这样表达：

module top_module (
	input [15:0] a,
	input [15:0] b,
	input [15:0] c,
	input [15:0] d,
	input [15:0] e,
	input [15:0] f,
	input [15:0] g,
	input [15:0] h,
	input [15:0] i,
	input [3:0] sel,
	output logic [15:0] out
);
 
	// Case statements can only be used inside procedural blocks (always block)
	// This is a combinational circuit, so use a combinational always @(*) block.
	always @(*) begin
		out = '1;		// '1 is a special literal syntax for a number with all bits set to 1.
						// '0, 'x, and 'z are also valid.
						// I prefer to assign a default value to 'out' instead of using a
						// default case.
		case (sel)
			4'h0: out = a;
			4'h1: out = b;
			4'h2: out = c;
			4'h3: out = d;
			4'h4: out = e;
			4'h5: out = f;
			4'h6: out = g;
			4'h7: out = h;
			4'h8: out = i;
		endcase
	end
	
endmodule

4. 256-to-1 multiplexer

module top_module (
	input [255:0] in,
	input [7:0] sel,
	output  out
);
 
	// Select one bit from vector in[]. The bit being selected can be variable.
	assign out = in[sel];
	
endmodule

 5. 256-to-1 4-bit multiplexer

module top_module (
	input [1023:0] in,
	input [7:0] sel,
	output [3:0] out
);
 
	// We can't part-select multiple bits without an error, but we can select one bit at a time,
	// four times, then concatenate them together.
	assign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]};
 
	// Alternatively, "indexed vector part select" works better, but has an unfamiliar syntax:
	// assign out = in[sel*4 +: 4];		// Select starting at index "sel*4", then select a total width of 4 bits with increasing (+:) index number.
	// assign out = in[sel*4+3 -: 4];	// Select starting at index "sel*4+3", then select a total width of 4 bits with decreasing (-:) index number.
	// Note: The width (4 in this case) must be constant.
 
endmodule