HDLBits答案及学习过程_hdlbite答案及讲解

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Getting started

Getting started

module top_module( output one );

// Insert your code here
    assign one = [fixme];

endmodule

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Output Zero

module top_module(
    output zero
);// Module body starts after semicolon
	assign zero = 1'b0;
endmodule

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verilog Language

Basic

Simple wire

module top_module( input in, output out );

    assign out=in;
endmodule

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Four wires

module top_module( 
    input a,b,c,
    output w,x,y,z );
    assign w=a;
    assign x=b;
    assign y=b;
    assign z=c;

endmodule
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inverter

module top_module( input in, output out );
    
    assign out = ~in;

endmodule

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and gate

module top_module( 
    input a, 
    input b, 
    output out );
    
    assign out=a&b;

endmodule
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Nor gate

module top_module( 
    input a, 
    input b, 
    output out );
    assign out=~(a|b);
    

endmodule
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Xorgate

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = ~(a^b);

endmodule
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Declaring wire

`default_nettype none
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
    
    wire X,Y,Z;
    assign X=a&b;
    assign Y=c&d;
    assign Z=X|Y;
    assign out=Z;
    assign out_n=~Z;
 
endmodule
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7485 chip

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    
    wire d1,d2,e1,e2;
    assign d1=p1a&p1b&p1c;
    assign d2=p1e&p1f&p1d;
    assign p1y=d1|d2;
    
    assign e1=p2a&p2b;
    assign e2=p2c&p2d;
    assign p2y=e1|e2;
    
endmodule
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Vectors

Vectors

module top_module ( 
    input wire [2:0] vec,
    output wire [2:0] outv,
    output wire o2,
    output wire o1,
    output wire o0  ); // Module body starts after module declaration
    assign  outv= vec;
    assign  o2=vec[2];
    assign  o1=vec[1];
    assign  o0=vec[0];
    

endmodule
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Vector part select

module top_module( 
    input [31:0] in,
    output [31:0] out );
    assign out[31:24] = in[7:0];
    assign out[23:16] = in[15:8];
    assign out[15:8] = in[23:16];
    assign out[7:0] = in[31:24];
    
endmodule
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bitwise operators

module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);
    assign out_or_bitwise = a|b;
    assign out_or_logical=a||b;
    assign out_not[5:3]=~b;
    assign out_not[2:0]=~a;

endmodule
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Four_input gates

module top_module( 
    input [3:0] in,
    output out_and,
    output out_or,
    output out_xor
);
    assign out_and=∈
    assign out_or=|in;
    assign out_xor=^in;

endmodule
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Vectors concatenation operator

module top_module (
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z );//
	
    
    assign {w, x, y, z} = {a, b, c, d, e, f, 2'b11};

endmodule
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位拼接符的应用，可拼接向量和数，拼接过后为一个整体，方便处理.

Vectorr

module top_module( 
    input [7:0] in,
    output [7:0] out
);
    assign out={in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]};

endmodule

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采取一位一位的笨拙的方式来。

Vector4

module top_module (
    input [7:0] in,
    output [31:0] out );//

    assign out = {{ 24{in[7]}} , in[7:0] };

endmodule
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向量倍数位拼接符：{num{bits},other bits};

Vector5

solution1

module top_module (
    input a, b, c, d, e,
    output [24:0] out );//
	
    assign      out[24:20]=~{5{a}}^{a,b,c,d,e};
    assign      out[19:15]=~{5{b}}^{a,b,c,d,e};
    assign      out[14:10]=~{5{c}}^{a,b,c,d,e};
    assign      out[9:5]=~{5{d}}^{a,b,c,d,e};
    assign      out[4:0]= ~{5{e}}^{a,b,c,d,e};
endmodule
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solution2

module top_module (
	input a, b, c, d, e,
	output [24:0] out
);

	 assign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ {5{a,b,c,d,e}};
	
endmodule

~非运算具有最高优先级，这里的异或运算中发现~的运算顺序不影响结果（不进位加法）


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Modules hierarchy

Moudule

不同模块连接方式：by name/ by position
用名字比较繁琐，但清晰；用位置方便，但改变模块端口后，需要一同变化

Solution1

module top_module ( input a, input b, output out );
    mod_a instance1(a,b,out);
endmodule

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Solution2

module top_module ( input a, input b, output out );
    mod_a instance1(.out(out),.in1(a),.in2(b));
endmodule
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Module pos

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    mod_a ( out1, out2, a,b,c,d );

endmodule
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module_name

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    mod_a (  .out1(out1), .out2(out2), .in1(a), .in2(b), .in3(c), .in4(d));
endmodule
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括号外是引用模块的post name，括号内是外部模块的节点

Module Shift

module top_module ( input clk, input d, output q );
    wire a,b;
    my_dff s1( .clk(clk),.d(d), .q(a) );
    my_dff s2( .clk(clk),.d(a), .q(b) );
    my_dff s3( .clk(clk),.d(b), .q(q) );

endmodule

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用名字确实方便不少；