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- module ip_fifo(
- input sys_clk,
- input sys_rst_n
- );
-
- wire wrreq;
- wire [7:0] data;
- wire wrempty;
- wire wrfull;
- wire wrusedw;
-
- wire rdreq;
- wire [7:0] q;
- wire rdempty;
- wire rdfull;
- wire rdusedw;
-
-
-
- /****************************************
- main code
- ****************************************/
-
-
- fifo_rd u_fifo_rd(
- .sys_clk (sys_clk ),
- .sys_rst_n (sys_rst_n ),
-
- .rdreq (rdreq ),
- .data (q ),
- .rdempty (rdempty ),
- .rdfull (rdfull )
- );
-
- fifo_wr u_fifo_wr(
- //system clock and reset
- .sys_clk(sys_clk),
- .sys_rst_n(sys_rst_n),
-
- //user interface
- .wrempty(wrempty),
- .wrfull(wrfull),
- .data(data),
- .wrreq(wrreq) // write request
- );
-
- fifo fifo_inst (
-
-
-
- .wrclk ( sys_clk ),
- .wrreq ( wrreq ),
- .data ( data ),
- .wrempty ( wrempty ),
- .wrfull ( wrfull ),
- .wrusedw ( wrusedw ),
-
- .rdclk ( sys_clk ),
- .rdreq ( rdreq),
- .q ( q),
- .rdempty ( rdempty ),
- .rdfull ( rdfull),
- .rdusedw ( rdusedw )
-
- );
-
-
-
- endmodule
- module fifo_wr(
- //system clock and reset
- input sys_clk,
- input sys_rst_n,
-
- //user interface
- input wrempty, // ip core cause
- input wrfull, // ip core cause
- output reg [7:0] data,
- output wrreq // write request
- );
-
- //reg define
- reg wrreq_t;
- reg [1:0] flow_cnt;
-
- /**************************************
- ** main code
- **************************************/
- assign wrreq=~wrfull & wrreq_t; //fifo not full and write request
-
- always @(posedge sys_clk or negedge sys_rst_n) begin
- if(!sys_rst_n)begin
- wrreq_t<=1'b0;
- data<=8'd0;
- flow_cnt<=2'd0;
- end
- else begin
- case(flow_cnt)
-
- 2'd0: begin
- if(wrempty)begin
- wrreq_t<=1'b1;
- flow_cnt<=flow_cnt+1'b1;
- end
- else
- flow_cnt<=flow_cnt;
- end
- /
- 2'd1: begin
- if(wrfull)begin
- wrreq_t<=1'b0;
- data<=8'd0;
- flow_cnt<=2'd0;
- end
- else begin
- wrreq_t<=1'b1;
- data<=data+1'b1;
- end
- end
- /*************************************/
- default : flow_cnt<=2'd0;
- endcase
- end
-
- end
- endmodule
- module fifo_rd(
- input sys_clk,
- input sys_rst_n,
-
- input [7:0] data,
- input rdfull,
- input rdempty,
- output rdreq //
- );
-
- //reg define
- reg rdreq_t;
- reg [7:0] data_fifo;
- reg [1:0] flow_cnt ;
-
- assign rdreq=~rdempty & rdreq_t;
-
- //fifo read data
- always @(posedge sys_clk or negedge sys_rst_n)begin
- if(!sys_rst_n)begin
- rdreq_t<=1'b0;
- data_fifo<=8'd0;
- end
-
- else begin
- case(flow_cnt)
- 2'd0:begin
-
- if(rdfull)begin
- rdreq_t<=1'b1;
- flow_cnt<=flow_cnt+1'b1;
- end
- else
- flow_cnt<=flow_cnt;
-
- end
-
- 2'd1:begin
-
- if(rdempty)begin
- rdreq_t<=1'b0;
- data_fifo<=8'd0;
- flow_cnt<=2'd0;
- end
- else begin
- rdreq_t<=1'b1;
- data_fifo<=data;
- end
-
- end
- default: flow_cnt<=2'd0;
- endcase
- end
- end
- endmodule
例化IP core 详情参见正点原子开拓者开发板手册
在实验过程中主要注意写请求和读请求的产生,还有读模块和写模块与IP core的配合关系 以及读写的转换时刻。
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